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| www.motorola.com/semiconductors m?core microcontrollers mmc2114/d rev. 1, 4/2002 mmc2114 advance information MMC2113 mmc2112 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . mmc2114 ? MMC2113 mmc2112 ? rev. 1.0 advance information motorola 3 mmc2114 MMC2113 mmc2112 advance information to provide the most up-to-date information, the revision of our documents on the world wide web will be the most current. your printed copy may be an earlier revision. to verify you have the latest information available, refer to: http://www.motorola.com/semiconductors/ the following revision history table summarizes changes contained in this document. for your convenience, the page number designators have been linked to the appropriate location. motorola and the stylized m logo are registered trademarks of motorola, inc. digitaldna is a trademark of motorola, inc. ? motorola, inc., 2002 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . advance information mmc2114 ? MMC2113 mmc2112 ? rev. 1.0 4 motorola advance information revision history date revision level description page number(s) march, 2002 n/a original release n/a april, 2002 1.0 figure 4-4. chip identification register (cir) ? corrrected reset condition for bits 11 and 8 131 20.9.3 show strobe (shs) ? corrected description in first paragraph 542 23.5 junction temperature determination ? changed subsection title from power dissipation to junction temperature determination 614 23.7 dc electrical specifications ? under operating supply current, external oscillator clocking changed stop mode maximum value from 10 a to 200 a 616 23.7 dc electrical specifications ? under operating supply current, crystal/pll clock changed maximum value for osc and pll disabled from 150 a to 200 a 617 appendix a. security ? updated for clarity 649 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . mmc2114 MMC2113 mmc2112 ? rev. 1.0 advance information motorola list of sections 5 advance information ? mmc2114, MMC2113, and mmc2112 list of sections section 1. general description . . . . . . . . . . . . . . . . . . . . 45 section 2. system memory map . . . . . . . . . . . . . . . . . . . 53 section 3. signal description. . . . . . . . . . . . . . . . . . . . . . 95 section 4. chip configuration module (ccm) . . . . . . . 121 section 5. reset controller module. . . . . . . . . . . . . . . . 139 section 6. power management . . . . . . . . . . . . . . . . . . . 155 section 7. mcore m210 central processor unit (cpu) . . . . . . . . . . . . . . . . . . . . . . . . . . 165 section 8. interrupt controller module . . . . . . . . . . . . . 177 section 9. static random access memory (sram) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 199 section 10. second generation flash for mcore (sgfm) . . . . . . . . . . . . . . . . . . 203 section 11. clock module . . . . . . . . . . . . . . . . . . . . . . . . 243 section 12. ports module . . . . . . . . . . . . . . . . . . . . . . . . 271 section 13. edge port module (eport) . . . . . . . . . . . . 285 section 14. watchdog timer module . . . . . . . . . . . . . . 295 section 15. programmable interrupt timer modules (pit1 and pit2) . . . . . . . . . . . . . . 305 section 16. timer modules (tim1 and tim2). . . . . . . . . 317 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . advance information mmc2114 MMC2113 mmc2112 ? rev. 1.0 6 list of sections motorola list of sections section 17. serial communications interface modules (sci1 and sci2) . . . . . . . . . . . . . . 353 section 18. serial peripheral interface module (spi) . . . . . . . . . . . . . . . . . . . . . . . . 397 section 19. queued analog-to-digital converter (qadc) . . . . . . . . . . . . . . . . . . . . 425 section 20. external bus interface module (ebi) . . . . . 527 section 21. chip select module . . . . . . . . . . . . . . . . . . . 547 section 22. jtag test access port and once . . . . . . 559 section 23. preliminary electrical specifications . . . . 611 section 24. mechanical specifications . . . . . . . . . . . . . 639 section 25. ordering information . . . . . . . . . . . . . . . . . 647 appendix a. security . . . . . . . . . . . . . . . . . . . . . . . . . . . 649 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . mmc2114 MMC2113 mmc2112 ? rev. 1.0 advance information motorola table of contents 7 advance information ? mmc2114, MMC2113, and mmc2112 table of contents section 1. general description 1.1 contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .45 1.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .45 1.3 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .46 1.4 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 section 2. system memory map 2.1 contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .53 2.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .53 2.3 address map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .54 2.4 register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .57 section 3. signal description 3.1 contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .95 3.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .97 3.3 package pinout summary . . . . . . . . . . . . . . . . . . . . . . . . . . . .98 3.4 chip specific implementation signal issues. . . . . . . . . . . . . .109 3.4.1 rstout signal functions . . . . . . . . . . . . . . . . . . . . . . . . .109 3.4.2 int signal functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . .110 3.4.3 serial peripheral interface (spi) pin functions . . . . . . . . .110 3.4.4 serial communications interface (sci1 and sci2) pin functions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .111 3.4.5 timer 1 and timer 2 pin functions . . . . . . . . . . . . . . . . . .112 3.4.6 queued analog-to-digital converter (qadc) pin functions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .112 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . advance information mmc2114 MMC2113 mmc2112 ? rev. 1.0 8 table of contents motorola table of contents 3.5 signal descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .113 3.5.1 reset signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .113 3.5.1.1 reset in (reset ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . .113 3.5.1.2 reset out (rstout ). . . . . . . . . . . . . . . . . . . . . . . . . . .113 3.5.2 phase-lock loop (pll) and clock signals . . . . . . . . . . . .113 3.5.2.1 external clock in (extal) . . . . . . . . . . . . . . . . . . . . . . .113 3.5.2.2 crystal (xtal) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .114 3.5.2.3 clock out (clkout) . . . . . . . . . . . . . . . . . . . . . . . . . . . 114 3.5.2.4 pll enable (pllen) . . . . . . . . . . . . . . . . . . . . . . . . . . .114 3.5.3 external memory interface signals . . . . . . . . . . . . . . . . . .114 3.5.3.1 data bus (d[31:0]) . . . . . . . . . . . . . . . . . . . . . . . . . . . . .114 3.5.3.2 show cycle strobe (shs ) . . . . . . . . . . . . . . . . . . . . . . .114 3.5.3.3 transfer acknowledge (ta ) . . . . . . . . . . . . . . . . . . . . . .115 3.5.3.4 transfer error acknowledge (tea ) . . . . . . . . . . . . . . . .115 3.5.3.5 emulation mode chip selects (cse[1:0]) . . . . . . . . . . .115 3.5.3.6 transfer code (tc[2:0]) . . . . . . . . . . . . . . . . . . . . . . . . .115 3.5.3.7 read/write (r/w ). . . . . . . . . . . . . . . . . . . . . . . . . . . . . .115 3.5.3.8 address bus (a[22:0]) . . . . . . . . . . . . . . . . . . . . . . . . . .115 3.5.3.9 enable byte (eb[3:0] ) . . . . . . . . . . . . . . . . . . . . . . . . . .116 3.5.3.10 chip select (cs[3:0] ) . . . . . . . . . . . . . . . . . . . . . . . . . . .116 3.5.3.11 output enable (oe ) . . . . . . . . . . . . . . . . . . . . . . . . . . . .116 3.5.4 edge port signals. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .116 3.5.4.1 external interrupts (int[7:6] ) . . . . . . . . . . . . . . . . . . . . .116 3.5.4.2 external interrupts (int[5:2] ) . . . . . . . . . . . . . . . . . . . . .116 3.5.4.3 external interrupts (int[1:0] ) . . . . . . . . . . . . . . . . . . . . .116 3.5.5 serial peripheral interface module signals . . . . . . . . . . . .117 3.5.5.1 master out/slave in (mosi). . . . . . . . . . . . . . . . . . . . . .117 3.5.5.2 master in/slave out (miso). . . . . . . . . . . . . . . . . . . . . .117 3.5.5.3 serial clock (sck) . . . . . . . . . . . . . . . . . . . . . . . . . . . . .117 3.5.5.4 slave select (ss ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .117 3.5.6 serial communications interface module signals . . . . . . .117 3.5.6.1 receive data (rxd1 and rxd2) . . . . . . . . . . . . . . . . . .117 3.5.6.2 transmit data (txd1 and txd2). . . . . . . . . . . . . . . . . .118 3.5.7 timer signals (icoc1[3:0] and icoc2[3:0]) . . . . . . . . . . .118 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . table of contents mmc2114 MMC2113 mmc2112 ? rev. 1.0 advance information motorola table of contents 9 3.5.8 analog-to-digital converter signals . . . . . . . . . . . . . . . . . .118 3.5.8.1 analog inputs (pqa[4:3], pqa[1:0], and pqb[3:0]) . . . .118 3.5.8.2 analog reference (v rh and v rl ) . . . . . . . . . . . . . . . . .118 3.5.8.3 analog supply (v dda and v ssa ) . . . . . . . . . . . . . . . . . .118 3.5.8.4 positive supply (v ddh ) . . . . . . . . . . . . . . . . . . . . . . . . .118 3.5.9 debug and emulation support signals . . . . . . . . . . . . . . .119 3.5.9.1 test reset (trst) . . . . . . . . . . . . . . . . . . . . . . . . . . . . .119 3.5.9.2 test clock (tclk) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119 3.5.9.3 test mode select (tms) . . . . . . . . . . . . . . . . . . . . . . . .119 3.5.9.4 test data input (tdi) . . . . . . . . . . . . . . . . . . . . . . . . . . .119 3.5.9.5 test data output (tdo). . . . . . . . . . . . . . . . . . . . . . . . .119 3.5.9.6 debug event (de ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . .119 3.5.10 test signal (test). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .120 3.5.11 power and ground signals . . . . . . . . . . . . . . . . . . . . . . . .120 3.5.11.1 standby power (v stby ) . . . . . . . . . . . . . . . . . . . . . . . . .120 3.5.11.2 positive supply (v dd ). . . . . . . . . . . . . . . . . . . . . . . . . . .120 3.5.11.3 ground (v ss ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .120 section 4. chip configuration module (ccm) 4.1 contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .121 4.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .122 4.3 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .122 4.4 modes of operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .122 4.4.1 master mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .123 4.4.2 single-chip mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .123 4.4.3 emulation mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .123 4.4.4 factory access slave test (fast) mode . . . . . . . . . . . . .123 4.5 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124 4.6 signal descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .124 4.7 memory map and registers . . . . . . . . . . . . . . . . . . . . . . . . . .125 4.7.1 programming model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .125 4.7.2 memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .126 4.7.3 register descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . .126 4.7.3.1 chip configuration register . . . . . . . . . . . . . . . . . . . . . .126 4.7.3.2 reset configuration register . . . . . . . . . . . . . . . . . . . . .129 4.7.3.3 chip identification register . . . . . . . . . . . . . . . . . . . . . .131 4.7.3.4 chip test register . . . . . . . . . . . . . . . . . . . . . . . . . . . . .132 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . advance information mmc2114 MMC2113 mmc2112 ? rev. 1.0 10 table of contents motorola table of contents 4.8 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .133 4.8.1 reset configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .133 4.8.2 chip mode selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . .135 4.8.3 boot device selection . . . . . . . . . . . . . . . . . . . . . . . . . . . .135 4.8.4 output pad strength configuration . . . . . . . . . . . . . . . . . .137 4.8.5 clock mode selection. . . . . . . . . . . . . . . . . . . . . . . . . . . . .137 4.8.6 internal flash configuration . . . . . . . . . . . . . . . . . . . . . .138 4.9 reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .138 4.10 interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .138 section 5. reset controller module 5.1 contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .139 5.2 overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .140 5.3 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .140 5.4 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141 5.5 signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .141 5.5.1 reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .142 5.5.2 rstout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .142 5.6 memory map and registers . . . . . . . . . . . . . . . . . . . . . . . . . .142 5.6.1 reset control register . . . . . . . . . . . . . . . . . . . . . . . . . . . .143 5.6.2 reset status register . . . . . . . . . . . . . . . . . . . . . . . . . . . .145 5.7 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .147 5.7.1 reset sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .147 5.7.1.1 power-on reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .148 5.7.1.2 external reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .148 5.7.1.3 watchdog timer reset . . . . . . . . . . . . . . . . . . . . . . . . .148 5.7.1.4 loss of clock reset . . . . . . . . . . . . . . . . . . . . . . . . . . . .148 5.7.1.5 loss of lock reset . . . . . . . . . . . . . . . . . . . . . . . . . . . .149 5.7.1.6 software reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .149 5.7.1.7 lvd reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .149 5.7.2 reset control flow. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .149 5.7.2.1 synchronous reset requests . . . . . . . . . . . . . . . . . . . .151 5.7.2.2 internal reset request . . . . . . . . . . . . . . . . . . . . . . . . .151 5.7.2.3 power-on reset/low-voltage detect reset . . . . . . . . .151 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . table of contents mmc2114 MMC2113 mmc2112 ? rev. 1.0 advance information motorola table of contents 11 5.7.3 concurrent resets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .152 5.7.3.1 reset flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .152 5.7.3.2 reset status flags. . . . . . . . . . . . . . . . . . . . . . . . . . . . .152 section 6. power management 6.1 contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .155 6.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .156 6.3 low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .156 6.3.1 run mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .156 6.3.2 wait mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .157 6.3.3 doze mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .157 6.3.4 stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .157 6.3.5 peripheral shut down . . . . . . . . . . . . . . . . . . . . . . . . . . . .157 6.4 peripheral behavior in low-power modes . . . . . . . . . . . . . . .158 6.4.1 reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .158 6.4.2 clocks. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158 6.4.3 once . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .159 6.4.4 jtag . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .160 6.4.5 interrupt controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .160 6.4.6 edge port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .160 6.4.7 random-access memory (ram) . . . . . . . . . . . . . . . . . . . .160 6.4.8 flash . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .161 6.4.9 queued analog-to-digital converter (qadc) . . . . . . . . . .161 6.4.10 watchdog timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .161 6.4.11 programmable interrupt timers (pit1 and pit2). . . . . . . .162 6.4.12 serial peripheral interface (spi). . . . . . . . . . . . . . . . . . . . .162 6.4.13 serial communication interfaces (sci1 and sci2) . . . . . .162 6.4.14 timers (tim1 and tim2). . . . . . . . . . . . . . . . . . . . . . . . . . .163 6.5 summary of peripheral state during low-power modes . . . .163 section 7. m core m210 central processor unit (cpu) 7.1 contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .165 7.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .165 7.3 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .166 7.4 microarchitecture summary . . . . . . . . . . . . . . . . . . . . . . . . . .167 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . advance information mmc2114 MMC2113 mmc2112 ? rev. 1.0 12 table of contents motorola table of contents 7.5 programming model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .169 7.6 data format summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .171 7.7 operand addressing capabilities . . . . . . . . . . . . . . . . . . . . . .172 7.8 instruction set overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . .172 section 8. interrupt controller module 8.1 contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .177 8.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .178 8.3 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .178 8.4 low-power mode operation . . . . . . . . . . . . . . . . . . . . . . . . . .178 8.5 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 179 8.6 external signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .179 8.7 memory map and registers . . . . . . . . . . . . . . . . . . . . . . . . . .179 8.7.1 memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .180 8.7.2 registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .181 8.7.2.1 interrupt control register. . . . . . . . . . . . . . . . . . . . . . . .181 8.7.2.2 interrupt status register . . . . . . . . . . . . . . . . . . . . . . . .183 8.7.2.3 interrupt force registers . . . . . . . . . . . . . . . . . . . . . . . .184 8.7.2.4 interrupt pending register . . . . . . . . . . . . . . . . . . . . . . .186 8.7.2.5 normal interrupt enable register. . . . . . . . . . . . . . . . . .187 8.7.2.6 normal interrupt pending register. . . . . . . . . . . . . . . . .188 8.7.2.7 fast interrupt enable register . . . . . . . . . . . . . . . . . . . .189 8.7.2.8 fast interrupt pending register . . . . . . . . . . . . . . . . . . .190 8.7.2.9 priority level select registers . . . . . . . . . . . . . . . . . . . . 191 8.8 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .191 8.8.1 interrupt sources and prioritization . . . . . . . . . . . . . . . . . .192 8.8.2 fast and normal interrupt requests . . . . . . . . . . . . . . . . .192 8.8.3 autovectored and vectored interrupt requests . . . . . . . . .193 8.8.4 interrupt configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . .195 8.8.4.1 cpu configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . .195 8.8.4.2 interrupt controller configuration. . . . . . . . . . . . . . . . . .195 8.8.4.3 interrupt source configuration . . . . . . . . . . . . . . . . . . . .196 8.8.5 interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .196 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . table of contents mmc2114 MMC2113 mmc2112 ? rev. 1.0 advance information motorola table of contents 13 section 9. static random access memory (sram) 9.1 contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .199 9.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .199 9.3 modes of operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .200 9.4 low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .200 9.5 standby power supply pin (v stby ) . . . . . . . . . . . . . . . . . . . .200 9.6 standby operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .200 9.7 reset operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .201 9.8 interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .201 section 10. second generation flash for m core (sgfm) 10.1 contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .203 10.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .204 10.3 glossary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .205 10.4 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .206 10.5 modes of operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .206 10.6 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .207 10.7 module memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .209 10.7.1 unbanked register descriptions . . . . . . . . . . . . . . . . . . . .213 10.7.1.1 sgfm configuration register . . . . . . . . . . . . . . . . . . . .213 10.7.1.2 sgfm clock divider register . . . . . . . . . . . . . . . . . . . . 215 10.7.1.3 sgfm test register . . . . . . . . . . . . . . . . . . . . . . . . . . .216 10.7.1.4 sgfm security register . . . . . . . . . . . . . . . . . . . . . . . .217 10.7.1.5 sgfm monitor data register. . . . . . . . . . . . . . . . . . . . .219 10.7.2 banked register descriptions . . . . . . . . . . . . . . . . . . . . . .220 10.7.2.1 sgfm protection register . . . . . . . . . . . . . . . . . . . . . . .220 10.7.2.2 sgfm supervisor access register . . . . . . . . . . . . . . . .222 10.7.2.3 sgfm data access register . . . . . . . . . . . . . . . . . . . . .223 10.7.2.4 sgfm test status register . . . . . . . . . . . . . . . . . . . . . .224 10.7.2.5 sgfm user status register. . . . . . . . . . . . . . . . . . . . . .224 10.7.2.6 sgfm command register. . . . . . . . . . . . . . . . . . . . . . .226 10.7.2.7 sgfm control register . . . . . . . . . . . . . . . . . . . . . . . . . 227 10.7.2.8 sgfm address register . . . . . . . . . . . . . . . . . . . . . . . .228 10.7.2.9 sgfm data register . . . . . . . . . . . . . . . . . . . . . . . . . . .229 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . advance information mmc2114 MMC2113 mmc2112 ? rev. 1.0 14 table of contents motorola table of contents 10.8 sgfm user mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .230 10.8.1 read operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .230 10.8.2 write operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .230 10.8.3 program and erase operations . . . . . . . . . . . . . . . . . . . . .231 10.8.3.1 setting the sgfmclkd register. . . . . . . . . . . . . . . . . .231 10.8.3.2 program, erase, and verify sequences. . . . . . . . . . . . .232 10.8.3.3 flash user mode valid commands. . . . . . . . . . . . . . .234 10.8.3.4 flash user mode illegal operations . . . . . . . . . . . . . .236 10.8.4 stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .237 10.8.5 master mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .238 10.8.6 emulation mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .238 10.8.7 debug mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .238 10.9 flash security operation . . . . . . . . . . . . . . . . . . . . . . . . . . .238 10.9.1 back door access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 239 10.9.2 erase verify check. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .239 10.10 resets. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .240 10.11 interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .240 section 11. clock module 11.1 contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .243 11.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .244 11.3 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .244 11.4 modes of operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .245 11.4.1 normal pll mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .245 11.4.2 1:1 pll mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .245 11.4.3 external clock mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . .245 11.4.4 low-power options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .245 11.4.4.1 wait and doze modes . . . . . . . . . . . . . . . . . . . . . . . . . .245 11.4.4.2 stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .246 11.5 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .247 11.6 signal descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .248 11.6.1 extal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .248 11.6.2 xtal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .248 11.6.3 clkout. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 248 11.6.4 pllen . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .248 11.6.5 rstout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .249 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . table of contents mmc2114 MMC2113 mmc2112 ? rev. 1.0 advance information motorola table of contents 15 11.7 memory map and registers . . . . . . . . . . . . . . . . . . . . . . . . . .249 11.7.1 module memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . .249 11.7.2 register descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . .250 11.7.2.1 synthesizer control register . . . . . . . . . . . . . . . . . . . . .250 11.7.2.2 synthesizer status register. . . . . . . . . . . . . . . . . . . . . .253 11.7.2.3 synthesizer test register . . . . . . . . . . . . . . . . . . . . . . .256 11.7.2.4 synthesizer test register 2 . . . . . . . . . . . . . . . . . . . . . .257 11.8 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .258 11.8.1 system clock modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . .258 11.8.2 system clocks generation. . . . . . . . . . . . . . . . . . . . . . . . .259 11.8.3 pll lock detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .259 11.8.3.1 pll loss of lock conditions . . . . . . . . . . . . . . . . . . . . .261 11.8.3.2 pll loss of lock reset . . . . . . . . . . . . . . . . . . . . . . . . .261 11.8.4 loss of clock detection . . . . . . . . . . . . . . . . . . . . . . . . . . . 261 11.8.4.1 alternate clock selection . . . . . . . . . . . . . . . . . . . . . . . .262 11.8.4.2 loss-of-clock reset. . . . . . . . . . . . . . . . . . . . . . . . . . . .265 11.8.5 clock operation during reset . . . . . . . . . . . . . . . . . . . . . .266 11.8.6 pll operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .266 11.8.6.1 phase and frequency detector (pfd). . . . . . . . . . . . . .268 11.8.6.2 charge pump/loop filter . . . . . . . . . . . . . . . . . . . . . . . .268 11.8.6.3 voltage control output (vco) . . . . . . . . . . . . . . . . . . . .269 11.8.6.4 multiplication factor divider (mfd) . . . . . . . . . . . . . . . . 269 11.9 reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 269 11.10 interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .269 section 12. ports module 12.1 contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .271 12.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .272 12.3 signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .273 12.4 memory map and registers . . . . . . . . . . . . . . . . . . . . . . . . . .273 12.4.1 memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .274 12.4.2 register descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . .275 12.4.2.1 port output data registers . . . . . . . . . . . . . . . . . . . . . .275 12.4.2.2 port data direction registers. . . . . . . . . . . . . . . . . . . . .276 12.4.2.3 port pin data/set data registers . . . . . . . . . . . . . . . . .277 12.4.2.4 port clear output data registers . . . . . . . . . . . . . . . . .278 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . advance information mmc2114 MMC2113 mmc2112 ? rev. 1.0 16 table of contents motorola table of contents 12.4.2.5 port c/d pin assignment register . . . . . . . . . . . . . . . . .279 12.4.2.6 port e pin assignment register. . . . . . . . . . . . . . . . . . .280 12.5 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .281 12.5.1 pin functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .282 12.5.2 port digital i/o timing . . . . . . . . . . . . . . . . . . . . . . . . . . . .283 12.6 interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .283 section 13. edge port module (eport) 13.1 contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .285 13.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .285 13.3 low-power mode operation . . . . . . . . . . . . . . . . . . . . . . . . . .286 13.3.1 wait and doze modes . . . . . . . . . . . . . . . . . . . . . . . . . . . .286 13.3.2 stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .287 13.4 interrupt/general-purpose i/o pin descriptions . . . . . . . . . . .287 13.5 memory map and registers . . . . . . . . . . . . . . . . . . . . . . . . . .287 13.5.1 memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .287 13.5.2 registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .288 13.5.2.1 eport pin assignment register . . . . . . . . . . . . . . . . .288 13.5.2.2 eport data direction register. . . . . . . . . . . . . . . . . . .290 13.5.2.3 edge port interrupt enable register . . . . . . . . . . . . . . .291 13.5.2.4 edge port data register . . . . . . . . . . . . . . . . . . . . . . . .292 13.5.2.5 edge port pin data register . . . . . . . . . . . . . . . . . . . . .292 13.5.2.6 edge port flag register. . . . . . . . . . . . . . . . . . . . . . . . .293 section 14. watchdog timer module 14.1 contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .295 14.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .295 14.3 modes of operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .296 14.3.1 wait mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .296 14.3.2 doze mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .296 14.3.3 stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .296 14.3.4 debug mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .296 14.4 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .297 14.5 signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .297 14.6 memory map and registers . . . . . . . . . . . . . . . . . . . . . . . . . .298 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . table of contents mmc2114 MMC2113 mmc2112 ? rev. 1.0 advance information motorola table of contents 17 14.6.1 memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .298 14.6.2 registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .298 14.6.2.1 watchdog control register . . . . . . . . . . . . . . . . . . . . . .299 14.6.2.2 watchdog modulus register . . . . . . . . . . . . . . . . . . . . .301 14.6.2.3 watchdog count register . . . . . . . . . . . . . . . . . . . . . . .302 14.6.2.4 watchdog service register . . . . . . . . . . . . . . . . . . . . . .303 section 15. programmable interrupt timer modules (pit1 and pit2) 15.1 contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .305 15.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .306 15.3 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .306 15.4 modes of operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .307 15.4.1 wait mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .307 15.4.2 doze mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .307 15.4.3 stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .307 15.4.4 debug mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .307 15.5 signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .307 15.6 memory map and registers . . . . . . . . . . . . . . . . . . . . . . . . . .308 15.6.1 memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .308 15.6.2 registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .308 15.6.2.1 pit control and status register . . . . . . . . . . . . . . . . . .309 15.6.2.2 pit modulus register . . . . . . . . . . . . . . . . . . . . . . . . . .312 15.6.2.3 pit count register . . . . . . . . . . . . . . . . . . . . . . . . . . . .313 15.7 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .314 15.7.1 set-and-forget timer operation . . . . . . . . . . . . . . . . . . . .314 15.7.2 free-running timer operation . . . . . . . . . . . . . . . . . . . . .315 15.7.3 timeout specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . .315 15.8 interrupt operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .316 section 16. timer modules (tim1 and tim2) 16.1 contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .317 16.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .319 16.3 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .319 16.4 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .320 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . advance information mmc2114 MMC2113 mmc2112 ? rev. 1.0 18 table of contents motorola table of contents 16.5 modes of operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .321 16.5.1 supervisor and user modes. . . . . . . . . . . . . . . . . . . . . . . .321 16.5.2 run mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .321 16.5.3 stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .321 16.5.4 wait, doze, and debug modes . . . . . . . . . . . . . . . . . . . . .321 16.5.5 test mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .322 16.6 signal description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .322 16.6.1 icoc[2:0] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .322 16.6.2 icoc3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 322 16.7 memory map and registers . . . . . . . . . . . . . . . . . . . . . . . . . .323 16.7.1 timer input capture/output compare select register . . .324 16.7.2 timer compare force register . . . . . . . . . . . . . . . . . . . . .325 16.7.3 timer output compare 3 mask register . . . . . . . . . . . . . .326 16.7.4 timer output compare 3 data register. . . . . . . . . . . . . . .327 16.7.5 timer counter registers . . . . . . . . . . . . . . . . . . . . . . . . . .328 16.7.6 timer system control register 1 . . . . . . . . . . . . . . . . . . . .329 16.7.7 timer toggle-on-overflow register . . . . . . . . . . . . . . . . .330 16.7.8 timer control register 1 . . . . . . . . . . . . . . . . . . . . . . . . . .331 16.7.9 timer control register 2 . . . . . . . . . . . . . . . . . . . . . . . . . .332 16.7.10 timer interrupt enable register . . . . . . . . . . . . . . . . . . . . .333 16.7.11 timer system control register 2 . . . . . . . . . . . . . . . . . . . .334 16.7.12 timer flag register 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . .336 16.7.13 timer flag register 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . .337 16.7.14 timer channel registers . . . . . . . . . . . . . . . . . . . . . . . . . .338 16.7.15 pulse accumulator control register . . . . . . . . . . . . . . . . . 339 16.7.16 pulse accumulator flag register . . . . . . . . . . . . . . . . . . . .341 16.7.17 pulse accumulator counter registers . . . . . . . . . . . . . . . .342 16.7.18 timer port data register . . . . . . . . . . . . . . . . . . . . . . . . . .343 16.7.19 timer port data direction register . . . . . . . . . . . . . . . . . .344 16.7.20 timer test register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .345 16.8 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .345 16.8.1 prescaler . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .345 16.8.2 input capture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .345 16.8.3 output compare . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .346 16.8.4 pulse accumulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .347 16.8.4.1 event counter mode . . . . . . . . . . . . . . . . . . . . . . . . . . .347 16.8.4.2 gated time accumulation mode . . . . . . . . . . . . . . . . . .348 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . table of contents mmc2114 MMC2113 mmc2112 ? rev. 1.0 advance information motorola table of contents 19 16.8.5 general-purpose i/o ports. . . . . . . . . . . . . . . . . . . . . . . . .349 16.9 reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 351 16.10 interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .351 16.10.1 timer channel interrupts (cxf) . . . . . . . . . . . . . . . . . . . . .351 16.10.2 pulse accumulator overflow (paovf). . . . . . . . . . . . . . . .352 16.10.3 pulse accumulator input (paif) . . . . . . . . . . . . . . . . . . . . .352 16.10.4 timer overflow (tof) . . . . . . . . . . . . . . . . . . . . . . . . . . . .352 section 17. serial communications interface modules (sci1 and sci2) 17.1 contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .353 17.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .354 17.3 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .355 17.4 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .356 17.5 modes of operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .357 17.5.1 doze mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .357 17.5.2 stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .357 17.6 signal description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .358 17.6.1 rxd . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 358 17.6.2 txd . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .358 17.7 memory map and registers . . . . . . . . . . . . . . . . . . . . . . . . . .358 17.7.1 sci baud rate registers . . . . . . . . . . . . . . . . . . . . . . . . . .360 17.7.2 sci control register 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . .361 17.7.3 sci control register 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . .364 17.7.4 sci status register 1. . . . . . . . . . . . . . . . . . . . . . . . . . . . .366 17.7.5 sci status register 2. . . . . . . . . . . . . . . . . . . . . . . . . . . . .369 17.7.6 sci data registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .370 17.7.7 sci pullup and reduced drive register . . . . . . . . . . . . . .371 17.7.8 sci port data register . . . . . . . . . . . . . . . . . . . . . . . . . . . .372 17.7.9 sci data direction register . . . . . . . . . . . . . . . . . . . . . . . .373 17.8 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .374 17.9 data format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .374 17.10 baud rate generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .375 17.11 transmitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .376 17.11.1 frame length . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .377 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . advance information mmc2114 MMC2113 mmc2112 ? rev. 1.0 20 table of contents motorola table of contents 17.11.2 transmitting a frame . . . . . . . . . . . . . . . . . . . . . . . . . . . . .378 17.11.3 break frames. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .380 17.11.4 idle frames . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .380 17.12 receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .381 17.12.1 frame length . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .381 17.12.2 receiving a frame . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .381 17.12.3 data sampling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .382 17.12.4 framing errors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .387 17.12.5 baud rate tolerance . . . . . . . . . . . . . . . . . . . . . . . . . . . . .387 17.12.5.1 slow data tolerance . . . . . . . . . . . . . . . . . . . . . . . . . . .388 17.12.5.2 fast data tolerance . . . . . . . . . . . . . . . . . . . . . . . . . . .389 17.12.6 receiver wakeup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .390 17.12.6.1 idle input line wakeup (wake = 0) . . . . . . . . . . . . . . .390 17.12.6.2 address mark wakeup (wake = 1). . . . . . . . . . . . . . . .391 17.13 single-wire operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .392 17.14 loop operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .393 17.15 i/o ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .394 17.16 reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .395 17.17 interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .395 17.17.1 transmit data register empty . . . . . . . . . . . . . . . . . . . . . .395 17.17.2 transmission complete . . . . . . . . . . . . . . . . . . . . . . . . . . .395 17.17.3 receive data register full. . . . . . . . . . . . . . . . . . . . . . . . . 396 17.17.4 idle receiver input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .396 17.17.5 overrun . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .396 section 18. serial peripheral interface module (spi) 18.1 contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .397 18.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .398 18.3 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .398 18.4 modes of operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .399 18.5 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .399 18.6 signal description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .400 18.6.1 miso (master in/slave out) . . . . . . . . . . . . . . . . . . . . . . . .400 18.6.2 mosi (master out/slave in) . . . . . . . . . . . . . . . . . . . . . . . .400 18.6.3 sck (serial clock) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .401 18.6.4 ss (slave select) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .401 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . table of contents mmc2114 MMC2113 mmc2112 ? rev. 1.0 advance information motorola table of contents 21 18.7 memory map and registers . . . . . . . . . . . . . . . . . . . . . . . . . .401 18.7.1 spi control register 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 402 18.7.2 spi control register 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 405 18.7.3 spi baud rate register . . . . . . . . . . . . . . . . . . . . . . . . . . .406 18.7.4 spi status register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .408 18.7.5 spi data register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .409 18.7.6 spi pullup and reduced drive register . . . . . . . . . . . . . .410 18.7.7 spi port data register . . . . . . . . . . . . . . . . . . . . . . . . . . . .411 18.7.8 spi port data direction register . . . . . . . . . . . . . . . . . . . .412 18.8 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .413 18.8.1 master mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .414 18.8.2 slave mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .415 18.8.3 transmission formats . . . . . . . . . . . . . . . . . . . . . . . . . . . .416 18.8.3.1 transfer format when cpha = 1 . . . . . . . . . . . . . . . . .416 18.8.3.2 transfer format when cpha = 0 . . . . . . . . . . . . . . . . .417 18.8.4 spi baud rate generation. . . . . . . . . . . . . . . . . . . . . . . . .420 18.8.5 slave-select output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .420 18.8.6 bidirectional mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .421 18.8.7 error conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .422 18.8.7.1 write collision error . . . . . . . . . . . . . . . . . . . . . . . . . . . .422 18.8.7.2 mode fault error . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .422 18.8.8 low-power mode options . . . . . . . . . . . . . . . . . . . . . . . . .423 18.8.8.1 run mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .423 18.8.8.2 doze mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .423 18.8.8.3 stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .424 18.9 reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 424 18.10 interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .424 18.10.1 mode fault (modf) flag . . . . . . . . . . . . . . . . . . . . . . . . . .424 18.10.2 spi interrupt flag (spif) . . . . . . . . . . . . . . . . . . . . . . . . . .424 section 19. queued analog-to-digital converter (qadc) 19.1 contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .425 19.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .427 19.3 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .428 19.4 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .429 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . advance information mmc2114 MMC2113 mmc2112 ? rev. 1.0 22 table of contents motorola table of contents 19.5 modes of operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .430 19.5.1 debug mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .430 19.5.2 stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .431 19.6 signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .431 19.6.1 port qa pin functions . . . . . . . . . . . . . . . . . . . . . . . . . . . .432 19.6.1.1 port qa analog input pins . . . . . . . . . . . . . . . . . . . . . . .432 19.6.1.2 port qa digital input/output pins . . . . . . . . . . . . . . . . .433 19.6.2 port qb pin functions . . . . . . . . . . . . . . . . . . . . . . . . . . . .433 19.6.2.1 port qb analog input pins . . . . . . . . . . . . . . . . . . . . . . .433 19.6.2.2 port qb digital input pins . . . . . . . . . . . . . . . . . . . . . . .433 19.6.3 external trigger input pins. . . . . . . . . . . . . . . . . . . . . . . . .434 19.6.4 multiplexed address output pins . . . . . . . . . . . . . . . . . . . .434 19.6.5 multiplexed analog input pins . . . . . . . . . . . . . . . . . . . . . .435 19.6.6 voltage reference pins . . . . . . . . . . . . . . . . . . . . . . . . . . .435 19.6.7 dedicated analog supply pins . . . . . . . . . . . . . . . . . . . . . .435 19.6.8 dedicated digital i/o port supply pin. . . . . . . . . . . . . . . . . 435 19.7 memory map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .436 19.8 register descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 437 19.8.1 qadc module configuration register (qadcmcr) . . . . .437 19.8.2 qadc test register (qadctest) . . . . . . . . . . . . . . . . . .438 19.8.3 port data registers (portqa and portqb) . . . . . . . . .438 19.8.4 port qa and qb data direction register (ddrqa and ddrqb) . . . . . . . . . . . . . . . . . . . . . . . . . 440 19.8.5 control registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .442 19.8.5.1 qadc control register 0 (qacr0) . . . . . . . . . . . . . . . . 442 19.8.5.2 qadc control register 1 (qacr1) . . . . . . . . . . . . . . . . 445 19.8.5.3 qadc control register 2 (qacr2) . . . . . . . . . . . . . . . . 448 19.8.6 status registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .453 19.8.6.1 qadc status register 0 (qasr0). . . . . . . . . . . . . . . . .453 19.8.6.2 qadc status register 1 (qasr1). . . . . . . . . . . . . . . . .462 19.8.7 conversion command word table (ccw) . . . . . . . . . . . .463 19.8.8 result registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .468 19.8.8.1 right-justified unsigned result register (rjurr) . . . .468 19.8.8.2 left-justified signed result register (ljsrr) . . . . . . .469 19.8.8.3 left-justified unsigned result register (ljurr) . . . . . 470 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . table of contents mmc2114 MMC2113 mmc2112 ? rev. 1.0 advance information motorola table of contents 23 19.9 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .470 19.9.1 result coherency. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .470 19.9.2 external multiplexing . . . . . . . . . . . . . . . . . . . . . . . . . . . . .471 19.9.2.1 external multiplexing operation . . . . . . . . . . . . . . . . . . .471 19.9.2.2 module version options. . . . . . . . . . . . . . . . . . . . . . . . .473 19.9.3 analog subsystem . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .474 19.9.3.1 analog-to-digital converter operation . . . . . . . . . . . . . .474 19.9.3.2 conversion cycle times . . . . . . . . . . . . . . . . . . . . . . . .475 19.9.3.3 channel decode and multiplexer . . . . . . . . . . . . . . . . . .476 19.9.3.4 sample buffer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .476 19.9.3.5 digital-to-analog converter (dac) array . . . . . . . . . . . .476 19.9.3.6 comparator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .477 19.9.3.7 bias . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .477 19.9.3.8 successive approximation register. . . . . . . . . . . . . . . . 477 19.9.3.9 state machine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .477 19.10 digital control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .478 19.10.1 queue priority timing examples . . . . . . . . . . . . . . . . . . . .478 19.10.1.1 queue priority . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .478 19.10.1.2 queue priority schemes . . . . . . . . . . . . . . . . . . . . . . . .481 19.10.2 boundary conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . .492 19.10.3 scan modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .493 19.10.4 disabled mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .494 19.10.5 reserved mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .494 19.10.6 single-scan modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .494 19.10.6.1 software-initiated single-scan mode. . . . . . . . . . . . . . .495 19.10.6.2 externally triggered single-scan mode. . . . . . . . . . . . .496 19.10.6.3 externally gated single-scan mode . . . . . . . . . . . . . . .497 19.10.6.4 interval timer single-scan mode. . . . . . . . . . . . . . . . . .497 19.10.7 continuous-scan modes . . . . . . . . . . . . . . . . . . . . . . . . . .499 19.10.7.1 software-initiated continuous-scan mode. . . . . . . . . . .500 19.10.7.2 externally triggered continuous-scan mode . . . . . . . .501 19.10.7.3 externally gated continuous-scan mode . . . . . . . . . . .501 19.10.7.4 periodic timer continuous-scan mode . . . . . . . . . . . . .502 19.10.8 qadc clock (qclk) generation . . . . . . . . . . . . . . . . . . . .503 19.10.9 periodic/interval timer . . . . . . . . . . . . . . . . . . . . . . . . . . . .504 19.10.10 conversion command word table . . . . . . . . . . . . . . . . . .505 19.10.11 result word table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .509 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . advance information mmc2114 MMC2113 mmc2112 ? rev. 1.0 24 table of contents motorola table of contents 19.11 pin connection considerations . . . . . . . . . . . . . . . . . . . . . . .509 19.11.1 analog reference pins. . . . . . . . . . . . . . . . . . . . . . . . . . . .509 19.11.2 analog power pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .510 19.11.3 conversion timing schemes . . . . . . . . . . . . . . . . . . . . . . .512 19.11.4 analog supply filtering and grounding . . . . . . . . . . . . . . .515 19.11.5 accommodating positive/negative stress conditions . . . .517 19.11.6 analog input considerations . . . . . . . . . . . . . . . . . . . . . . .519 19.11.7 analog input pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .521 19.11.7.1 settling time for the external circuit . . . . . . . . . . . . . . .522 19.11.7.2 error resulting from leakage . . . . . . . . . . . . . . . . . . . .523 19.12 interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .524 19.12.1 interrupt operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .524 19.12.2 interrupt sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .525 section 20. external bus interface module (ebi) 20.1 contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .527 20.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .528 20.3 signal descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .529 20.3.1 data bus (d[31:0]) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .530 20.3.2 show cycle strobe (shs ) . . . . . . . . . . . . . . . . . . . . . . . . .530 20.3.3 transfer acknowledge (ta ) . . . . . . . . . . . . . . . . . . . . . . . .530 20.3.4 transfer error acknowledge (tea ) . . . . . . . . . . . . . . . . . .530 20.3.5 emulation mode chip selects (cse[1:0]) . . . . . . . . . . . . .530 20.3.6 transfer code (tc[2:0]) . . . . . . . . . . . . . . . . . . . . . . . . . . .531 20.3.7 read/write (r/w ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .531 20.3.8 address bus (a[22:0]) . . . . . . . . . . . . . . . . . . . . . . . . . . . .531 20.3.9 enable byte (eb [3:0] ). . . . . . . . . . . . . . . . . . . . . . . . . . . . .531 20.3.10 chip selects (cs [3:0] ) . . . . . . . . . . . . . . . . . . . . . . . . . . . .531 20.3.11 output enable (oe ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .531 20.3.12 transfer size (tsiz[1:0]) . . . . . . . . . . . . . . . . . . . . . . . . . .532 20.3.13 processor status (pstat[3:0]) . . . . . . . . . . . . . . . . . . . . .532 20.4 memory map and registers . . . . . . . . . . . . . . . . . . . . . . . . . .532 20.5 operand transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .532 20.6 enable byte pins (eb[3:0] ) . . . . . . . . . . . . . . . . . . . . . . . . . . .534 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . table of contents mmc2114 MMC2113 mmc2112 ? rev. 1.0 advance information motorola table of contents 25 20.7 bus master cycles . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 534 20.7.1 read cycles . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 535 20.7.1.1 state 1 (x1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .536 20.7.1.2 optional wait states (x2w) . . . . . . . . . . . . . . . . . . . . . .536 20.7.1.3 state 2 (x2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .536 20.7.2 write cycles . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 537 20.7.2.1 state 1 (x1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .538 20.7.2.2 optional wait states (x2w) . . . . . . . . . . . . . . . . . . . . . .538 20.7.2.3 state 2 (x2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .538 20.8 bus exception operation . . . . . . . . . . . . . . . . . . . . . . . . . . . .540 20.8.1 transfer error termination . . . . . . . . . . . . . . . . . . . . . . . . .540 20.8.2 transfer abort termination . . . . . . . . . . . . . . . . . . . . . . . .540 20.9 emulation support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .540 20.9.1 emulation chip-selects (cse[1:0]) . . . . . . . . . . . . . . . . . .540 20.9.2 internal data transfer display (show cycles) . . . . . . . . . .541 20.9.3 show strobe (shs ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .542 20.9.4 transfer code (tc[2:0]) . . . . . . . . . . . . . . . . . . . . . . . . . . .543 20.9.5 processor status (pstat) . . . . . . . . . . . . . . . . . . . . . . . . .543 20.10 bus monitor. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .545 20.11 interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .545 section 21. chip select module 21.1 contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .547 21.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .547 21.3 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .548 21.4 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .549 21.5 signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .550 21.6 memory map and registers . . . . . . . . . . . . . . . . . . . . . . . . . .550 21.6.1 memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .550 21.6.2 registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .551 21.7 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .556 21.8 interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .557 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . advance information mmc2114 ? MMC2113 mmc2112 ? rev. 1.0 26 table of contents motorola table of contents section 22. jtag test access port and once 22.1 contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .559 22.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .561 22.3 top-level test access port (tap) . . . . . . . . . . . . . . . . . . . . .563 22.3.1 test clock (tclk) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 564 22.3.2 test mode select (tms) . . . . . . . . . . . . . . . . . . . . . . . . . .564 22.3.3 test data input (tdi) . . . . . . . . . . . . . . . . . . . . . . . . . . . . .564 22.3.4 test data output (tdo) . . . . . . . . . . . . . . . . . . . . . . . . . . .564 22.3.5 test reset (trst) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .564 22.3.6 debug event (de) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .564 22.4 top-level tap controller . . . . . . . . . . . . . . . . . . . . . . . . . . . .566 22.5 instruction shift register. . . . . . . . . . . . . . . . . . . . . . . . . . . . .567 22.5.1 extest instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .567 22.5.2 idcode instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 568 22.5.3 sample/preload instruction . . . . . . . . . . . . . . . . . . . . . 569 22.5.4 enable_mcu_once instruction . . . . . . . . . . . . . . . . . . .569 22.5.5 highz instruction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 570 22.5.6 clamp instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .570 22.5.7 bypass instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .570 22.6 idcode register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 571 22.7 bypass register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 572 22.8 boundary scan register. . . . . . . . . . . . . . . . . . . . . . . . . . . . .572 22.9 restrictions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .572 22.10 non-scan chain operation. . . . . . . . . . . . . . . . . . . . . . . . . . .573 22.11 boundary scan . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .573 22.12 low-level tap (once) module . . . . . . . . . . . . . . . . . . . . . . .579 22.13 signal descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .581 22.13.1 debug serial input (tdi) . . . . . . . . . . . . . . . . . . . . . . . . . .581 22.13.2 debug serial clock (tclk) . . . . . . . . . . . . . . . . . . . . . . . .581 22.13.3 debug serial output (tdo) . . . . . . . . . . . . . . . . . . . . . . . .581 22.13.4 debug mode select (tms). . . . . . . . . . . . . . . . . . . . . . . . .582 22.13.5 test reset (trst ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .582 22.13.6 debug event (de ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .582 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . table of contents mmc2114 MMC2113 mmc2112 ? rev. 1.0 advance information motorola table of contents 27 22.14 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .582 22.14.1 operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .583 22.14.2 once controller and serial interface. . . . . . . . . . . . . . . . .584 22.14.3 once interface signals . . . . . . . . . . . . . . . . . . . . . . . . . . .585 22.14.3.1 internal debug request input (idr ) . . . . . . . . . . . . . . .585 22.14.3.2 cpu debug request (dbgrq ) . . . . . . . . . . . . . . . . . . .586 22.14.3.3 cpu debug acknowledge (dbgack ) . . . . . . . . . . . . . .586 22.14.3.4 cpu breakpoint request (brkrq ). . . . . . . . . . . . . . . .586 22.14.3.5 cpu address, attributes (addr, attr) . . . . . . . . . . . . 587 22.14.3.6 cpu status (pstat) . . . . . . . . . . . . . . . . . . . . . . . . . . .587 22.14.3.7 once debug output (debug ) . . . . . . . . . . . . . . . . . . .587 22.14.4 once controller registers. . . . . . . . . . . . . . . . . . . . . . . . .587 22.14.4.1 once command register . . . . . . . . . . . . . . . . . . . . . . .588 22.14.4.2 once control register . . . . . . . . . . . . . . . . . . . . . . . . .590 22.14.4.3 once status register . . . . . . . . . . . . . . . . . . . . . . . . . .594 22.14.5 once decoder (odec) . . . . . . . . . . . . . . . . . . . . . . . . . . .596 22.14.6 memory breakpoint logic. . . . . . . . . . . . . . . . . . . . . . . . . .596 22.14.6.1 memory address latch (mal) . . . . . . . . . . . . . . . . . . . .597 22.14.6.2 breakpoint address base registers . . . . . . . . . . . . . . .597 22.14.7 breakpoint address mask registers . . . . . . . . . . . . . . . . .597 22.14.7.1 breakpoint address comparators . . . . . . . . . . . . . . . . .598 22.14.7.2 memory breakpoint counters . . . . . . . . . . . . . . . . . . . .598 22.14.8 once trace logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .598 22.14.8.1 once trace counter . . . . . . . . . . . . . . . . . . . . . . . . . . .599 22.14.8.2 trace operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .600 22.14.9 methods of entering debug mode . . . . . . . . . . . . . . . . . . .600 22.14.9.1 debug request during reset . . . . . . . . . . . . . . . . . . .600 22.14.9.2 debug request during normal activity . . . . . . . . . . . . .601 22.14.9.3 debug request during stop, doze, or wait mode . . . .601 22.14.9.4 software request during normal activity . . . . . . . . . . .601 22.14.10 enabling once trace mode . . . . . . . . . . . . . . . . . . . . . . .601 22.14.11 enabling once memory breakpoints. . . . . . . . . . . . . . . . .602 22.14.12 pipeline information and write-back bus register . . . . . .602 22.14.12.1 program counter register . . . . . . . . . . . . . . . . . . . . . . .603 22.14.12.2 instruction register . . . . . . . . . . . . . . . . . . . . . . . . . . . .603 22.14.12.3 control state register . . . . . . . . . . . . . . . . . . . . . . . . . .603 22.14.12.4 writeback bus register . . . . . . . . . . . . . . . . . . . . . . . . . 605 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . advance information mmc2114 ? MMC2113 mmc2112 ? rev. 1.0 28 table of contents motorola table of contents 22.14.12.5 processor status register . . . . . . . . . . . . . . . . . . . . . . .605 22.14.13 instruction address fifo buffer (pc fifo) . . . . . . . . . . . .606 22.14.14 reserved test control registers . . . . . . . . . . . . . . . . . . . . 607 22.14.15 serial protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .607 22.14.16 once commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .608 22.14.17 target site debug system requirements . . . . . . . . . . . . .608 22.14.18 interface connector for jtag/once serial port . . . . . . . .608 section 23. preliminary electrical specifications 23.1 contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .611 23.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .612 23.3 absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . .613 23.4 thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . .614 23.5 junction temperature determination . . . . . . . . . . . . . . . . . . .614 23.6 electrostatic discharge (esd) protection . . . . . . . . . . . . . . . .615 23.7 dc electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . 616 23.8 pll electrical specifications. . . . . . . . . . . . . . . . . . . . . . . . . . 618 23.9 qadc electrical characteristics . . . . . . . . . . . . . . . . . . . . . . .620 23.10 flash memory characteristics . . . . . . . . . . . . . . . . . . . . . . .624 23.11 external interface timing characteristics . . . . . . . . . . . . . . . .625 23.12 general purpose i/o timing . . . . . . . . . . . . . . . . . . . . . . . . . .630 23.13 reset and configuration override timing . . . . . . . . . . . . . . .631 23.14 spi timing characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . .632 23.15 once, jtag, and boundary scan timing . . . . . . . . . . . . . . .635 section 24. mechanical specifications 24.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .639 24.3 bond pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .640 24.4 package information for the 144-pin lqfp . . . . . . . . . . . . . .641 24.5 package information for the 100-pin lqfp . . . . . . . . . . . . . .641 24.6 package information for the 196-ball mapbga . . . . . . . . . . .642 24.7 144-pin lqfp mechanical drawing . . . . . . . . . . . . . . . . . . . .643 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . table of contents mmc2114 MMC2113 mmc2112 ? rev. 1.0 advance information motorola table of contents 29 24.8 100-pin lqfp mechanical drawing . . . . . . . . . . . . . . . . . . . .644 24.9 196-ball mapbga mechanical drawing. . . . . . . . . . . . . . . . .645 section 25. ordering information 25.1 contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .647 25.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .647 25.3 mc order numbers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .647 appendix a. security a.1 contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .649 a.2 security philosophy/strategy . . . . . . . . . . . . . . . . . . . . . . . . .649 a.3 mcu operation with security enabled . . . . . . . . . . . . . . . . . .650 a.4 flash access blocking mechanisms . . . . . . . . . . . . . . . . . .650 a.4.1 forced operating mode selection . . . . . . . . . . . . . . . . . . .650 a.4.2 disabled once access . . . . . . . . . . . . . . . . . . . . . . . . . . . 651 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . advance information mmc2114 MMC2113 mmc2112 ? rev. 1.0 30 table of contents motorola table of contents f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . mmc2114 MMC2113 mmc2112 ? rev. 1.0 advance information motorola list of figures 31 advance information ? mmc2114, MMC2113, and mmc2112 list of figures figure title page 1-1 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 2-1 mmc2112 address map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .54 2-2 MMC2113 address map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .54 2-3 mmc2114 address map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .55 2-4 register summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .57 3-1 196-ball mapbga assignments. . . . . . . . . . . . . . . . . . . . . . .103 3-2 144-pin lqfp assignments . . . . . . . . . . . . . . . . . . . . . . . . . .104 3-3 100-pin lqfp assignments . . . . . . . . . . . . . . . . . . . . . . . . . .105 4-1 chip configuration module block diagram. . . . . . . . . . . . . . .124 4-2 chip configuration register (ccr) . . . . . . . . . . . . . . . . . . . . 126 4-3 reset configuration register (rcon) . . . . . . . . . . . . . . . . . .129 4-4 chip identification register (cir) . . . . . . . . . . . . . . . . . . . . . .131 4-5 chip test register (ctr) . . . . . . . . . . . . . . . . . . . . . . . . . . . .132 5-1 reset controller block diagram . . . . . . . . . . . . . . . . . . . . . . .141 5-2 reset control register (rcr) . . . . . . . . . . . . . . . . . . . . . . . . 143 5-3 reset status register (rsr) . . . . . . . . . . . . . . . . . . . . . . . . .145 5-4 reset control flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .150 7-1 m core processor block diagram . . . . . . . . . . . . . . . . . . . . 167 7-2 programming model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .169 7-3 data organization in memory . . . . . . . . . . . . . . . . . . . . . . . . .171 7-4 data organization in registers. . . . . . . . . . . . . . . . . . . . . . . .171 8-1 interrupt controller block diagram . . . . . . . . . . . . . . . . . . . . .179 8-2 interrupt control register (icr) . . . . . . . . . . . . . . . . . . . . . . .181 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . advance information mmc2114 MMC2113 mmc2112 ? rev. 1.0 32 list of figures motorola list of figures figure title page 8-3 interrupt status register (isr) . . . . . . . . . . . . . . . . . . . . . . . .183 8-4 interrupt force register high (ifrh) . . . . . . . . . . . . . . . . . . .184 8-5 interrupt force register low (ifrl) . . . . . . . . . . . . . . . . . . . .185 8-6 interrupt pending register (ipr) . . . . . . . . . . . . . . . . . . . . . .186 8-7 normal interrupt enable register (nier) . . . . . . . . . . . . . . . .187 8-8 normal interrupt pending register (nipr) . . . . . . . . . . . . . . .188 8-9 fast interrupt enable register (fier) . . . . . . . . . . . . . . . . . .189 8-10 fast interrupt pending register (fipr) . . . . . . . . . . . . . . . . .190 8-11 priority level select registers (plsr0 ? plsr39) . . . . . . . . .191 10-1 sgfm module block diagram . . . . . . . . . . . . . . . . . . . . . . . .208 10-2 sgfm array memory map . . . . . . . . . . . . . . . . . . . . . . . . . . .209 10-3 sgfm module configuration register (sgfmcr). . . . . . . . .213 10-4 sgfm clock divider register (sgfmclkd) . . . . . . . . . . . . .215 10-5 sgfm test register (sgfmtst) . . . . . . . . . . . . . . . . . . . . .216 10-6 sgfm security register (sgfmsec) . . . . . . . . . . . . . . . . . .217 10-7 sgfm monitor data register (sgfmmntr) . . . . . . . . . . . . .219 10-8 sgfm protection register (sgfmprot) . . . . . . . . . . . . . . .220 10-9 sgfmprot protection diagram . . . . . . . . . . . . . . . . . . . . . .221 10-10 sgfm supervisor access register (sgfmasacc) . . . . . . .222 10-11 sgfm data access register (sgfmdacc) . . . . . . . . . . . . .223 10-12 sgfm test status register (sgfmtstat). . . . . . . . . . . . . .224 10-13 sgfm user status register (sgfmustat) . . . . . . . . . . . . .224 10-14 sgfm command register (sgfmcmd) . . . . . . . . . . . . . . . .226 10-15 sgfm control register (sgfmctl) . . . . . . . . . . . . . . . . . . .227 10-16 sgfm address register (sgfmadr) . . . . . . . . . . . . . . . . . .228 10-17 sgfm data register (sgfmdata) . . . . . . . . . . . . . . . . . . . .229 10-18 example program algorithm. . . . . . . . . . . . . . . . . . . . . . . . . .235 10-19 sgfm interrupt implementation . . . . . . . . . . . . . . . . . . . . . . .241 11-1 clock module block diagram . . . . . . . . . . . . . . . . . . . . . . . . .247 11-2 synthesizer control register (syncr) . . . . . . . . . . . . . . . . . 250 11-3 synthesizer status register (synsr) . . . . . . . . . . . . . . . . . .253 11-4 synthesizer test register (syntr) . . . . . . . . . . . . . . . . . . . .256 11-5 synthesizer test register 2 (syntr2) . . . . . . . . . . . . . . . . .257 11-6 lock detect sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .260 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . list of figures mmc2114 MMC2113 mmc2112 ? rev. 1.0 advance information motorola list of figures 33 figure title page 11-7 pll block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .267 11-8 crystal oscillator example . . . . . . . . . . . . . . . . . . . . . . . . . . . 267 12-1 ports module block diagram . . . . . . . . . . . . . . . . . . . . . . . . .272 12-2 port output data registers (portx) . . . . . . . . . . . . . . . . . . .275 12-3 port data direction registers (ddrx) . . . . . . . . . . . . . . . . . .276 12-4 port pin data/set data registers (portxp/setx) . . . . . . . .277 12-5 port clear output data registers (clrx). . . . . . . . . . . . . . . .278 12-6 port c, d, i7, and i6 pin assignment register (pcdpar) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 279 12-7 port e pin assignment register (pepar) . . . . . . . . . . . . . . .280 12-8 digital input timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .283 12-9 digital output timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .283 13-1 eport block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .286 13-2 eport pin assignment register (eppar) . . . . . . . . . . . . . .288 13-3 eport data direction register (epddr) . . . . . . . . . . . . . . . 290 13-4 eport port interrupt enable register (epier). . . . . . . . . . .291 13-5 eport port data register (epdr) . . . . . . . . . . . . . . . . . . . .292 13-6 eport port pin data register (eppdr). . . . . . . . . . . . . . . .292 13-7 eport port flag register (epfr) . . . . . . . . . . . . . . . . . . . .293 14-1 watchdog timer block diagram . . . . . . . . . . . . . . . . . . . . . . .297 14-2 watchdog control register (wcr). . . . . . . . . . . . . . . . . . . . .299 14-3 watchdog modulus register (wmr) . . . . . . . . . . . . . . . . . . .301 14-4 watchdog count register (wcntr) . . . . . . . . . . . . . . . . . . .302 14-5 watchdog service register (wsr) . . . . . . . . . . . . . . . . . . . .303 15-1 pit block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .306 15-2 pit control and status register (pcsr) . . . . . . . . . . . . . . . .309 15-3 pit modulus register (pmr) . . . . . . . . . . . . . . . . . . . . . . . . .312 15-4 pit count register (pcntr) . . . . . . . . . . . . . . . . . . . . . . . . .313 15-5 counter reloading from the modulus latch . . . . . . . . . . . . . .314 15-6 counter in free-running mode . . . . . . . . . . . . . . . . . . . . . . .315 16-1 timer block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .320 16-2 timer input capture/output compare select register (timios). . . . . . . . . . . . . . . . . . . . . . . . . .324 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . advance information mmc2114 MMC2113 mmc2112 ? rev. 1.0 34 list of figures motorola list of figures figure title page 16-3 timer compare force register (timcforc) . . . . . . . . . . . .325 16-4 timer output compare 3 mask register (timoc3m) . . . . . .326 16-5 timer output compare 3 data register (timoc3d) . . . . . . .327 16-6 timer counter register high (timcnth) . . . . . . . . . . . . . . .328 16-7 timer counter register low (timcntl) . . . . . . . . . . . . . . . .328 16-8 timer system control register (timscr1) . . . . . . . . . . . . . .329 16-9 fast clear flag logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .330 16-10 timer toggle-on-overflow register (timtov) . . . . . . . . . . .330 16-11 timer control register 1 (timctl1) . . . . . . . . . . . . . . . . . . .331 16-12 timer control register 2 (timctl2) . . . . . . . . . . . . . . . . . . .332 16-13 timer interrupt enable register (timie). . . . . . . . . . . . . . . . .333 16-14 timer system control register 2 (timscr2) . . . . . . . . . . . .334 16-15 timer flag register 1 (timflg1). . . . . . . . . . . . . . . . . . . . . .336 16-16 timer flag register 2 (timflg2). . . . . . . . . . . . . . . . . . . . . .337 16-17 timer channel [0:3] register high (timcxh). . . . . . . . . . . . .338 16-18 timer channel [0:3] register low (timcxl) . . . . . . . . . . . . .338 16-19 pulse accumulator control register (timpactl) . . . . . . . . .339 16-20 pulse accumulator flag register (timpaflg) . . . . . . . . . . .341 16-21 pulse accumulator counter register high (timpacnth) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 342 16-22 pulse accumulator counter register low (timpacntl) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .342 16-23 timer port data register (timport) . . . . . . . . . . . . . . . . . .343 16-24 timer port data direction register (timddr) . . . . . . . . . . . . 344 16-25 timer test register (timtst) . . . . . . . . . . . . . . . . . . . . . . . .345 16-26 channel 3 output compare/pulse accumulator logic . . . . . .348 17-1 sci block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .356 17-2 sci baud rate register high (scibdh) . . . . . . . . . . . . . . . .360 17-3 sci baud rate register low (scibdl) . . . . . . . . . . . . . . . . .360 17-4 sci control register 1 (scicr1) . . . . . . . . . . . . . . . . . . . . . . 361 17-5 sci control register 2 (scicr2) . . . . . . . . . . . . . . . . . . . . . . 364 17-6 sci status register 1 (scisr1). . . . . . . . . . . . . . . . . . . . . . .366 17-7 sci status register 2 (scisr2). . . . . . . . . . . . . . . . . . . . . . .369 17-8 sci data register high (scidrh) . . . . . . . . . . . . . . . . . . . . . 370 17-9 sci data register low (scidrl). . . . . . . . . . . . . . . . . . . . . .370 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . list of figures mmc2114 MMC2113 mmc2112 ? rev. 1.0 advance information motorola list of figures 35 figure title page 17-10 sci pullup and reduced drive register (scipurd) . . . . . . . 371 17-11 sci port data register (sciport) . . . . . . . . . . . . . . . . . . . .372 17-12 sci data direction register (sciddr) . . . . . . . . . . . . . . . . .373 17-13 sci data formats . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .374 17-14 transmitter block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . .376 17-15 sci receiver block diagram . . . . . . . . . . . . . . . . . . . . . . . . . 381 17-16 receiver data sampling . . . . . . . . . . . . . . . . . . . . . . . . . . . . .382 17-17 start bit search example 1. . . . . . . . . . . . . . . . . . . . . . . . . . .384 17-18 start bit search example 2. . . . . . . . . . . . . . . . . . . . . . . . . . .385 17-19 start bit search example 3. . . . . . . . . . . . . . . . . . . . . . . . . . .385 17-20 start bit search example 4. . . . . . . . . . . . . . . . . . . . . . . . . . .386 17-21 start bit search example 5. . . . . . . . . . . . . . . . . . . . . . . . . . .386 17-22 start bit search example 6. . . . . . . . . . . . . . . . . . . . . . . . . . .387 17-23 slow data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .388 17-24 fast data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .389 17-25 single-wire operation (loops = 1, rsrc = 1) . . . . . . . . . .392 17-26 loop operation (loops = 1, rsrc = 0). . . . . . . . . . . . . . . .393 18-1 spi block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .399 18-2 spi control register 1 (spicr1) . . . . . . . . . . . . . . . . . . . . . .402 18-3 spi control register 2 (spicr2) . . . . . . . . . . . . . . . . . . . . . .405 18-4 spi baud rate register (spibr) . . . . . . . . . . . . . . . . . . . . . .406 18-5 spi status register (spisr) . . . . . . . . . . . . . . . . . . . . . . . . .408 18-6 spi data register (spidr). . . . . . . . . . . . . . . . . . . . . . . . . . .409 18-7 spi pullup and reduced drive register (spipurd) . . . . . . . 410 18-8 spi port data register (spiport) . . . . . . . . . . . . . . . . . . . .411 18-9 spi port data direction register (spiddr) . . . . . . . . . . . . . .412 18-10 full-duplex operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .413 18-11 spi clock format 1 (cpha = 1) . . . . . . . . . . . . . . . . . . . . . . .417 18-12 spi clock format 0 (cpha = 0) . . . . . . . . . . . . . . . . . . . . . . .418 18-13 transmission error due to master/slave clock skew . . . . . .419 19-1 qadc block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .429 19-2 qadc input and output signals. . . . . . . . . . . . . . . . . . . . . . .432 19-3 qadc module configuration register (qadcmcr) . . . . . . .437 19-4 qadc test register (qadctest) . . . . . . . . . . . . . . . . . . . . 438 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . advance information mmc2114 MMC2113 mmc2112 ? rev. 1.0 36 list of figures motorola list of figures figure title page 19-5 qadc port qa data register (portqa) . . . . . . . . . . . . . . .439 19-6 qadc port qb data register (portqb) . . . . . . . . . . . . . . .439 19-7 qadc port qa data direction register (ddrqa) and port qb data direction register (ddrqb) . . . . . . . . 441 19-8 qadc control register 0 (qacr0) . . . . . . . . . . . . . . . . . . . . 442 19-9 qadc control register 1 (qacr1) . . . . . . . . . . . . . . . . . . . . 445 19-10 qadc control register 2 (qacr2) . . . . . . . . . . . . . . . . . . . . 448 19-11 qadc status register 0 (qasr0) . . . . . . . . . . . . . . . . . . . . .453 19-12 queue status transition . . . . . . . . . . . . . . . . . . . . . . . . . . . . .461 19-13 qadc status register 1 (qasr1) . . . . . . . . . . . . . . . . . . . . .462 19-14 conversion command word table (ccw) . . . . . . . . . . . . . .464 19-15 right-justified unsigned result register (rjurr) . . . . . . . .468 19-16 left-justified signed result register (ljsrr). . . . . . . . . . . .469 19-17 left-justified unsigned result register (ljurr). . . . . . . . . . 470 19-18 external multiplexing configuration . . . . . . . . . . . . . . . . . . . .472 19-19 qadc analog subsystem block diagram . . . . . . . . . . . . . . . 474 19-20 conversion timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .475 19-21 bypass mode conversion timing . . . . . . . . . . . . . . . . . . . . . .476 19-22 qadc queue operation with pause . . . . . . . . . . . . . . . . . . .480 19-23 ccw priority situation 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . .483 19-24 ccw priority situation 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . .483 19-25 ccw priority situation 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . .484 19-26 ccw priority situation 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . .484 19-27 ccw priority situation 5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . .485 19-28 ccw priority situation 6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . .486 19-29 ccw priority situation 7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . .486 19-30 ccw priority situation 8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . .487 19-31 ccw priority situation 9 . . . . . . . . . . . . . . . . . . . . . . . . . . . . .487 19-32 ccw priority situation 10 . . . . . . . . . . . . . . . . . . . . . . . . . . . .488 19-33 ccw priority situation 11 . . . . . . . . . . . . . . . . . . . . . . . . . . . .488 19-34 ccw freeze situation 12 . . . . . . . . . . . . . . . . . . . . . . . . . . . .489 19-35 ccw freeze situation 13 . . . . . . . . . . . . . . . . . . . . . . . . . . . .489 19-36 ccw freeze situation 14 . . . . . . . . . . . . . . . . . . . . . . . . . . . .490 19-37 ccw freeze situation 15 . . . . . . . . . . . . . . . . . . . . . . . . . . . .490 19-38 ccw freeze situation 16 . . . . . . . . . . . . . . . . . . . . . . . . . . . .490 19-39 ccw freeze situation 17 . . . . . . . . . . . . . . . . . . . . . . . . . . . .491 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . list of figures mmc2114 MMC2113 mmc2112 ? rev. 1.0 advance information motorola list of figures 37 figure title page 19-40 ccw freeze situation 18 . . . . . . . . . . . . . . . . . . . . . . . . . . . .491 19-41 ccw freeze situation 19 . . . . . . . . . . . . . . . . . . . . . . . . . . . .491 19-42 qadc clock subsystem functions . . . . . . . . . . . . . . . . . . . . 503 19-43 qadc conversion queue operation . . . . . . . . . . . . . . . . . . .506 19-44 equivalent analog input circuitry . . . . . . . . . . . . . . . . . . . . . .510 19-45 errors resulting from clipping . . . . . . . . . . . . . . . . . . . . . . . .511 19-46 external positive edge trigger mode timing with pause. . . .512 19-47 gated mode, single scan timing . . . . . . . . . . . . . . . . . . . . . .514 19-48 gated mode, continuous scan timing. . . . . . . . . . . . . . . . . .514 19-49 star-ground at the point of power supply origin . . . . . . . . . .516 19-50 input pin subjected to negative stress . . . . . . . . . . . . . . . . .518 19-51 input pin subjected to positive stress . . . . . . . . . . . . . . . . . .518 19-52 external multiplexing of analog signal sources . . . . . . . . . . .520 19-53 electrical model of an a/d input pin . . . . . . . . . . . . . . . . . . . .521 20-1 read cycle flowchart. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .535 20-2 write cycle flowchart. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .537 20-3 master mode ? 1-clock read and write cycle . . . . . . . . . . .539 20-4 master mode ? 2-clock read and write cycle . . . . . . . . . . .539 20-5 internal (show) cycle followed by external 1-clock read . .542 20-6 internal (show) cycle followed by external 1-clock write . .543 21-1 chip select block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . 549 21-2 chip select control register 0 (cscr0) . . . . . . . . . . . . . . . . 551 21-3 chip select control register 1 (cscr1) . . . . . . . . . . . . . . . . 552 21-4 chip select control register 2 (cscr2) . . . . . . . . . . . . . . . . 552 21-5 chip select control register 3 (cscr3) . . . . . . . . . . . . . . . . 553 22-1 top-level tap module and low-level (once) tap module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .562 22-2 top-level tap controller state machine . . . . . . . . . . . . . . . .566 22-3 idcode register bit specification. . . . . . . . . . . . . . . . . . . . . 571 22-4 once block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .579 22-5 low-level (once) tap module data registers (drs) . . . . . .580 22-6 once controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .583 22-7 once controller and serial interface . . . . . . . . . . . . . . . . . . .585 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . advance information mmc2114 MMC2113 mmc2112 ? rev. 1.0 38 list of figures motorola list of figures figure title page 22-8 once interface diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . .586 22-9 once command register (ocmr) . . . . . . . . . . . . . . . . . . . .588 22-10 once control register (ocr) . . . . . . . . . . . . . . . . . . . . . . . .590 22-11 once status register (osr) . . . . . . . . . . . . . . . . . . . . . . . . .594 22-12 once memory breakpoint logic . . . . . . . . . . . . . . . . . . . . . .596 22-13 once trace logic block diagram . . . . . . . . . . . . . . . . . . . . .599 22-14 cpu scan chain register (cpuscr) . . . . . . . . . . . . . . . . . .602 22-15 control state register (ctl) . . . . . . . . . . . . . . . . . . . . . . . . .604 22-16 once pc fifo. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .606 22-17 recommended connector interface to jtag/once port . . .609 23-1 clkout timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .626 23-2 clock read/write cycle timing . . . . . . . . . . . . . . . . . . . . . . .627 23-3 read/write cycle timing with wait states . . . . . . . . . . . . . . .628 23-4 show cycle timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .629 23-5 gpio timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .630 23-6 reset and configuration override timing . . . . . . . . . . . . . .631 23-7 spi timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .633 23-8 test clock input timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . .635 23-9 boundary scan (jtag) timing. . . . . . . . . . . . . . . . . . . . . . . .636 23-10 test access port timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . .636 23-11 trst timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .636 23-12 debug event pin timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . .637 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . mmc2114 MMC2113 mmc2112 ? rev. 1.0 advance information motorola list of tables 39 advance information ? mmc2114, MMC2113, and mmc2112 list of tables table title page 1-1 package option summary . . . . . . . . . . . . . . . . . . . . . . . . . . . .46 2-1 register address location map . . . . . . . . . . . . . . . . . . . . . . . .56 3-1 package pinouts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .98 3-2 signal descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .106 4-1 signal properties . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .124 4-2 write-once bits read/write accessibility . . . . . . . . . . . . . . . . 125 4-3 chip configuration module memory map . . . . . . . . . . . . . . . .126 4-4 chip configuration mode selection . . . . . . . . . . . . . . . . . . . .127 4-5 bus monitor timeout values. . . . . . . . . . . . . . . . . . . . . . . . . .129 4-6 reset configuration pin states during reset. . . . . . . . . . . . .133 4-7 configuration during reset . . . . . . . . . . . . . . . . . . . . . . . . . .134 4-8 chip configuration mode selection . . . . . . . . . . . . . . . . . . . .135 4-9 chip select cs0 configuration encoding . . . . . . . . . . . . . . . .136 4-10 boot device selection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .136 4-11 output pad driver strength selection. . . . . . . . . . . . . . . . . . .137 4-12 clock mode selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .137 5-1 reset controller signal properties . . . . . . . . . . . . . . . . . . . . .141 5-2 reset controller address map . . . . . . . . . . . . . . . . . . . . . . . .142 5-3 reset source summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . .147 6-1 cpu and peripherals in low-power modes . . . . . . . . . . . . . .164 7-1 m core instruction set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . advance information mmc2114 MMC2113 mmc2112 ? rev. 1.0 40 list of tables motorola list of tables table title page 8-1 interrupt controller module memory map . . . . . . . . . . . . . . . .180 8-2 mask encoding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .182 8-3 priority select encoding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 191 8-4 fast interrupt vector number . . . . . . . . . . . . . . . . . . . . . . . . .194 8-5 vector table mapping. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .194 8-6 interrupt source assignment . . . . . . . . . . . . . . . . . . . . . . . . .197 10-1 sgfm configuration field . . . . . . . . . . . . . . . . . . . . . . . . . . .211 10-2 sgfm register address map. . . . . . . . . . . . . . . . . . . . . . . . .212 10-3 register bank select decoding . . . . . . . . . . . . . . . . . . . . . . .215 10-4 security states . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .218 10-5 sgfmcmd user mode commands . . . . . . . . . . . . . . . . . . . .226 10-6 flash user mode commands . . . . . . . . . . . . . . . . . . . . . . .234 10-7 sgfm interrupt sources. . . . . . . . . . . . . . . . . . . . . . . . . . . . .240 11-1 signal properties . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .248 11-2 clock module memory map . . . . . . . . . . . . . . . . . . . . . . . . . .249 11-3 system frequency multiplier of the reference frequency in normal pll mode . . . . . . . . . . . . . . . . . . . .251 11-4 stpmd[1:0] operation in stop mode . . . . . . . . . . . . . . . . . . .253 11-5 system clock modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .254 11-6 clock-out and clock-in relationships . . . . . . . . . . . . . . . . . .258 11-7 loss of clock summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . .262 11-8 stop mode operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .263 11-9 charge pump current and mfd in normal mode operation. . . . . . . . . . . . . . . . . . . . . . . . .268 12-1 i/o port module memory map. . . . . . . . . . . . . . . . . . . . . . . . .274 12-2 pepar reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .280 12-3 ports a ? i supported pin functions. . . . . . . . . . . . . . . . . . . . .282 13-1 edge port module memory map . . . . . . . . . . . . . . . . . . . . . . .287 13-2 eppax field settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .289 14-1 watchdog timer module memory map. . . . . . . . . . . . . . . . . .298 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . list of tables mmc2114 MMC2113 mmc2112 ? rev. 1.0 advance information motorola list of tables 41 table title page 15-1 programmable interrupt timer modules memory map . . . . . .308 15-2 prescaler select encoding . . . . . . . . . . . . . . . . . . . . . . . . . . .310 15-3 pit interrupt requests . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .316 16-1 signal properties . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .322 16-2 timer modules memory map . . . . . . . . . . . . . . . . . . . . . . . . .323 16-3 output compare action selection . . . . . . . . . . . . . . . . . . . . .331 16-4 input capture edge selection. . . . . . . . . . . . . . . . . . . . . . . . .332 16-5 prescaler selection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .335 16-6 clock selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 340 16-7 timer settings and pin functions. . . . . . . . . . . . . . . . . . . . . .350 16-8 timer interrupt requests . . . . . . . . . . . . . . . . . . . . . . . . . . . .351 17-1 signal properties . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .358 17-2 serial communications interface module memory map . . . . .359 17-3 sci normal, loop, and single-wire mode pin configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .362 17-4 example baud rates (system clock = 33 mhz) . . . . . . . . . .375 17-5 example 10-bit and 11-bit frames. . . . . . . . . . . . . . . . . . . . .377 17-6 start bit verification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .383 17-7 data bit recovery. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .383 17-8 stop bit recovery . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .384 17-9 sci port control summary . . . . . . . . . . . . . . . . . . . . . . . . . . .394 17-10 sci interrupt request sources. . . . . . . . . . . . . . . . . . . . . . . .395 18-1 signal properties . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .400 18-2 spi memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .402 18-3 ss pin i/o configurations. . . . . . . . . . . . . . . . . . . . . . . . . . . .404 18-4 bidirectional pin configurations . . . . . . . . . . . . . . . . . . . . . . .405 18-5 spi baud rate selection (33-mhz module clock) . . . . . . . . .407 18-6 spi port summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .411 18-7 normal mode and bidirectional mode. . . . . . . . . . . . . . . . . . .421 18-8 spi interrupt request sources . . . . . . . . . . . . . . . . . . . . . . . .424 19-1 multiplexed analog input channels . . . . . . . . . . . . . . . . . . . .435 19-2 qadc memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .436 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . advance information mmc2114 MMC2113 mmc2112 ? rev. 1.0 42 list of tables motorola list of tables table title page 19-3 prescaler f sys divide-by values. . . . . . . . . . . . . . . . . . . . . . .444 19-4 queue 1 operating modes . . . . . . . . . . . . . . . . . . . . . . . . . . .446 19-5 queue 2 operating modes . . . . . . . . . . . . . . . . . . . . . . . . . . .449 19-6 ccw pause bit response . . . . . . . . . . . . . . . . . . . . . . . . . . .455 19-7 queue status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .458 19-8 input sample times . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .465 19-9 non-multiplexed channel assignments and pin designations. . . . . . . . . . . . . . . . . . . . . . . . . . . . .466 19-10 multiplexed channel assignments and pin designations. . . . . . . . . . . . . . . . . . . . . . . . . . . . .467 19-11 analog input channels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .473 19-12 trigger events . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .481 19-13 status bits. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .482 19-14 external circuit settling time to 1/2 lsb . . . . . . . . . . . . . . . .523 19-15 error resulting from input leakage (i off ) . . . . . . . . . . . . . . . .524 19-16 qadc status flags and interrupt sources. . . . . . . . . . . . . . .524 20-1 signal properties . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .529 20-2 data transfer cases. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .533 20-3 eb[3:0] assertion encoding . . . . . . . . . . . . . . . . . . . . . . . . . .534 20-4 emulation mode chip-select summary . . . . . . . . . . . . . . . . .541 20-5 transfer code definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . .544 20-6 processor status encoding . . . . . . . . . . . . . . . . . . . . . . . . . .544 21-1 signal properties . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .550 21-2 chip select memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . .550 21-3 chip select wait states encoding . . . . . . . . . . . . . . . . . . . . .555 21-4 chip select address range encoding . . . . . . . . . . . . . . . . . .557 22-1 jtag instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .568 22-2 list of pins not scanned in jtag mode . . . . . . . . . . . . . . . .574 22-3 boundary scan register definition. . . . . . . . . . . . . . . . . . . . .575 22-4 once register addressing. . . . . . . . . . . . . . . . . . . . . . . . . . .589 22-5 sequential control field settings . . . . . . . . . . . . . . . . . . . . . .591 22-6 memory breakpoint control field settings . . . . . . . . . . . . . . .593 22-7 processor mode field settings. . . . . . . . . . . . . . . . . . . . . . . .595 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . list of tables mmc2114 MMC2113 mmc2112 ? rev. 1.0 advance information motorola list of tables 43 table title page 23-1 absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . .613 23-2 thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . .614 23-3 esd protection characteristics . . . . . . . . . . . . . . . . . . . . . . .615 23-4 dc electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . 616 23-5 pll electrical specifications. . . . . . . . . . . . . . . . . . . . . . . . . .618 23-6 qadc absolute maximum ratings. . . . . . . . . . . . . . . . . . . . .620 23-7 qadc electrical specifications (operating) . . . . . . . . . . . . . .621 23-8 qadc conversion specifications (operating) . . . . . . . . . . . .622 23-9 sgfm flash program and erase characteristics . . . . . . . .624 23-10 sgfm flash module life characteristics . . . . . . . . . . . . . .624 23-11 external interface timing characteristics . . . . . . . . . . . . . . .625 23-12 gpio timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .630 23-13 reset and configuration override timing . . . . . . . . . . . . . . .631 23-14 spi timing characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . .632 23-15 once, jtag, and boundary scan timing . . . . . . . . . . . . . . .635 25-1 mc order numbers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .647 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . advance information mmc2114 MMC2113 mmc2112 ? rev. 1.0 44 list of tables motorola list of tables f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . mmc2114 MMC2113 mmc2112 ? rev. 1.0 advance information motorola general description 45 advance information ? mmc2114, MMC2113, and mmc2112 section 1. general description 1.1 contents 1.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .45 1.3 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .46 1.4 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 1.2 introduction the mmc2114, MMC2113, and mmc2112 are members of a family of general-purpose microcontrollers (mcu) based on the m core m210 central processor unit (cpu). these are low-voltage devices that operate between 2.7 volts and 3.6 volts. they are well suited for use in battery-powered applications. the maximum operating frequency is 33 mhz over a temperature range of ? 40 c to 85 c. available packages are: 100-pin low-profile quad flat pack (lqfp) for single-chip mode operation 144-pin lqfp for applications requiring an external memory interface or a large number of general-purpose inputs/outputs (gpio) 196-ball plastic mold array process ball grid array (mapbga) providing the same functionality as the 144-pin lqfp in a smaller form factor table 1-1 summarizes the memory sizes, package options, and operating modes of the mmc2112, MMC2113, and mmc2114. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . advance information mmc2114 MMC2113 mmc2112 ? rev. 1.0 46 general description motorola general description note: the MMC2113 may contain more than 8k of internal sram, but only the 8k range from 0x0080_0000 to 0x0080_1fff is tested and guaranteed to be operational. it is recommended that internal sram outside this range not be used. accesses to sram outside this range terminate without a transfer error exception. 1.3 features features include: m core m210 integer processor: ? 32-bit reduced instruction set computer (risc) architecture ? low power and high performance once debug support 128 kbytes (MMC2113) or 256 kbytes (mmc2114) flash memory (1) : ? single cycle byte, half-word (16-bit) and word (32-bit) reads ? fast automated program and erase cycles ? ability to program one flash bank while executing from another (mmc2114 only) ? interrupt on program/erase command completion ? flexible protection scheme for accidental program/erase ? access restriction controls for both supervisor/user and data/program spaces table 1-1. package option summary device on-chip sram (kbytes) on-chip flash (kbytes) packages operating modes (1) 1. see 4.4 modes of operation for descriptions of the different mcu operating modes. mmc2112 32 ? 144 lqfp 196 mapbga master only MMC2113 8 128 100 lqfp 144 lqfp 196 mapbga single chip master emulation mmc2114 32 256 1. the mmc2112 has no integrated flash memory and is intended for use with external non-volatile memory devices. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . general description features mmc2114 MMC2113 mmc2112 ? rev. 1.0 advance information motorola general description 47 ? enhanced security feature prevents unauthorized access to contents of flash (protects company ip) ? single supply operation (no need for separate, high voltage program/erase supply) 8 kbytes (MMC2113) or 32 kbytes (mmc2112 and mmc2114) of static random-access memory (sram): ? single cycle byte, half-word (16-bit), and word (32-bit) reads and writes ? standby power supply support serial peripheral interface (spi): ? master mode and slave mode ? wired-or mode ? slave select output ? mode fault error flag with cpu interrupt capability ? double-buffered receiver ? serial clock with programmable polarity and phase ? control of spi operation during wait mode ? reduced drive control ? general-purpose input/output (i/o) capability two serial communications interfaces (sci): ? full-duplex operation ? standard mark/space non-return-to-zero (nrz) format ? 13-bit baud rate prescaler ? programmable 8-bit or 9-bit data format ? separately enabled transmitter and receiver ? separate receiver and transmitter cpu interrupt requests ? two receiver wakeup methods (idle line and address mark) ? receiver framing error detection ? hardware parity checking ? 1/16 bit-time noise detection ? reduced drive control ? general-purpose i/o capability f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . advance information mmc2114 MMC2113 mmc2112 ? rev. 1.0 48 general description motorola general description two timers: ? four 16-bit input capture/output compare channels ? 16-bit architecture ? 16-bit pulse accumulator ? pulse widths variable from microseconds to seconds ? eight selectable prescalers ? toggle-on-overflow feature for pulse-width modulation queued analog-to-digital converter (qadc): ? eight analog input channels ? 10-bit resolution 2 counts accuracy ? minimum 7 s conversion time ? internal sample and hold ? programmable input sample time for various source impedances ? two conversion command queues with a total of 64 entries ? subqueues possible using pause mechanism ? queue complete and pause interrupts available on both queues ? queue pointers indicate current location for each queue ? automated queue modes initiated by: external edge trigger and gated trigger periodic/interval timer, within queued analog-to-digital converter (qadc) module {queue1 and queue2} software command ? single-scan or continuous-scan of queues ? output data readable in three formats: right-justified unsigned left-justified signed left-justified unsigned ? unused analog channels can be used as digital i/o ? minimum pin set configuration implemented f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . general description features mmc2114 MMC2113 mmc2112 ? rev. 1.0 advance information motorola general description 49 interrupt controller: ? up to 40 interrupt sources ? 32 unique programmable priority levels for each interrupt source ? independent enable/disable of pending interrupts based on priority level ? normal or fast interrupt request for each priority level ? fast interrupt requests always have priority over normal interrupts ? ability to mask interrupts at and below a defined priority level ? ability to select between autovectored or vectored interrupt requests ? vectored interrupts generated based on priority level ? ability to generate a separate vector number for normal and fast interrupts ? ability for software to self-schedule interrupts ? software visibility of pending interrupts and interrupt signals to core ? asynchronous operation to support wakeup from low-power modes external interrupts supported: ? rising/falling edge select ? low-level sensitive ? ability for software generation of external interrupt event ? interrupt pins configurable as general-purpose i/o two periodic interval timers: ? 16-bit counter with modulus "initial count" register ? selectable as free running or count down ? 16 selectable prescalers ? 2 0 to 2 15 watchdog timer: ? 16-bit counter with modulus "initial count" register ? pause option for low-power modes f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . advance information mmc2114 MMC2113 mmc2112 ? rev. 1.0 50 general description motorola general description phase-lock loop (pll): ? reference crystal from 2 to 10 mhz ? low-power modes supported ? separate clock-out signal integrated low-voltage detector (lvd): ? can be enabled and disabled under software control ? sets flag when v dd drops below internal bandgap reference threshold ? reset and interrupt request enable bits ? optional automatic disabling in low-power stop mode reset: ? separate reset in and reset out signals ? seven sources of reset: power-on reset (por) external software watchdog timer loss of clock loss of pll lock low-voltage detect ? status flag indicates source of last reset chip configurations: ? support for single-chip, master, emulation, and test modes ? system configuration during reset ? bus monitor ? configurable output pad drive strength control general-purpose input/output (gpio): ? up to 72 bits of gpio ? coherent 32-bit control ? bit manipulation supported via set/clear functions ? unused peripheral pins may be used as extra gpio. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . general description block diagram mmc2114 MMC2113 mmc2112 ? rev. 1.0 advance information motorola general description 51 external bus interface: ? provides for direct support of asynchronous random-access memory (ram), read-only memory (rom), flash, and memory mapped peripherals ? bidirectional data bus with wide (32-bit) and narrow (16-bit) modes ? 23-bit address bus with four chip selects provide access to 32 mbytes of external memory ? byte/write enables ? boot from on-chip flash or external memories ? internal bus activity is visible via show-cycle mode ? special chip selects support replacement of gpio with external port replacement logic joint test action group (jtag) support for system-level board testing 1.4 block diagram the basic structure of these devices is shown in figure 1-1 . f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . advance information mmc2114 MMC2113 mmc2112 ? rev. 1.0 52 general description motorola general description figure 1-1. block diagram flash controller osc/pll reset spi sram sci1 sci2 interrupt ipbus interface tms tdi tdo tclk de trst int[7:0] miso txd2 rxd2 tim1 tim2 icoc1[3:0] pqb[3:0] v rl , v rh v dda , v ssa extal xtal pllen clkout reset rstout d[31:0] v ss x 8 v dd x 8 ports 128 kbytes (MMC2113) 8 kbytes (MMC2113) v stby icoc2[3:0] txd1 rxd1 por programmable interval timer 2 watchdog timer adc mosi sck ss cs test programmable interval timer 1 edge port pstat[3:0] cpu a[22:0] r/w eb[3:0] cs[3:0] tc[2:0] shs cse[1:0] ta tea oe test pqa[4:3] pqa[1:0] v ddh cpu bus external memory interface ipbus once jtag tap 32 kbytes (mmc2112/4) 256 kbytes (mmc2114) v ddf v ssf lvd 0 kbyte (mmc2112) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . mmc2114 MMC2113 mmc2112 ? rev. 1.0 advance information motorola system memory map 53 advance information ? mmc2114, MMC2113, and mmc2112 section 2. system memory map 2.1 contents 2.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .53 2.3 address map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .54 2.4 register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .57 2.2 introduction the address maps, shown in figure 2-1 , figure 2-2 , and figure 2-3 , include: internal flash: ? 256 kbytes (mmc2114) ? 128 kbytes (MMC2113) ? 0 kbytes (mmc2112) internal static random-access memory (sram): ? 32 kbytes (mmc2112 and mmc2114) ? 8 kbytes (MMC2113) internal memory mapped registers external address space f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . advance information mmc2114 MMC2113 mmc2112 ? rev. 1.0 54 system memory map motorola system memory map 2.3 address map figure 2-1. mmc2112 address map figure 2-2. MMC2113 address map internal sram external memory 0x00c0_0000 0x0080_0000 32 kbytes 0x0080_7fff registers see table 2-1 0x8000_0000 0xffff_ffff 0x00d0_002f 0x0000_0000 internal flash internal sram external memory 0x00c0_0000 0x0000_0000 8 kbytes 128 kbytes 0x0080_1fff registers see table 2-1 0x8000_0000 0x0080_0000 0xffff_ffff 0x00d0_002f 0x0001_ffff f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . system memory map address map mmc2114 MMC2113 mmc2112 ? rev. 1.0 advance information motorola system memory map 55 note: the MMC2113 may contain more than 8k of internal sram, but only the 8k range from 0x0080_0000 to 0x0080_1fff is tested and guaranteed to be operational. it is recommended that internal sram outside this range not be used. accesses to sram outside this range terminate without a transfer error exception. figure 2-3. mmc2114 address map internal flash internal sram external memory 0x00c0_0000 0x0000_0000 32 kbytes 256 kbytes 0x0080_0000 registers see table 2-1 0x8000_0000 0x0080_7fff 0x0003_ffff 0x00d0_002f 0xffff_ffff f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . advance information mmc2114 MMC2113 mmc2112 ? rev. 1.0 56 system memory map motorola system memory map table 2-1. register address location map (1) 1. see module sections for details of how much of each block is being decoded. accesses to addresses outside the module memory maps (and also the reserved area 0x00d1_0000 ? 0x7fff_ffff) will not be responded to and will result in a bus monitor transfer error exception. base address (hex) maximum size usage 0x00c0_0000 64 kbyte ports (2) (ports) 2. the port register space is mirrored/repeated in the 64-kbyte block. this allows the full 64- kbyte block to be decoded and used to execute an external access to a port replacement unit in emulation mode. 0x00c1_0000 64 kbyte chip configuration (ccm) 0x00c2_0000 64 kbyte chip selects (cs) 0x00c3_0000 64 kbyte clocks (clock) 0x00c4_0000 64 kbyte reset (r eset) 0x00c5_0000 64 kbyte interrupt controller (intc) 0x00c6_0000 64 kbyte edge port (eport) 0x00c7_0000 64 kbyte watchdog timer (wdt) 0x00c8_0000 64 kbyte programmable interrupt timer 1 (pit1) 0x00c9_0000 64 kbyte programmable interrupt timer 2 (pit2) 0x00ca_0000 64 kbyte queued analog-to-digital converter (qadc) 0x00cb_0000 64 kbyte serial peripheral interface (spi) 0x00cc_0000 64 kbyte serial communications interface 1 (sci1) 0x00cd_0000 64 kbyte serial communications interface 2 (sci2) 0x00ce_0000 64 kbyte timer 1 (tim1) 0x00cf_0000 64 kbyte timer 2 (tim2) 0x00d0_0000 64 kbyte flash registers (sgfm) 0x8000_0000 2 gbyte external memory f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . system memory map register map mmc2114 MMC2113 mmc2112 ? rev. 1.0 advance information motorola system memory map 57 2.4 register map address register name bit number ports (ports) bit 7654321bit 0 0x00c0_0000 port a output data register (porta) see page 275. read: porta7 porta6 porta5 porta4 porta3 porta2 porta1 porta0 write: reset:11111111 bit 7654321bit 0 0x00c0_0001 port b output data register (portb) see page 275. read: portb7 portb6 portb5 portb4 portb3 portb2 portb1 portb0 write: reset:11111111 bit 7654321bit 0 0x00c0_0002 port c output data register (portc) see page 275. read: portc7 portc6 portc5 portc4 portc3 portc2 portc1 portc0 write: reset:11111111 bit 7654321bit 0 0x00c0_0003 port d output data register (portd) see page 275. read: portd7 portd6 portd5 portd4 portd3 portd2 portd1 portd0 write: reset:11111111 bit 7654321bit 0 0x00c0_0004 port e output data register (porte) see page 275. read: porte7 porte6 porte5 porte4 porte3 porte2 porte1 porte0 write: reset:11111111 bit 7654321bit 0 0x00c0_0005 port f output data register (portf) see page 275. read: portf7 portf6 portf5 portf4 portf3 portf2 portf1 portf0 write: reset:11111111 bit 7654321bit 0 0x00c0_0006 port g output data register (portg) see page 275. read: portg7 portg6 portg5 portg4 portg3 portg2 portg1 portg0 write: reset:11111111 p = current pin state u = unaffected = writes have no effect and the access terminates without a transfer error exception. figure 2-4. register summary (sheet 1 of 37) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . advance information mmc2114 MMC2113 mmc2112 ? rev. 1.0 58 system memory map motorola system memory map bit 7654321bit 0 0x00c0_0007 port h output data register (porth) see page 275. read: porth7 porth6 porth5 porth4 porth3 porth2 porth1 porth0 write: reset:11111111 bit 7654321bit 0 0x00c0_0008 port i output data register (porti) see page 275. read: porti7 porti6 porti5 porti4 porti3 porti2 porti1 porti0 write: reset:11111111 bit 7654321bit 0 0x00c0_0009 0x00c0_000b reserved writes have no effect, reads return 0s, and the access terminates without a transfer error exception. bit 7654321bit 0 0x00c0_000c port a data direction register (ddra) see page 276. read: ddra7 ddra6 ddra5 ddra4 ddra3 ddra2 ddra1 ddra0 write: reset:00000000 bit 7654321bit 0 0x00c0_000d port b data direction register (ddrb) see page 276. read: ddrb7 ddrb6 ddrb5 ddrb4 ddrb3 ddrb2 ddrb1 ddrb0 write: reset:00000000 bit 7654321bit 0 0x00c0_000e port c data direction register (ddrc) see page 276. read: ddrc7 ddrc6 ddrc5 ddrc4 ddrc3 ddrc2 ddrc1 ddrc0 write: reset:00000000 bit 7654321bit 0 0x00c0_000f port d data direction register (ddrd) see page 276. read: ddrd7 ddrd6 ddrd5 ddrd4 ddrd3 ddrd2 ddrd1 ddrd0 write: reset:00000000 bit 7654321bit 0 0x00c0_0010 port e data direction register (ddre) see page 276. read: ddre7 ddre6 ddre5 ddre4 ddre3 ddre2 ddre1 ddre0 write: reset:00000000 address register name bit number p = current pin state u = unaffected = writes have no effect and the access terminates without a transfer error exception. figure 2-4. register summary (sheet 2 of 37) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . system memory map register map mmc2114 MMC2113 mmc2112 ? rev. 1.0 advance information motorola system memory map 59 bit 7654321bit 0 0x00c0_0011 port f data direction register (ddrf) see page 276. read: ddrf7 ddrf6 ddrf5 ddrf4 ddrf3 ddrf2 ddrf1 ddrf0 write: reset:00000000 bit 7654321bit 0 0x00c0_0012 port g data direction register (ddrg) see page 276. read: ddrg7 ddrg6 ddrg5 ddrg4 ddrg3 ddrg2 ddrg1 ddrg0 write: reset:00000000 bit 7654321bit 0 0x00c0_0013 port h data direction register (ddrh) see page 276. read: ddrh7 ddrh6 ddrh5 ddrh4 ddrh3 ddrh2 ddrh1 ddrh0 write: reset:00000000 bit 7654321bit 0 0x00c0_0014 port i data direction register (ddri) see page 276. read: ddri7 ddri6 ddri5 ddri4 ddri3 ddri2 ddri1 ddri0 write: reset:00000000 bit 7654321bit 0 0x00c0_0015 0x00c0_0017 reserved writes have no effect, reads return 0s, and the access terminates without a transfer error exception. bit 7654321bit 0 0x00c0_0018 port a pin data/set data register (portap/seta) see page 277. read: portap7 portap6 portap5 portap4 portap3 portap2 portap1 portap0 write: seta7 seta6 seta5 seta4 seta3 seta2 seta1 seta0 reset:pppppppp bit 7654321bit 0 0x00c0_0019 port b pin data/set data register (portbp/setb) see page 277. read: portbp7 portbp6 portbp5 portbp4 portbp3 portbp2 portbp1 portbp0 write: setb7 setb6 setb5 setb4 setb3 setb2 setb1 setb0 reset:pppppppp bit 7654321bit 0 0x00c0_001a port c pin data/set data register (portcp/setc) see page 277. read: portcp7 portcp6 portcp5 portcp4 portcp3 portcp2 portcp1 portcp0 write: setc7 setc6 setc5 setc4 setc3 setc2 setc1 setc0 reset:pppppppp address register name bit number p = current pin state u = unaffected = writes have no effect and the access terminates without a transfer error exception. figure 2-4. register summary (sheet 3 of 37) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . advance information mmc2114 MMC2113 mmc2112 ? rev. 1.0 60 system memory map motorola system memory map bit 7654321bit 0 0x00c0_001b port d pin data/set data register (portdp/setd) see page 277. read: portdp7 portdp6 portdp5 portdp4 portdp3 portdp2 portdp1 portdp0 write: setd7 setd6 setd5 setd4 setd3 setd2 setd1 setd0 reset:pppppppp bit 7654321bit 0 0x00c0_001c port e pin data/set data register (portep/sete) see page 277. read: portep7 portep6 portep5 portep4 portep3 portep2 portep1 portep0 write: sete7 sete6 sete5 sete4 sete3 sete2 sete1 sete0 reset:pppppppp bit 7654321bit 0 0x00c0_001d port f pin data/set data register (portfp/setf) see page 277. read: portfp7 portfp6 portfp5 portfp4 portfp3 portfp2 portfp1 portfp0 write: setf7 setf6 setf5 setf4 setf3 setf2 setf1 setf0 reset:pppppppp bit 7654321bit 0 0x00c0_001e port g pin data/set data register (portgp/setg) see page 277. read: portgp7 portgp6 portgp5 portgp4 portgp3 portgp2 portgp1 portgp0 write: setg7 setg6 setg5 setg4 setg3 setg2 setg1 setg0 reset:pppppppp bit 7654321bit 0 0x00c0_001f port h pin data/set data register (porthp/seth) see page 277. read: porthp7 porthp6 porthp5 porthp4 porthp3 porthp2 porthp1 porthp0 write: seth7 seth6 seth5 seth4 seth3 seth2 seth1 seth0 reset:pppppppp bit 7654321bit 0 0x00c0_0020 port i pin data/set data register (portip/seti) see page 277. read: portip7 portip6 portip5 portip4 portip3 portip2 portip1 portip0 write: seti7 seti6 seti5 seti4 seti3 seti2 seti1 seti0 reset:pppppppp bit 7654321bit 0 0x00c0_0021 0x00c0_0023 reserved writes have no effect, reads return 0s, and the access terminates without a transfer error exception. bit 7654321bit 0 0x00c0_0024 port a clear output data register (clra) see page 278. read:00000000 write: clra7 clra6 clra5 clra4 clra3 clra2 clra1 clra0 reset:00000000 address register name bit number p = current pin state u = unaffected = writes have no effect and the access terminates without a transfer error exception. figure 2-4. register summary (sheet 4 of 37) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . system memory map register map mmc2114 MMC2113 mmc2112 ? rev. 1.0 advance information motorola system memory map 61 bit 7654321bit 0 0x00c0_0025 port b clear output data register (clrb) see page 278. read:00000000 write: clrb7 clrb6 clrb5 clrb4 clrb3 clrb2 clrb1 clrb0 reset:00000000 bit 7654321bit 0 0x00c0_0026 port c clear output data register (clrc) see page 278. read:00000000 write: clrc7 clrc6 clrc5 clrc4 clrc3 clrc2 clrc1 clrc0 reset:00000000 bit 7654321bit 0 0x00c0_0027 port d clear output data register (clrd) see page 278. read:00000000 write: clrd7 clrd6 clrd5 clrd4 clrd3 clrd2 clrd1 clrd0 reset:00000000 bit 7654321bit 0 0x00c0_0028 port e clear output data register (clre) see page 278. read:00000000 write: clre7 clre6 clre5 clre4 clre3 clre2 clre1 clre0 reset:00000000 bit 7654321bit 0 0x00c0_0029 port f clear output data register (clrf) see page 278. read:00000000 write: clrf7 clrf6 clrf5 clrf4 clrf3 clrf2 clrf1 clrf0 reset:00000000 bit 7654321bit 0 0x00c0_002a port g clear output data register (clrg) see page 278. read:00000000 write: clrg7 clrg6 clrg5 clrg4 clrg3 clrg2 clrg1 clrg0 reset:00000000 bit 7654321bit 0 0x00c0_002b port h clear output data register (clrh) see page 278. read:00000000 write: clrh7 clrh6 clrh5 clrh4 clrh3 clrh2 clrh1 clrh0 reset:00000000 address register name bit number p = current pin state u = unaffected = writes have no effect and the access terminates without a transfer error exception. figure 2-4. register summary (sheet 5 of 37) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . advance information mmc2114 MMC2113 mmc2112 ? rev. 1.0 62 system memory map motorola system memory map bit 7654321bit 0 0x00c0_002c port i clear output data register (clri) see page 278. read:00000000 write: clri7 clri6 clri5 clri4 clri3 clri2 clri1 clri0 reset:00000000 bit 7654321bit 0 0x00c0_002d 0x00c0_002f reserved writes have no effect, reads return 0s, and the access terminates without a transfer error exception. bit 7654321bit 0 0x00c0_0030 port c/d pin assignment register (pcdpar) see page 279. read: pcdpa 0000000 write: reset:see note0000000 note: reset state determined during reset configuration. pcdpa = 1 except in single-chip mode or when an external boot device is selected with a 16-bit port size in master mode. bit 7654321bit 0 0x00c0_0031 port e pin assignment register (pepar) see page 280. read: pepa7 pepa6 pepa5 pepa4 pepa3 pepa2 pepa1 pepa0 write: reset: reset state determined during reset configuration as shown in table 12-2. pepar reset values . bit 7654321bit 0 0x00c0_0032 0x00c0_003f reserved writes have no effect, reads return 0s, and the access terminates without a transfer error exception. bit 7654321bit 0 0x00c0_0040 0x00c0_ffff reserved ports register space (block of 0x00c0_0000 through 0x00c0_003f) is mirrored/repeated. address register name bit number p = current pin state u = unaffected = writes have no effect and the access terminates without a transfer error exception. figure 2-4. register summary (sheet 6 of 37) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . system memory map register map mmc2114 MMC2113 mmc2112 ? rev. 1.0 advance information motorola system memory map 63 chip configuration module (ccm) bit 15 14 13 12 11 10 9 bit 8 0x00c1_0000 0x00c1_0001 chip configuration register (ccr) see page 126. read: load 0 shen emint 0 mode2 mode1 mode0 write: reset: note 1 0 note 2 note 2 0 note 1 note 1 note 1 bit 7654321bit 0 read: 0 szen psten shint bme bmd bmt1 bmt0 write: reset: 0 note 3 note 2 0 1 0 0 0 notes: 1. determined during reset configuration 2. 0 for all configurations except emulation mode, 1 for emulation mode 3. 0 for all configurations except emulation and master modes, 1 for emulation and master modes bit 7654321bit 0 0x00c1_0002 reserved writes have no effect, reads return 0s, and the access terminates without a transfer error exception. bit 7654321bit 0 0x00c1_0003 reserved writes have no effect, reads return 0s, and the access terminates without a transfer error exception. bit 15 14 13 12 11 10 9 bit 8 0x00c1_0004 0x00c1_0005 reset configuration register (rcon) see page 129. read:00000000 write: reset:00000000 bit 7654321bit 0 read: 1 rpllsel 1 rpllref 0 rload 0 1 bootps 0 bootsel 0 0 mode write: reset:11001000 address register name bit number p = current pin state u = unaffected = writes have no effect and the access terminates without a transfer error exception. figure 2-4. register summary (sheet 7 of 37) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . advance information mmc2114 MMC2113 mmc2112 ? rev. 1.0 64 system memory map motorola system memory map bit 15 14 13 12 11 10 9 bit 8 0x00c1_0006 0x00c1_0007 chip identification register (cir) see page 131. read: 0 pin7 0 pin6 0 pin5 1 pin4 0 pin3 1 pin2 1 pin1 1 pin0 write: reset:00010111 bit 7654321bit 0 read: 0 prn7 0 prn6 0 prn5 0 prn4 0 prn3 0 prn2 0 prn1 0 prn0 write: reset:00000000 bit 15 14 13 12 11 10 9 bit 8 0x00c1_0008 0x00c1_0009 chip test register (ctr) see page 132. read:00000000 write: reset:00000000 bit 7654321bit 0 read:00000000 write: reset:00000000 bit 7654321bit 0 0x00c1_000a 0x00c1_000b reserved writes have no effect, reads return 0s, and the access terminates without a transfer error exception. bit 7654321bit 0 0x00c1_000c 0x00c1_000f unimplemented access results in the module generating an access termination transfer error. bit 7654321bit 0 0x00c1_0010 0x00c1_ffff unimplemented access results in a bus monitor timeout generating an access termination transfer error. address register name bit number p = current pin state u = unaffected = writes have no effect and the access terminates without a transfer error exception. figure 2-4. register summary (sheet 8 of 37) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . system memory map register map mmc2114 MMC2113 mmc2112 ? rev. 1.0 advance information motorola system memory map 65 chip selects (cs) bit 15 14 13 12 11 10 9 bit 8 0x00c2_0000 0x00c2_0001 chip select control register 0 (cscr0) see page 551. read: so ro ps wws we ws2 ws1 ws0 write: reset: 0 0 see note 1 1 1 1 1 bit 7654321bit 0 read:000000 taen csen write: reset:0000001see note note: reset state determined during reset configuration. bit 15 14 13 12 11 10 9 bit 8 0x00c2_0002 0x00c2_0003 chip select control register 1 (cscr1) see page 552. read: so ro ps wws we ws2 ws1 ws0 write: reset:00111111 bit 7654321bit 0 read:000000 taen csen write: reset:0000001see note note: reset state determined during reset configuration bit 15 14 13 12 11 10 9 bit 8 0x00c2_0004 0x00c2_0005 chip select control register 2 (cscr2) see page 552. read: so ro ps wws we ws2 ws1 ws0 write: reset:00111111 bit 7654321bit 0 read:000000 taen csen write: reset:00000010 address register name bit number p = current pin state u = unaffected = writes have no effect and the access terminates without a transfer error exception. figure 2-4. register summary (sheet 9 of 37) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . advance information mmc2114 MMC2113 mmc2112 ? rev. 1.0 66 system memory map motorola system memory map bit 15 14 13 12 11 10 9 bit 8 0x00c2_0006 0x00c2_0007 chip select control register 3 (cscr3) see page 553. read: so ro ps wws we ws2 ws1 ws0 write: reset:00111111 bit 7654321bit 0 read:000000 taen csen write: reset:00000010 bit 7654321bit 0 0x00c2_0008 0x00c2_ffff unimplemented access results in a bus monitor timeout generating an access termination transfer error. clocks (clock) bit 15 14 13 12 11 10 9 bit 8 0x00c3_0000 0x00c3_0001 synthesizer control register (syncr) see page 250. read: lolre mfd2 mfd1 mfd0 locre rfd2 rfd1 rfd0 write: reset:00100001 bit 7654321bit 0 read: locen disclk fwkup rsvd4 stmpd1 stmpd0 rsvd1 rsvd0 write: reset:00000000 bit 7654321bit 0 0x00c3_0002 synthesizer status register (synsr) see page 253. read: pllmode pllsel pllref locks lock locs 0 0 write: reset: note 1 note 1 note 1 note 2 note 2 0 0 0 notes: 1. reset state determined during reset configuration 2. see the locks and lock bit descriptions. address register name bit number p = current pin state u = unaffected = writes have no effect and the access terminates without a transfer error exception. figure 2-4. register summary (sheet 10 of 37) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . system memory map register map mmc2114 MMC2113 mmc2112 ? rev. 1.0 advance information motorola system memory map 67 bit 7654321bit 0 0x00c3_0003 synthesizer test register (syntr) see page 256. read:00000000 write: reset:00000000 bit 31 30 29 28 27 26 25 bit 24 0x00c3_0004 0x00c3_0005 0x00c3_0006 0x00c3_0007 synthesizer test register 2 (syntr2) see page 257. read:00000000 write: reset:00000000 bit 23 22 21 20 19 18 17 bit 16 read:00000000 write: reset:00000000 bit 15 14 13 12 11 10 9 bit 8 read:000000 rsvd9 rsvd8 write: reset:00000000 bit 7654321bit 0 read: rsvd7 rsvd6 rsvd5 rsvd4 rsvd3 rsvd2 rsvd2 rsvd0 write: reset:00000000 bit 7654321bit 0 0x00c3_0008 0x00c3_ffff unimplemented access results in a bus monitor timeout generating an access termination transfer error. reset (reset) bit 7654321bit 0 0x00c4_0000 reset control register (rcr) see page 143. read: softrst frc- rstout 0 lvdf lvdie lvdre lvdse lvde write: reset: 0 0 0 see note 0 0 0 0 note: reset dependent address register name bit number p = current pin state u = unaffected = writes have no effect and the access terminates without a transfer error exception. figure 2-4. register summary (sheet 11 of 37) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . advance information mmc2114 MMC2113 mmc2112 ? rev. 1.0 68 system memory map motorola system memory map bit 7654321bit 0 0x00c4_0001 reset status register (rsr) see page 143. read: 0 lvd soft wdr por ext loc lol write: reset: 0 reset dependent bit 7654321bit 0 0x00c4_0002 reset test register (rtr) read:00000000 write: reset:00000000 bit 7654321bit 0 0x00c4_0003 reserved writes have no effect, reads return 0s, and the access terminates without a transfer error exception. bit 7654321bit 0 0x00c4_0004 0x00c4_ffff unimplemented access results in a bus monitor timeout generating an access termination transfer error. interrupt controller (intc) bit 15 14 13 12 11 10 9 bit 8 0x00c5_0000 0x00c5_0001 interrupt control register (icr) see page 181. read: ae fve me mfi 0000 write: reset:10000000 bit 7654321bit 0 read: 0 0 0 mask4 mask3 mask2 mask1 mask0 write: reset:00000000 bit 15 14 13 12 11 10 9 bit 8 0x00c5_0002 0x00c5_0003 interrupt status register (isr) see page 183. read:000000intfint write: reset:00000000 bit 7654321bit 0 read:0 vec6vec5vec4vec3vec2vec1vec0 write: reset:00000000 address register name bit number p = current pin state u = unaffected = writes have no effect and the access terminates without a transfer error exception. figure 2-4. register summary (sheet 12 of 37) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . system memory map register map mmc2114 MMC2113 mmc2112 ? rev. 1.0 advance information motorola system memory map 69 bit 31 30 29 28 27 26 25 bit 24 0x00c5_0004 0x00c5_0005 0x00c5_0006 0x00c5_0007 interrupt force register high (ifrh) see page 184. read:00000000 write: reset:00000000 bit 23 22 21 20 19 18 17 bit 16 read:00000000 write: reset:00000000 bit 15 14 13 12 11 10 9 bit 8 read:00000000 write: reset:00000000 bit 7654321bit 0 read: if39 if38 if37 if36 if35 if34 if33 if32 write: reset:00000000 bit 31 30 29 28 27 26 25 bit 24 0x00c5_0008 0x00c5_0009 0x00c5_000a 0x00c5_000b interrupt force register low (ifrl) see page 185. read: if31 if30 if29 if28 if27 if26 if25 if24 write: reset:00000000 bit 23 22 21 20 19 18 17 bit 16 read: if23 if22 if21 if20 if19 if18 if17 if16 write: reset:00000000 bit 15 14 13 12 11 10 9 bit 8 read: if15 if14 if13 if12 if11 if10 if9 if8 write: reset:00000000 bit 7654321bit 0 read: if7 if6 if5 if4 if3 if2 if1 if0 write: reset:00000000 address register name bit number p = current pin state u = unaffected = writes have no effect and the access terminates without a transfer error exception. figure 2-4. register summary (sheet 13 of 37) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . advance information mmc2114 MMC2113 mmc2112 ? rev. 1.0 70 system memory map motorola system memory map bit 31 30 29 28 27 26 25 bit 24 0x00c5_000c 0x00c5_000d 0x00c5_000e 0x00c5_000f interrupt pending register (ipr) see page 186. read:ip31ip30ip29ip28ip27ip26ip25ip24 write: reset:00000000 bit 23 22 21 20 19 18 17 bit 16 read:ip23ip22ip21ip20ip19ip18ip17ip16 write: reset:00000000 bit 15 14 13 12 11 10 9 bit 8 read:ip15ip14ip13ip12ip11ip10 ip9 ip8 write: reset:00000000 bit 7654321bit 0 read:ip7ip6ip5ip4ip3ip2ip1ip0 write: reset:00000000 bit 31 30 29 28 27 26 25 bit 24 0x00c5_0010 0x00c5_0011 0x00c5_0012 0x00c5_0013 normal interrupt enable register (nier) see page 187. read: nie31 nie30 nie29 nie28 nie27 nie26 nie25 nie24 write: reset:00000000 bit 23 22 21 20 19 18 17 bit 16 read: nie23 nie22 nie21 nie20 nie19 nie18 nie17 nie16 write: reset:00000000 bit 15 14 13 12 11 10 9 bit 8 read: nie15 nie14 nie13 nie12 nie11 nie10 nie9 nie8 write: reset:00000000 bit 7654321bit 0 read: nie7 nie6 nie5 nie4 nie3 nie2 nie1 nie0 write: reset:00000000 address register name bit number p = current pin state u = unaffected = writes have no effect and the access terminates without a transfer error exception. figure 2-4. register summary (sheet 14 of 37) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . system memory map register map mmc2114 MMC2113 mmc2112 ? rev. 1.0 advance information motorola system memory map 71 bit 31 30 29 28 27 26 25 bit 24 0x00c5_0014 0x00c5_0015 0x00c5_0016 0x00c5_0017 normal interrupt pending register (nipr) see page 188. read: nip31 nip30 nip29 nip28 nip27 nip26 nip25 nip24 write: reset:00000000 bit 23 22 21 20 19 18 17 bit 16 read: nip23 nip22 nip21 nip20 nip19 nip18 nip17 nip16 write: reset:00000000 bit 15 14 13 12 11 10 9 bit 8 read: nip15 nip14 nip13 nip12 nip11 nip10 nip9 nip8 write: reset:00000000 bit 7654321bit 0 read:nip7nip6nip5nip4nip3nip2nip1nip0 write: reset:00000000 bit 31 30 29 28 27 26 25 bit 24 0x00c5_0018 0x00c5_0019 0x00c5_001a 0x00c5_001b fast interrupt enable register (fier) see page 189. read: fie31 fie30 fie29 fie28 fie27 fie26 fie25 fie24 write: reset:00000000 bit 23 22 21 20 19 18 17 bit 16 read: fie23 fie22 fie21 fie20 fie19 fie18 fie17 fie16 write: reset:00000000 bit 15 14 13 12 11 10 9 bit 8 read: fie15 fie14 fie13 fie12 fie11 fie10 fie9 fie8 write: reset:00000000 bit 7654321bit 0 read: fie7 fie6 fie5 fie4 fie3 fie2 fie1 fie0 write: reset:00000000 address register name bit number p = current pin state u = unaffected = writes have no effect and the access terminates without a transfer error exception. figure 2-4. register summary (sheet 15 of 37) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . advance information mmc2114 MMC2113 mmc2112 ? rev. 1.0 72 system memory map motorola system memory map bit 31 30 29 28 27 26 25 bit 24 0x00c5_001c 0x00c5_001d 0x00c5_001e 0x00c5_001f fast interrupt pending register (fipr) see page 190. read: fip31 fip30 fip29 fip28 fip27 fip26 fip25 fip24 write: reset:00000000 bit 23 22 21 20 19 18 17 bit 16 read: fip23 fip22 fip21 fip20 fip19 fip18 fip17 fip16 write: reset:00000000 bit 15 14 13 12 11 10 9 bit 8 read: fip15 fip14 fip13 fip12 fip11 fip10 fip9 fip8 write: reset:00000000 bit 7654321bit 0 read: fip7 fip6 fip5 fip4 fip3 fip2 fip1 fip0 write: reset:00000000 bit 7654321bit 0 0x00c5_0040 0x00c5_0067 priority level select registers (plsr39?plsr0) see page 191. read: 0 0 0 pls4 pls3 pls2 pls1 pls0 write: reset:00000000 bit 7654321bit 0 0x00c5_0068 0x00c5_007f unimplemented access results in the module generating an access termination transfer error. bit 7654321bit 0 0x00c5_0080 0x00c5_ffff unimplemented access results in a bus monitor timeout generating an access termination transfer error. address register name bit number p = current pin state u = unaffected = writes have no effect and the access terminates without a transfer error exception. figure 2-4. register summary (sheet 16 of 37) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . system memory map register map mmc2114 MMC2113 mmc2112 ? rev. 1.0 advance information motorola system memory map 73 edge port (eport) bit 15 14 13 12 11 10 9 bit 8 0x00c6_0000 0x00c6_0001 eport pin assignment register (eppar) see page 288. read: eppa7 eppa6 eppa5 eppa4 write: reset:00000000 bit 7654321bit 0 read: eppa3 eppa2 eppa1 eppa0 write: reset:00000000 bit 7654321bit 0 0x00c6_0002 eport data direction register (epddr) see page 290. read: epdd7 epdd6 epdd5 epdd4 epdd3 epdd2 epdd1 epdd0 write: reset:00000000 bit 7654321bit 0 0x00c6_0003 eport port interrupt enable register (epier) see page 291. read: epie7 epie6 epie5 epie4 epie3 epie2 epie1 epie0 write: reset:00000000 bit 7654321bit 0 0x00c6_0004 eport port data register (epdr) see page 292. read: epd7 epd6 epd5 epd4 epd3 epd2 epd1 epd0 write: reset:11111111 bit 7654321bit 0 0x00c6_0005 eport port pin data register (eppdr) see page 292. read: eppd7 eppd6 eppd5 eppd4 eppd3 eppd2 eppd1 eppd0 write: reset:pppppppp bit 7654321bit 0 0x00c6_0006 eport port flag regiser (epfr) see page 293. read: epf7 epf6 epf5 epf4 epf3 epf2 epf1 epf0 write: reset:00000000 bit 7654321bit 0 0x00c6_0007 reserved writes have no effect, reads return 0s, and the access terminates without a transfer error exception. address register name bit number p = current pin state u = unaffected = writes have no effect and the access terminates without a transfer error exception. figure 2-4. register summary (sheet 17 of 37) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . advance information mmc2114 MMC2113 mmc2112 ? rev. 1.0 74 system memory map motorola system memory map bit 7654321bit 0 0x00c6_0008 0x00c6_ffff unimplemented access results in a bus monitor timeout generating an access termination transfer error. watchdog timer (wdt) bit 15 14 13 12 11 10 9 bit 8 0x00c7_0000 0x00c7_0001 watchdog control register (wcr) see page 299. read:00000000 write: reset:00000000 bit 7654321bit 0 read:0000 wait doze dbg en write: reset:00001111 bit 15 14 13 12 11 10 9 bit 8 0x00c7_0002 0x00c7_0003 watchdog modulus register (wmr) see page 301. read: wm15 wm14 wm13 wm12 wm11 wm10 wm9 wm8 write: reset:11111111 bit 7654321bit 0 read: wm7 wm6 wm5 wm4 wm3 wm2 wm1 wm0 write: reset:11111111 bit 15 14 13 12 11 10 9 bit 8 0x00c7_0004 0x00c7_0005 watchdog count register (wcntr) see page 302. read: wc15 wc14 wc13 wc12 wc11 wc10 wc9 wc8 write: reset:11111111 bit 7654321bit 0 read: wc7 wc6 wc5 wc4 wc3 wc2 wc1 wc0 write: reset:11111111 address register name bit number p = current pin state u = unaffected = writes have no effect and the access terminates without a transfer error exception. figure 2-4. register summary (sheet 18 of 37) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . system memory map register map mmc2114 MMC2113 mmc2112 ? rev. 1.0 advance information motorola system memory map 75 bit 15 14 13 12 11 10 9 bit 8 0x00c7_0006 0x00c7_0007 watchdog service register (wsr) see page 303. read: ws15 ws14 ws13 ws12 ws11 ws10 ws9 ws8 write: reset:00000000 bit 7654321bit 0 read: ws7 ws6 ws5 ws4 ws3 ws2 ws1 ws0 write: reset:00000000 bit 7654321bit 0 0x00c7_0008 0x00c7_ffff unimplemented access results in a bus monitor timeout generating an access termination transfer error. programmable interrupt timer 1 (pit1) and programming interrupt timer 2 (pit2) note: addresses for pit1 are at 0x00c8_#### and addresses for pit2 are at 0x00c9_####. bit 15 14 13 12 11 10 9 bit 8 0x00c8_0000 0x00c8_0001 0x00c9_0000 0x00c9_0001 pit control and status register (pcsr) see page 309. read:0000 pre3 pre2 pre1 pre0 write: reset:00000000 bit 7654321bit 0 read: 0 pdoze pdbg ovw pie pif rld en write: reset:00000000 bit 15 14 13 12 11 10 9 bit 8 0x00c8_0002 0x00c8_0003 0x00c9_0002 0x00c9_0003 pit modulus register (pmr) see page 312. read: pm15 pm14 pm13 pm12 pm11 pm10 pm9 pm8 write: reset:11111111 bit 7654321bit 0 read: pm7 pm6 pm5 pm4 pm3 pm2 pm1 pm0 write: reset:11111111 address register name bit number p = current pin state u = unaffected = writes have no effect and the access terminates without a transfer error exception. figure 2-4. register summary (sheet 19 of 37) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . advance information mmc2114 MMC2113 mmc2112 ? rev. 1.0 76 system memory map motorola system memory map bit 15 14 13 12 11 10 9 bit 8 0x00c8_0004 0x00c8_0005 0x00c9_0004 0x00c9_0005 pit count register (pcntr) see page 313. read: pc15 pc14 pc13 pc12 pc11 pc10 pc9 pc8 write: reset:11111111 bit 7654321bit 0 read: pc7 pc6 pc5 pc4 pc3 pc2 pc1 pc0 write: reset:11111111 bit 7654321bit 0 0x00c8_0006 0x00c8_0007 unimplemented access results in the module generating an access termination transfer error. bit 7654321bit 0 0x00ca_0008 0x00ca_ffff unimplemented access results in a bus monitor timeout generating an access termination transfer error. queued analog-to-digital converter (qadc) bit 15 14 13 12 11 10 9 bit 8 0x00ca_0000 0x00ca_0001 qadc module configuration register (qadcmcr) see page 437. read: qstop qdbg 000000 write: reset:00000000 bit 7654321bit 0 read: supv 0000000 write: reset:10000000 bit 15 14 13 12 11 10 9 bit 8 0x00ca_0002 0x00ca_0003 qadc test register (qadctest) see page 438. access results in the module generating an access termination transfer error if not in test mode. bit 7654321bit 0 access results in the module generating an access termination transfer error if not in test mode. address register name bit number p = current pin state u = unaffected = writes have no effect and the access terminates without a transfer error exception. figure 2-4. register summary (sheet 20 of 37) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . system memory map register map mmc2114 MMC2113 mmc2112 ? rev. 1.0 advance information motorola system memory map 77 0x00ca_0004 0x00ca_0005 reserved writes have no effect, reads return 0s, and the access terminates without a transfer error exception. bit 7654321bit 0 writes have no effect, reads return 0s, and the access terminates without a transfer error exception. bit 7654321bit 0 0x00ca_0006 qadc port a data register (portqa) see page 439. read: 0 0 0 pqa4 pqa3 0 pqa1 pqa0 write: reset:000pp0pp bit 7654321bit 0 0x00ca_0007 qadc port b data register (portqb) see page 439. read:0000 pqb3 pqb2 pqb1 pqb0 write: reset:0000pppp bit 7654321bit 0 0x00ca_0008 qadc port a data direction register (ddrqa) see page 441. read: 0 0 0 ddqa4 ddqa3 0 ddqa1 ddqa0 write: reset:00000000 qadc port b data direction register (ddrqb) see page 441. bit 7654321bit 0 0x00ca_0009 read: 0000 ddqb3 ddqb2 ddqb1 ddqb0 write: reset:00000000 bit 15 14 13 12 11 10 9 bit 8 0x00ca_000a 0x00ca_000b qadc control register 0 (qacr0) see page 442. read: mux 00 trg 0000 write: reset:00000000 bit 7654321bit 0 read: 0 qpr6 qpr5 qpr4 qpr3 qpr2 qpr1 qpr0 write: reset:00010011 address register name bit number p = current pin state u = unaffected = writes have no effect and the access terminates without a transfer error exception. figure 2-4. register summary (sheet 21 of 37) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . advance information mmc2114 MMC2113 mmc2112 ? rev. 1.0 78 system memory map motorola system memory map bit 15 14 13 12 11 10 9 bit 8 0x00ca_000c 0x00ca_000d qadc control register 1 (qacr1) see page 445. read: cie1 pie1 0 mq112 mq111 mq110 mq19 mq18 write: sse1 reset:00000000 bit 7654321bit 0 read:00000000 write: reset:00000000 bit 15 14 13 12 11 10 9 bit 8 0x00ca_000e 0x00ca_000f qadc control register 2 (qacr2) see page 448. read: cie2 pie2 0 mq212 mq211 mq210 mq29 mq28 write: sse2 reset:00000000 bit 7654321bit 0 read: resume bq26 bq25 bq24 bq23 bq22 bq21 bq20 write: reset:01111111 bit 15 14 13 12 11 10 9 bit 8 0x00ca_0010 0x00ca_0011 qadc status register 0 (qasr0) see page 453. read: cf1 pf1 cf2 pf2 tor1 tor2 qs9 qs8 write: reset:00000000 bit 7654321bit 0 read: qs7 qs6 cwp5 cwp4 cwp3 cwp2 cwp1 cwp0 write: reset:00000000 address register name bit number p = current pin state u = unaffected = writes have no effect and the access terminates without a transfer error exception. figure 2-4. register summary (sheet 22 of 37) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . system memory map register map mmc2114 MMC2113 mmc2112 ? rev. 1.0 advance information motorola system memory map 79 bit 15 14 13 12 11 10 9 bit 8 0x00ca_0012 0x00ca_0013 qadc status register 1 (qasr1) see page 462. read: 0 0 cwpq15 cwpq14 cwpq13 cwpq12 cwpq11 cwpq10 write: reset:00111111 bit 7654321bit 0 read: 0 0 cwpq25 cwpq24 cwpq23 cwpq22 cwpq21 cwpq20 write: reset:00111111 bit 7654321bit 0 0x00ca_0014 0x00ca_01ff reserved writes have no effect, reads return 0s, and the access terminates without a transfer error exception. bit 15 14 13 12 11 10 9 bit 8 0x00ca_0200 0x00ca_027e conversion command word register (ccw0 ? ccw63) see page 464. read:000000 pbyp write: reset:000000uu bit 7654321bit 0 read: ist1 ist0 chan5 chan4 chan3 chan2 chan1 chan0 write: reset:uuuuuuuu bit 15 14 13 12 11 10 9 bit 8 0x00ca_0280 0x00ca_02fe right-justified unsigned result register (rjurr0 ? rjurr63) see page 468. read:000000 result write: reset:000000 bit 7654321bit 0 read: result write: reset: address register name bit number p = current pin state u = unaffected = writes have no effect and the access terminates without a transfer error exception. figure 2-4. register summary (sheet 23 of 37) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . advance information mmc2114 MMC2113 mmc2112 ? rev. 1.0 80 system memory map motorola system memory map bit 15 14 13 12 11 10 9 bit 8 0x00ca_0300 0x00ca_037e left-justified signed result register (ljsrr0 ? ljsrr63) see page 469. read: sresult write: reset: bit 7654321bit 0 read: result 000000 write: reset: 000000 bit 15 14 13 12 11 10 9 bit 8 0x00ca_0380 0x00ca_03fe left-justified unsigned result register (ljurr0 ? ljurr63) see page 470. read: result write: reset: bit 7654321bit 0 read: result 000000 write: reset: 000000 bit 7654321bit 0 0x00ca_0400 0x00ca_ffff unimplemented access results in a bus monitor timeout generating an access termination transfer error. serial peripheral interface (spi) bit 7654321bit 0 0x00cb_0000 spi control register 1 (spicr1) see page 402. read: spie spe swom mstr cpol cpha ssoe lsbfe write: reset:00000100 bit 7654321bit 0 0x00cb_0001 spi control register 2 (spicr2) see page 405. read:000000 spisdoz spc0 write: reset:00000000 address register name bit number p = current pin state u = unaffected = writes have no effect and the access terminates without a transfer error exception. figure 2-4. register summary (sheet 24 of 37) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . system memory map register map mmc2114 MMC2113 mmc2112 ? rev. 1.0 advance information motorola system memory map 81 bit 7654321bit 0 0x00cb_0002 spi baud rate register (spibr) see page 406. read: 0 sppr6 sppr5 sppr4 0 spr2 spr1 spr0 write: reset:00000000 bit 7654321bit 0 0x00cb_0003 spi status register (spisr) see page 408. read: spif wcol 0 modf 0 0 0 0 write: reset:00000000 bit 7654321bit 0 0x00cb_0004 reserved writes have no effect, reads return 0s, and the access terminates without a transfer error exception. bit 7654321bit 0 0x00cb_0005 spi data register (spidr) see page 409. read: bit 7654321bit 0 write: reset:00000000 bit 7654321bit 0 0x00cb_0006 spi pullup and reduced drive register (spipurd) see page 410. read: 0 0 rsvd5 rdpsp 00 rsvd1 pupsp write: reset:00000000 bit 7654321bit 0 0x00cb_0007 spi port data register (spiport) see page 411. read: rsvd7 rsvd6 rsvd5 rsvd4 portsp3 portsp2 portsp1 portsp0 write: reset:00000000 bit 7654321bit 0 0x00cb_0008 spi port data direction register (spiddr) see page 412. read: rsvd7 rsvd6 rsvd5 rsvd4 ddrsp3 ddrsp2 ddrsp1 ddrsp0 write: reset:00000000 bit 7654321bit 0 0x00cb_0009 0x00cb_000f reserved writes have no effect, reads return 0s, and the access terminates without a transfer error exception. address register name bit number p = current pin state u = unaffected = writes have no effect and the access terminates without a transfer error exception. figure 2-4. register summary (sheet 25 of 37) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . advance information mmc2114 MMC2113 mmc2112 ? rev. 1.0 82 system memory map motorola system memory map bit 7654321bit 0 0x00cb_0010 0x00cb_ffff unimplemented access results in a bus monitor timeout generating an access termination transfer error. serial communications interface 1 (sci1) and serial communications interface 2 (sci2) note: addresses for sci1 are at 0x00cc_#### and addresses for sci2 are at 0x00cd_####. bit 7654321bit 0 0x00cc_0000 0x00cd_0000 sci baud rate register high (scibdh) see page 360. read: 0 0 0 sbr12 sbr11 sbr10 sbr9 sbr8 write: reset:00000000 bit 7654321bit 0 0x00cc_0001 0x00cd_0001 sci baud rate register low (scibdl) see page 360. read: sbr7 sbr6 sbr5 sbr4 sbr3 sbr2 sbr1 sbr0 write: reset:00000100 bit 7654321bit 0 0x00cc_0002 0x00cd_0002 sci control register 1 (scicr1) see page 361. read: loops woms rsrc m wake ilt pe pt write: reset:00000000 bit 7654321bit 0 0x00cc_0003 0x00cd_0003 sci control register 2 (scicr2) see page 364. read: tie tcie rie ilie te re rwu sbk write: reset:00000000 bit 7654321bit 0 0x00cc_0004 0x00cd_0004 sci status register 1 (scisr1) see page 366. read: tdre tc rdrf idle or nf fe pf write: reset:11000000 bit 7654321bit 0 0x00cc_0005 0x00cd_0005 sci status register 2 (scisr2) see page 369. read:0000000raf write: reset:00000000 address register name bit number p = current pin state u = unaffected = writes have no effect and the access terminates without a transfer error exception. figure 2-4. register summary (sheet 26 of 37) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . system memory map register map mmc2114 MMC2113 mmc2112 ? rev. 1.0 advance information motorola system memory map 83 bit 7654321bit 0 0x00cc_0006 0x00cd_0006 sci data register high (scidrh) see page 370. read: r8 t8 000000 write: reset:00000000 bit 7654321bit 0 0x00cc_0007 0x00cd_0007 sci data register low (scidrl) see page 370. read:r7r6r5r4r3r2r1r0 write: t7 t6 t5 t4 t3 t2 t1 t0 reset:00000000 bit 7654321bit 0 0x00cc_0008 0x00cd_0008 sci pullup and reduced drive register (scipurd) see page 371. read: scisdoz 0 rsvd5 rdpsci 00 rsvd1 pupsci write: reset:00000000 bit 7654321bit 0 0x00cc_0009 0x00cd_0009 sci port data register (sciport) see page 372. read: rsvd7 rsvd6 rsvd5 rsvd4 rsvd3 rsvd2 portsc1 portsc0 write: reset:00000000 bit 7654321bit 0 0x00cc_000a 0x00cd_000a sci data direction register (sciddr) see page 373. read: rsvd7 rsvd6 rsvd5 rsvd4 rsvd3 rsvd2 ddrsc1 ddrsc0 write: reset:00000000 bit 7654321bit 0 0x00cc_000b 0x00cc_000f 0x00cd_000b 0x00cd_000f reserved writes have no effect, reads return 0s, and the access terminates without a transfer error exception. bit 7654321bit 0 0x00cc_0010 0x00cc_ffff 0x00cd_0010 0x00cd_ffff unimplemented access results in a bus monitor timeout generating an access termination transfer error. address register name bit number p = current pin state u = unaffected = writes have no effect and the access terminates without a transfer error exception. figure 2-4. register summary (sheet 27 of 37) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . advance information mmc2114 MMC2113 mmc2112 ? rev. 1.0 84 system memory map motorola system memory map timer 1 (tim1) and timer 2 (tim2) note: addresses for tim1 are at 0x00ce_#### and addresses for tim2 are at 0x00cf_####. bit 7654321bit 0 0x00ce_0000 0x00cf_0000 timer input capture/ output compare select register (timios) see page 324. read:0000 ios3 ios2 ios1 ios0 write: reset:00000000 bit 7654321bit 0 0x00ce_0001 0x00cf_0001 timer compare force register (timcforc) see page 325. read:00000000 write: foc3 foc2 foc1 foc0 reset:00000000 bit 7654321bit 0 0x00ce_0002 0x00cf_0002 timer output compare 3 mask register (timoc3m) see page 326. read:0000 oc3m3 oc3m2 oc3m1 oc3m0 write: reset:00000000 bit 7654321bit 0 0x00ce_0003 0x00cf_0003 timer output compare 3 data register (timoc3d) see page 327. read:0000 oc3d3 oc3d2 oc3d1 oc3d0 write: reset:00000000 bit 7654321bit 0 0x00ce_0004 0x00cf_0004 timer counter register high (timcnth) see page 328. read: bit 15 14 13 12 11 10 9 bit 8 write: reset:00000000 bit 7654321bit 0 0x00ce_0005 0x00cf_0005 timer counter register low (timcntl) see page 328. read:bit 7654321bit 0 write: reset:00000000 bit 7654321bit 0 0x00ce_0006 0x00cf_0006 timer system control register 1 (timscr1) see page 329. read: timen 00 tffca 0000 write: reset:00000000 address register name bit number p = current pin state u = unaffected = writes have no effect and the access terminates without a transfer error exception. figure 2-4. register summary (sheet 28 of 37) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . system memory map register map mmc2114 MMC2113 mmc2112 ? rev. 1.0 advance information motorola system memory map 85 bit 7654321bit 0 0x00ce_0007 0x00cf_0007 reserved writes have no effect, reads return 0s, and the access terminates without a transfer error exception. bit 7654321bit 0 0x00ce_0008 0x00cf_0008 timer toggle on overflow register (timtov) see page 330. read:0000 tov3 tov2 tov1 tov0 write: reset:00000000 bit 7654321bit 0 0x00ce_0009 0x00cf_0009 timer control register 1 (timctl1) see page 331. read: om3 ol3 om2 ol2 om1 ol1 om0 ol0 write: reset:00000000 bit 7654321bit 0 0x00ce_000a 0x00cf_000a reserved writes have no effect, reads return 0s, and the access terminates without a transfer error exception. bit 7654321bit 0 0x00ce_000b 0x00cf_000b timer control register 2 (timctl2) see page 332. read: edg3b edg3a edg2b edg2a edg1b edg1a edg0b edg10 write: reset:00000000 bit 7654321bit 0 0x00ce_000c 0x00cf_000c timer interrupt enable register (timie) see page 333. read:0000 c3i c2i c1i c0i write: reset:00000000 bit 7654321bit 0 0x00ce_000d 0x00cf_000d timer system control register 2 (timscr2) see page 334. read: toi 0 pupt rdpt tcre pr2 pr1 pr0 write: reset:00000000 bit 7654321bit 0 0x00ce_000e 0x00cf_000e timer flag register 1 (timflg1) see page 336. read:0000 c3f c2f c1f c0f write: reset:00000000 address register name bit number p = current pin state u = unaffected = writes have no effect and the access terminates without a transfer error exception. figure 2-4. register summary (sheet 29 of 37) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . advance information mmc2114 MMC2113 mmc2112 ? rev. 1.0 86 system memory map motorola system memory map bit 7654321bit 0 0x00ce_000f 0x00cf_000f timer flag register 2 (timflg2) see page 337. read: tof 0000000 write: reset:00000000 bit 15 14 13 12 11 10 9 bit 8 0x00ce_0010 0x00cf_0010 timer channel 0 register high (timc0h) see page 338. read: bit 15 14 13 12 11 10 9 bit 8 write: reset:00000000 bit 7654321bit 0 0x00ce_0011 0x00cf_0011 timer channel 0 register low (timc0l) see page 338. read: bit 7654321bit 0 write: reset:00000000 bit 15 14 13 12 11 10 9 bit 8 0x00ce_0012 0x00cf_0012 timer channel 1 register high (timc1h) see page 338. read: bit 15 14 13 12 11 10 9 bit 8 write: reset:00000000 bit 7654321bit 0 0x00ce_0013 0x00cf_0013 timer channel 1 register low (timc1l) see page 338. read: bit 7654321bit 0 write: reset:00000000 bit 15 14 13 12 11 10 9 bit 8 0x00ce_0014 0x00cf_0014 timer channel 2 register high (timc2h) see page 338. read: bit 15 14 13 12 11 10 9 bit 8 write: reset:00000000 bit 7654321bit 0 0x00ce_0015 0x00cf_0015 timer channel 2 register low (timc2l) see page 338. read: bit 7654321bit 0 write: reset:00000000 bit 15 14 13 12 11 10 9 bit 8 0x00ce_0016 0x00cf_0016 timer channel 3 register high (timc3h) see page 338. read: bit 15 14 13 12 11 10 9 bit 8 write: reset:00000000 address register name bit number p = current pin state u = unaffected = writes have no effect and the access terminates without a transfer error exception. figure 2-4. register summary (sheet 30 of 37) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . system memory map register map mmc2114 MMC2113 mmc2112 ? rev. 1.0 advance information motorola system memory map 87 bit 7654321bit 0 0x00ce_0017 0x00cf_0017 timer channel 3 register low (timc3l) see page 338. read: bit 7654321bit 0 write: reset:00000000 bit 7654321bit 0 0x00ce_0018 0x00cf_0018 pulse accumulator control register (timpactl) see page 339. read: 0 pae pamod pedge clk1 clk0 paovi pai write: reset:00000000 bit 7654321bit 0 0x00ce_0019 0x00cf_0019 pulse accumulator flag register (timpaflg) see page 341. read:000000 paovf paif write: reset:00000000 bit 15 14 13 12 11 10 9 bit 8 0x00ce_001a 0x00cf_001a pulse accumulator counter register high (timpacnth) see page 342. read: bit 15 14 13 12 11 10 9 bit 8 write: reset:00000000 bit 7654321bit 0 0x00ce_001b 0x00cf_001b pulse accumulator counter register low (timpacntl) see page 342. read: bit 7654321bit 0 write: reset:00000000 bit 7654321bit 0 0x00ce_001c 0x00cf_001c reserved writes have no effect, reads return 0s, and the access terminates without a transfer error exception. bit 7654321bit 0 0x00ce_001d 0x00cf_001d timer port data register (timport) see page 343. read:0000 portt3 portt2 portt1 portt0 write: reset:00000000 bit 7654321bit 0 0x00ce_001e 0x00cf_001e timer port data direction register (timddr) see page 344. read:0000 ddrt3 ddrt2 ddrt1 ddrt0 write: reset:00000000 address register name bit number p = current pin state u = unaffected = writes have no effect and the access terminates without a transfer error exception. figure 2-4. register summary (sheet 31 of 37) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . advance information mmc2114 MMC2113 mmc2112 ? rev. 1.0 88 system memory map motorola system memory map bit 7654321bit 0 0x00ce_001f 0x00cf_001f timer test register (timtst) see page 345. read:00000000 write: reset:00000000 bit 7654321bit 0 0x00ce_0020 0x00ce_ffff 0x00cf_0030 0x00cf_ffff unimplemented access results in the module generating an access termination transfer error. second generation flash for m?core (sgfm) bit 15 14 13 12 11 10 9 bit 8 0x00d0_0000 0x00d0_0001 sgfm module configuration register (sgfmmcr) see page 213. read: 0 frz 0 eme 0 lock 00 write: reset:000note 10000 bit 7654321bit 0 read: cbeie ccie keyacc 000 bksel write: reset:00000000 note: 1. reset state determined by chip reset configuration. bit 7654321bit 0 0x00d0_0002 sgfm clock divider register (sgfmclkd) see page 215. read: divld prdivdiv5div4div3div2div1div0 write: reset:00000000 bit 7654321bit 0 0x00d0_0003 unimplemented access results in the module generating an access termination transfer error. address register name bit number p = current pin state u = unaffected = writes have no effect and the access terminates without a transfer error exception. figure 2-4. register summary (sheet 32 of 37) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . system memory map register map mmc2114 MMC2113 mmc2112 ? rev. 1.0 advance information motorola system memory map 89 bit 7654321bit 0 0x00d0_0004 sgfm test register (sgfmtst) see page 216. read: rsvd7 rsvd6 rsvd5 rsvd4 00 rsvd1 rsvd0 write: reset:00000000 bit 7654321bit 0 0x00d0_0005 0x00d0_0007 unimplemented access results in the module generating an access termination transfer error. bit 31 30 29 28 27 26 25 bit 24 0x00d0_0008 0x00d0_0009 0x00d0_000a 0x00d0_000b sgfm security register (sgfmsec) see page 217. read:keyensecstat000000 write: reset: f (1) note 2000000 bit 23 22 21 20 19 18 17 bit 16 read:00000000 write: reset:00000000 bit 15 14 13 12 11 10 9 bit 8 read: sec15 sec14 sec13 sec12 sec11 sec10 sec9 sec8 write: reset: f (1) f (1) f (1) f (1) f (1) f (1) f (1) f (1) bit 7654321bit 0 read:sec7sec6sec5sec4sec3sec2sec1sec0 write: reset: f (1) f (1) f (1) f (1) f (1) f (1) f (1) f (1) notes: 1. reset state loaded from flash array during reset. 2. reset state determined by security state of module. address register name bit number p = current pin state u = unaffected = writes have no effect and the access terminates without a transfer error exception. figure 2-4. register summary (sheet 33 of 37) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . advance information mmc2114 MMC2113 mmc2112 ? rev. 1.0 90 system memory map motorola system memory map bit 31 30 29 28 27 26 25 bit 24 0x00d0_000c 0x00d0_000d 0x00d0_000e 0x00d0_000f sgfm monitor data register (sgfmmntr) see page 219. read: rsvd31 rsvd30 rsvd29 rsvd28 rsvd27 rsvd26 rsvd25 rsvd24 write: reset: note 1 bit 23 22 21 20 19 18 17 bit 16 read: rsvd23 rsvd22 rsvd21 rsvd20 rsvd19 rsvd18 rsvd17 rsvd16 write: reset: note 1 bit 15 14 13 12 11 10 9 bit 8 read: rsvd15 rsvd14 rsvd13 rsvd12 rsvd11 rsvd10 rsvd9 rsvd8 write: reset: note 1 bit 7654321bit 0 read: rsvd7 rsvd6 rsvd5 rsvd4 rsvd3 rsvd2 rsvd1 rsvd0 write: reset: note 1 note 1. sgfmmntr does not have a default reset state. bit 15 14 13 12 11 10 9 bit 8 0x00d0_0010 0x00d0_0011 sgfm protection register (sgfmprot) see page 220. read: prot15 prot14 prot13 prot12 prot11 prot10 prot9 prot8 write: reset: f (1) f (1) f (1) f (1) f (1) f (1) f (1) f (1) bit 7654321bit 0 read: prot7 prot6 prot5 prot4 prot3 prot2 prot1 prot0 write: reset: f (1) f (1) f (1) f (1) f (1) f (1) f (1) f (1) note 1. reset state loaded from flash configuration field during reset. bit 7654321bit 0 0x00d0_0012 0x00d0_0013 unimplemented access results in the module generating an access termination transfer error. address register name bit number p = current pin state u = unaffected = writes have no effect and the access terminates without a transfer error exception. figure 2-4. register summary (sheet 34 of 37) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . system memory map register map mmc2114 MMC2113 mmc2112 ? rev. 1.0 advance information motorola system memory map 91 bit 15 14 13 12 11 10 9 bit 8 0x00d0_0014 0x00d0_0015 sgfm supervisor access register (sgfmasacc) see page 221. read: supv15 supv14 supv13 supv12 supv11 supv10 supv9 supv8 write: reset: f (1) f (1) f (1) f (1) f (1) f (1) f (1) f (1) bit 7654321bit 0 read: supv7 supv6 supv5 supv4 supv3 supv2 supv1 supv0 write: reset: f (1) f (1) f (1) f (1) f (1) f (1) f (1) f (1) note 1. reset state loaded from flash array during reset. bit 15 14 13 12 11 10 9 bit 8 0x00d0_0016 0x00d0_0017 sgfm data access register (sgfmdacc) see page 223. read: data15 data14 data13 data12 data11 data10 data9 data8 write: reset: f (1) f (1) f (1) f (1) f (1) f (1) f (1) f (1) bit 7654321bit 0 read: data7 data6 data5 data4 data3 data2 data1 data0 write: reset: f (1) f (1) f (1) f (1) f (1) f (1) f (1) f (1) note 1. reset state loaded from flash configuration field during reset. bit 7654321bit 0 0x00d0_0018 sgfm test status register (sgfmtstat) see page 224. read:0000 rsvd3 0 rsvd1 rsvd0 write: reset: 00000000 bit 7654321bit 0 0x00d0_0019 0x00d0_001b unimplemented access results in the module generating an access termination transfer error. bit 7654321bit 0 0x00d0_001c sgfm user status register (sgfmustat) see page 224. read: cbeif ccif pviol accerr 0 blank 00 write: reset: 11000000 address register name bit number p = current pin state u = unaffected = writes have no effect and the access terminates without a transfer error exception. figure 2-4. register summary (sheet 35 of 37) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . advance information mmc2114 MMC2113 mmc2112 ? rev. 1.0 92 system memory map motorola system memory map bit 7654321bit 0 0x00d0_001d 0x00d0_001f unimplemented access results in a bus monitor timeout generating an access termination transfer error. bit 7654321bit 0 0x00d0_0020 sgfm command buffer and register (sgfmcmd) see page 226. read: 0 cmd6 cmd5 cmd4 cmd3 cmd2 cmd1 cmd0 write: reset: 00000000 bit 7654321bit 0 0x00d0_0021 0x00d0_0023 unimplemented access results in a bus monitor timeout generating an access termination transfer error. bit 15 14 13 12 11 10 9 bit 8 0x00d0_0024 0x00d0_0025 sgfm control register (sgfmctl) see page 227. read: rsvd15 0000000 write: reset: 00000000 bit 7654321bit 0 read: rsvd7 rsvd6 rsvd5 rsvd4 rsvd3 rsvd2 rsvd1 rsvd0 write: reset: 00000000 bit 15 14 13 12 11 10 9 bit 8 0x00d0_0026 0x00d0_0027 sgfm address register (sgfmadr) see page 228. read: 0 rsvd14 rsvd13 rsvd12 rsvd11 rsvd10 rsvd9 rsvd8 write: reset: 00000000 bit 7654321bit 0 read: rsvd7 rsvd6 rsvd5 rsvd4 rsvd3 rsvd2 rsvd1 rsvd0 write: reset: 00000000 address register name bit number p = current pin state u = unaffected = writes have no effect and the access terminates without a transfer error exception. figure 2-4. register summary (sheet 36 of 37) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . system memory map register map mmc2114 MMC2113 mmc2112 ? rev. 1.0 advance information motorola system memory map 93 bit 31 30 29 28 27 26 25 bit 24 0x00d0_0028 0x00d0_0029 0x00d0_002a 0x00d0_002b sgfm data register (sgfmdata) see page 229. read: rsvd31 rsvd30 rsvd29 rsvd28 rsvd27 rsvd26 rsvd25 rsvd24 write: reset:00000000 bit 23 22 21 20 19 18 17 bit 16 read: rsvd23 rsvd22 rsvd21 rsvd20 rsvd19 rsvd18 rsvd17 rsvd16 write: reset:00000000 bit 15 14 13 12 11 10 9 bit 8 read: rsvd15 rsvd14 rsvd13 rsvd12 rsvd11 rsvd10 rsvd9 rsvd8 write: reset:00000000 bit 7654321bit 0 read: rsvd7 rsvd6 rsvd5 rsvd4 rsvd3 rsvd2 rsvd1 rsvd0 write: reset:00000000 address register name bit number p = current pin state u = unaffected = writes have no effect and the access terminates without a transfer error exception. figure 2-4. register summary (sheet 37 of 37) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . advance information mmc2114 MMC2113 mmc2112 ? rev. 1.0 94 system memory map motorola system memory map f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . mmc2114 MMC2113 mmc2112 ? rev. 1.0 advance information motorola signal description 95 advance information ? mmc2114, MMC2113, and mmc2112 section 3. signal description 3.1 contents 3.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .97 3.3 package pinout summary . . . . . . . . . . . . . . . . . . . . . . . . . . . .98 3.4 chip specific implementation signal issues. . . . . . . . . . . . . .109 3.4.1 rstout signal functions . . . . . . . . . . . . . . . . . . . . . . . . .109 3.4.2 int signal functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . .110 3.4.3 serial peripheral interface (spi) pin functions . . . . . . . . .110 3.4.4 serial communications interface (sci1 and sci2) pin functions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .111 3.4.5 timer 1 and timer 2 pin functions . . . . . . . . . . . . . . . . . .112 3.4.6 queued analog-to-digital converter (qadc) pin functions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .112 3.5 signal descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .113 3.5.1 reset signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .113 3.5.1.1 reset in (reset ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . .113 3.5.1.2 reset out (rstout ). . . . . . . . . . . . . . . . . . . . . . . . . . .113 3.5.2 phase-lock loop (pll) and clock signals . . . . . . . . . . . .113 3.5.2.1 external clock in (extal) . . . . . . . . . . . . . . . . . . . . . . .113 3.5.2.2 crystal (xtal) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .114 3.5.2.3 clock out (clkout) . . . . . . . . . . . . . . . . . . . . . . . . . . . 114 3.5.2.4 pll enable (pllen) . . . . . . . . . . . . . . . . . . . . . . . . . . .114 3.5.3 external memory interface signals . . . . . . . . . . . . . . . . . .114 3.5.3.1 data bus (d[31:0]) . . . . . . . . . . . . . . . . . . . . . . . . . . . . .114 3.5.3.2 show cycle strobe (shs ) . . . . . . . . . . . . . . . . . . . . . . .114 3.5.3.3 transfer acknowledge (ta ) . . . . . . . . . . . . . . . . . . . . . .115 3.5.3.4 transfer error acknowledge (tea ) . . . . . . . . . . . . . . . .115 3.5.3.5 emulation mode chip selects (cse[1:0]) . . . . . . . . . . .115 3.5.3.6 transfer code (tc[2:0]) . . . . . . . . . . . . . . . . . . . . . . . . .115 3.5.3.7 read/write (r/w ). . . . . . . . . . . . . . . . . . . . . . . . . . . . . .115 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . advance information mmc2114 MMC2113 mmc2112 ? rev. 1.0 96 signal description motorola signal description 3.5.3.8 address bus (a[22:0]) . . . . . . . . . . . . . . . . . . . . . . . . . .115 3.5.3.9 enable byte (eb[3:0] ) . . . . . . . . . . . . . . . . . . . . . . . . . .116 3.5.3.10 chip select (cs[3:0] ) . . . . . . . . . . . . . . . . . . . . . . . . . . .116 3.5.3.11 output enable (oe ) . . . . . . . . . . . . . . . . . . . . . . . . . . . .116 3.5.4 edge port signals. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .116 3.5.4.1 external interrupts (int[7:6] ) . . . . . . . . . . . . . . . . . . . . .116 3.5.4.2 external interrupts (int[5:2] ) . . . . . . . . . . . . . . . . . . . . .116 3.5.4.3 external interrupts (int[1:0] ) . . . . . . . . . . . . . . . . . . . . .116 3.5.5 serial peripheral interface module signals . . . . . . . . . . . .117 3.5.5.1 master out/slave in (mosi). . . . . . . . . . . . . . . . . . . . . .117 3.5.5.2 master in/slave out (miso). . . . . . . . . . . . . . . . . . . . . .117 3.5.5.3 serial clock (sck) . . . . . . . . . . . . . . . . . . . . . . . . . . . . .117 3.5.5.4 slave select (ss ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .117 3.5.6 serial communications interface module signals . . . . . . .117 3.5.6.1 receive data (rxd1 and rxd2) . . . . . . . . . . . . . . . . . .117 3.5.6.2 transmit data (txd1 and txd2). . . . . . . . . . . . . . . . . .118 3.5.7 timer signals (icoc1[3:0] and icoc2[3:0]) . . . . . . . . . . .118 3.5.8 analog-to-digital converter signals . . . . . . . . . . . . . . . . . .118 3.5.8.1 analog inputs (pqa[4:3], pqa[1:0], and pqb[3:0]) . . . .118 3.5.8.2 analog reference (v rh and v rl ) . . . . . . . . . . . . . . . . .118 3.5.8.3 analog supply (v dda and v ssa ) . . . . . . . . . . . . . . . . . .118 3.5.8.4 positive supply (v ddh ) . . . . . . . . . . . . . . . . . . . . . . . . .118 3.5.9 debug and emulation support signals . . . . . . . . . . . . . . .119 3.5.9.1 test reset (trst) . . . . . . . . . . . . . . . . . . . . . . . . . . . . .119 3.5.9.2 test clock (tclk) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119 3.5.9.3 test mode select (tms) . . . . . . . . . . . . . . . . . . . . . . . .119 3.5.9.4 test data input (tdi) . . . . . . . . . . . . . . . . . . . . . . . . . . .119 3.5.9.5 test data output (tdo). . . . . . . . . . . . . . . . . . . . . . . . .119 3.5.9.6 debug event (de ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . .119 3.5.10 test signal (test). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .120 3.5.11 power and ground signals . . . . . . . . . . . . . . . . . . . . . . . .120 3.5.11.1 standby power (v stby ) . . . . . . . . . . . . . . . . . . . . . . . . .120 3.5.11.2 positive supply (v dd ). . . . . . . . . . . . . . . . . . . . . . . . . . .120 3.5.11.3 ground (v ss ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .120 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . signal description introduction mmc2114 MMC2113 mmc2112 ? rev. 1.0 advance information motorola signal description 97 3.2 introduction the mmc2114, MMC2113, and mmc2112 are available in three packages: 100-pin joint-electron device engineering council (jedec) low- profile quad flat pack (lqfp) ? the 100-pin device is a minimum pin set for single-chip mode implementation. 144-pin jedec lqfp ? the 144-pin implementation includes 44 optional pins as a bond-out option to: ? accommodate an expanded set of features ? allow expansion of the number of general-purpose input/output (i/o) ? utilize off-chip memory ? provide enhanced support for development purposes 196-pin molded array process (map) ball grid array (bga) ? the 196-pin implementation includes: ? single-chip operation with extra general-purpose input/output ? expanded master mode for interfacing to external memories ? emulation mode for development and debug the optional group of pins includes: 23 address output lines four chip selects two emulation chip selects four byte/write enables read/write (r/w ) signal output enable signal three transfer code signals six power/ground pins note: the optional pins are either all present or none of them are present. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . advance information mmc2114 MMC2113 mmc2112 ? rev. 1.0 98 signal description motorola signal description 3.3 package pinout summary refer to: table 3-1 for a summary of the pinouts for the 144-pin and 100- pin lqfp packages. figure 3-1 , figure 3-2 , and figure 3-3 for a graphic view of the pinouts table 3-2 for a brief description of each signal table 3-1. package pinouts (sheet 1 of 5) pin number pin name 144-pin package 100-pin package 196-ball mapbga 1 1 b1 d30 / pa6 2 2 c2 d29 / pa5 3 3 c1 d28 / pa4 4 4 d3 d27 / pa3 5 5 d2 d26 / pa2 6 ? d1 a11 7 6 e3 d25 / pa1 8 ?? v ss 9 ?? v dd 10 7 e2 d24 / pa0 11 ? e1 a10 12 8 f3 d23 / pb7 13 ? f2 a9 14 ? f1 a8 15 9 g3 d22 / pb6 16 10 g2 d21 / pb5 17 11 g1 d20 / pb4 18 12 ? v ss 19 13 ? v dd 20 14 h3 d19 / pb3 21 15 h2 d18 / pb2 22 16 h1 d17 / pb1 23 ? j3 a7 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . signal description package pinout summary mmc2114 MMC2113 mmc2112 ? rev. 1.0 advance information motorola signal description 99 24 ? j2 a6 25 17 j1 d16 / pb0 26 ? k3 a5 27 18 k2 d15 / pc7 28 ? k1 a4 29 ? l3 a3 30 19 l2 d14 / pc6 31 20 l1 d13 / pc5 32 21 ? v ss 33 22 ? v dd 34 23 m2 d12 / pc4 35 24 m1 d11 / pc3 36 25 n1 d10 / pc2 37 26 p2 d9 / pc1 38 27 m3 d8 / pc0 39 28 n3 d7 / pd7 40 29 p3 d6 / pd6 41 30 m4 d5 / pd5 42 31 n4 d4 / pd4 43 32 p4 d3 / pd3 44 ?? v ss 45 ?? v dd 46 33 m5 d2 / pd2 47 ? n5 a2 48 34 p5 d1 / pd1 49 ? m6 a1 50 ? n6 a0 51 35 p6 d0 / pd0 52 36 m7 icoc23 53 37 n7 icoc22 54 38 p7 icoc21 55 39 m8 icoc20 56 40 n8 icoc13 table 3-1. package pinouts (sheet 2 of 5) pin number pin name 144-pin package 100-pin package 196-ball mapbga f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . advance information mmc2114 MMC2113 mmc2112 ? rev. 1.0 100 signal description motorola signal description 57 41 p8 icoc12 58 42 m9 icoc11 59 ? n9 r/w 60 ? p9 cse1 61 43 m10 icoc10 62 ? n10 cse0 63 44 p10 test 64 ?? v ss 65 ?? v dd 66 45 m11 txd2 67 ? n11 tc2 68 46 p11 rxd2 69 47 n12 txd1 70 48 p12 rxd1 71 49 n13 int0 72 50 p13 int1 73 51 p14 v ssf 74 52 m12 v ddf 75 53 n14 int2 76 54 ? v ss 77 55 ? v dd 78 ? m13 tc1 79 56 m14 int3 80 ? l12 tc0 81 ? l13 cs3 82 57 l14 int4 83 ? k12 cs2 84 58 k13 int5 85 ? k14 cs1 86 ? j12 cs0 87 59 j13 no connect 88 60 j14 int6 89 61 h12 int7 table 3-1. package pinouts (sheet 3 of 5) pin number pin name 144-pin package 100-pin package 196-ball mapbga f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . signal description package pinout summary mmc2114 MMC2113 mmc2112 ? rev. 1.0 advance information motorola signal description 101 90 62 h13 mosi 91 63 h14 miso 92 64 g12 v stby 93 65 g13 sck 94 66 g14 ss 95 ? f12 oe 96 ? f13 eb3 97 67 f14 shs / pe7 98 ? e12 eb2 99 68 e13 ta / pe6 100 ? e14 eb1 101 ? d12 eb0 102 69 d13 tea / pe5 103 70 e11 v ddh 104 71 d14 pqb3 105 72 c12 pqb2 106 73 c13 pqb1 107 74 c14 pqb0 108 75 b14 pqa4 109 76 a13 pqa3 110 77 b12 pqa1 111 78 a12 pqa0 112 79 c11 v rl 113 80 b11 v rh 114 81 e10 v ssa 115 82 e9 v dda 116 ? a11 a22 117 ? c10 a21 118 83 b10 reset 119 ? a10 a20 120 84 c9 rstout 121 ? b9 a19 122 ? a9 a18 table 3-1. package pinouts (sheet 4 of 5) pin number pin name 144-pin package 100-pin package 196-ball mapbga f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . advance information mmc2114 MMC2113 mmc2112 ? rev. 1.0 102 signal description motorola signal description 123 85 d8 pllen 124 86 a8 xtal 125 87 a7 extal 126 88 ? v ss 127 89 ? v ss 128 90 e8 clkout 129 91 ? v dd 130 92 b7 tclk 131 ? a6 a17 132 ? b6 a16 133 93 a5 tdi 134 ? c6 a15 135 94 b5 tdo 136 ? a4 a14 137 ? c5 a13 138 95 b4 tms 139 ? a3 a12 140 96 ? v ss 141 97 ? v dd 142 98 b3 trst 143 99 a2 de 144 100 c3 d31 / pa7 ?? a1, b2, c4, c7, c8, d4 ? d7, e4 ? e7, f4 ? f6, g4, g5, h4, h5, j4, k4, ? k11, l4 ? l11, n2, p1 v dd ?? a14, b8, b13, d9 ? d11, f7 ? f11, g6 ? g11, h6 ? h11, j5 ? j11 v ss table 3-1. package pinouts (sheet 5 of 5) pin number pin name 144-pin package 100-pin package 196-ball mapbga f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . mmc2114 MMC2113 mmc2112 ? rev. 1.0 advance information motorola signal description 103 signal description package pinout summary 1 2 3 4 5 6 7 8 9 10 11 12 13 14 a v dd de a12 a14 tdi a17 extal xtal a18 a20 a22 pqa0 pqa3 v ss a b d30 v dd trst tms tdo a16 tclk v ss a19 reset v rh pqa1 v ss pqa4 b c d28 d29 d31 v dd a13 a15 v dd v dd rstout a21 v rl pqb2 pqb1 pab0 c d a11 d26 d27 v dd v dd v dd v dd pllen v ss v ss v ss eb0 tea pqb3 d e a10 d24 d25 v dd v dd v dd v dd clkout v dda v ssa v ddh eb2 ta eb1 e f a8 a9 d23 v dd v dd v dd v ss v ss v ss v ss v ss oe eb3 shs f g d20 d21 d22 v dd v dd v ss v ss v ss v ss v ss v ss v stby sck ss g h d17 d18 d19 v dd v dd v ss v ss v ss v ss v ss v ss int7 mosi miso h j d16a6 a7v dd v ss v ss v ss v ss v ss v ss v ss cs0 n/c int6 j k a4 d15 a5 v dd v dd v dd v dd v dd v dd v dd v dd cs2 int5 cs1 k l d13 d14 a3 v dd v dd v dd v dd v dd v dd v dd v dd tc0 cs3 int4 l m d11 d12 d8 d5 d2 a1 icoc23 icoc20 icoc11 icoc10 txd2 v ddf tc1 int3 m n d10 v dd d7 d4 a2 a0 icoc22 icoc13 r/w cse0 tc2 txd1 int0 int2 n p v dd d9 d6 d3 d1 d0 icoc21 icoc12 cse1 test rxd2 rxd1 int1 v ss p 1 2 3 4 5 6 7 8 9 10 11 12 13 14 figure 3-1. 196-ball mapbga assignments f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . advance information mmc2114 MMC2113 mmc2112 ? rev. 1.0 104 signal description motorola signal description figure 3-2. 144-pin lqfp assignments 144 143 142 141 140 139 138 137 136 135 134 133 132 131 130 129 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 pqa4 pqb0 pqb1 pqb2 pqb3 v ddh tea eb0 eb1 ta eb2 shs eb3 oe ss sck v stby miso mosi int7 int6 no connect cs0 cs1 int5 cs2 int4 cs3 tc0 int3 tc1 v dd v ss int2 v ddf v ssf d30 d29 d28 d27 d26 a11 d25 v ss v dd d24 a10 d23 a9 a8 d22 d21 d20 v ss v dd d19 d18 d17 a7 a6 d16 a5 d15 a4 a3 d14 d13 v ss v dd d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 v ss v dd d2 a2 d1 a1 a0 d0 icoc23 icoc22 icoc21 icoc20 icoc13 icoc12 icoc11 r/w cse1 icoc10 cse0 test v ss v dd txd2 tc2 rxd2 txd1 rxd1 int0 int1 d31 de trst v dd v ss a12 tms a13 a14 tdo a15 tdi a16 a17 tclk v dd clkout v ss v ss extal xtal pllen a18 a19 rstout a20 reset a21 a22 v dda v ssa v rh v rl pqa0 pqa1 pqa3 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . signal description package pinout summary mmc2114 MMC2113 mmc2112 ? rev. 1.0 advance information motorola signal description 105 figure 3-3. 100-pin lqfp assignments 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 73 74 75 pa6 pa5 pa4 pa3 pa2 pa1 pa0 pb7 pb6 pb5 pb4 v ss v dd pb3 pb2 pb1 pb0 pc7 pc6 pc5 v ss v dd pc4 pc3 pc2 pc1 pc0 pd7 pd6 pd5 pd4 pd3 pd2 pd1 pd0 icoc23 icoc22 icoc21 icoc20 icoc13 icoc12 icoc11 icoc10 test txd2 rxd2 txd1 rxd1 int0 int1 pqa3 pqa1 pqa0 v rl v rh v ssa v dda reset rstout pllen xtal extal v ss v ss clkout v dd tclk tdi tdo tms v ss v dd trst de pa7 v ssf v ddf int2 v ss v dd i nt3 int4 int5 no connect i nt6 int7 mosi miso v stby sck ss pe7 pe6 pe5 v ddh pqb3 pqb2 pqb1 pqb0 pqa4 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . advance information mmc2114 MMC2113 mmc2112 ? rev. 1.0 106 signal description motorola signal description table 3-2. signal descriptions (sheet 1 of 3) name (1) alternate qty. dir. input hyst. input sync. (2) drive strength control (3) pullup (4) output driver (st/od/sp) (5) reset reset ? 1 i/o (6) yy ? pullup ? rstout showint 1 i/o (6) ? ? load ? st clock extal ? 1 i n n ? ? sp xtal ? 1 o ? ? ? ? sp clkout ? 1 i/o (6) ? ? load ? st pllen ? 1 i ? ? ? pullup ? external memory interface and ports d[31:0] pa[7:0], pb[7:0] pc[7:0], pd[7:0] 32 i/o y y load ? st shs rcon / pe7 1 i/o y y load pullup st ta pe6 1 i/o y y load pullup st tea pe5 1 i/o y y load pullup st cse[1:0] pe[4:3] 2 i/o y y load pullup st tc[2:0] pe[2:0] 3 i/o y y load pullup st r/w pf7 1 i/o y y load pullup st a[22:0] pf[6:0], pg[7:0] ph[7:0] 23 i/o y y load pullup st eb[3:0] pi[7:4] 4 i/o y y load pullup st cs[3:0] pi[3:0] 4 i/o y y load pullup st oe ? 1 i/o (6) ? ? load ? st edge port int[7:6] tsiz[1:0] / gpio 2 i/o y y load ? ? int[5:2] pstat[3:0] / gpio 4 i/o y y load ? ? int[1:0] gpio 2 i/o y y load ? ? f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . signal description package pinout summary mmc2114 MMC2113 mmc2112 ? rev. 1.0 advance information motorola signal description 107 serial peripheral interface (spi) mosi gpio 1 i/o y y rdpsp0 pullup (4) st / od (7) miso gpio 1 i/o y y rdpsp0 pullup (4) st / od (7) sck gpio 1 i/o y y rdpsp0 pullup (4) st / od (7) ss gpio 1 i/o y y rdpsp0 pullup (4) st / od (7) serial communication interface (sci1 and sci2) txd1 gpio 1 i/o y y rdpsci0 pullup (4) st / od (7) rxd1 gpio 1 i/o y y rdpsci0 pullup (4) st / od (7) txd2 gpio 1 i/o y y rdpsci0 pullup (4) st / od (7) rxd2 gpio 1 i/o y y rdpsci0 pullup (4) st / od (7) timer 1 and timer 2 icoc13 ic / oc / pai / gpio 1 i/o y y rdpt pullup (4) st icoc1[2:0] ic / oc / gpio 3 i/o y y rdpt pullup (4) st icoc23 ic / oc / pai / gpio 1 i/o y y rdpt pullup (4) st icoc2[2:0] ic / oc / gpio 3 i/o y y rdpt pullup (4) st queued analog-to-digital converter (qadc) pqa4 ? pqa3, pqa1 ? pqa0 gpio 4 i/o y y ? ? st pqb[3:0] gpi 4 i/o y y ? ? st v rh ? 1 i ? ? ? ? ? v rl ? 1 i ? ? ? ? ? v dda ? 1 i ? ? ? ? ? v ssa ? 1 i ? ? ? ? ? v ddh ? 1 i ? ? ? ? ? table 3-2. signal descriptions (sheet 2 of 3) name (1) alternate qty. dir. input hyst. input sync. (2) drive strength control (3) pullup (4) output driver (st/od/sp) (5) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . advance information mmc2114 MMC2113 mmc2112 ? rev. 1.0 108 signal description motorola signal description debug and jtag test port control trst ? 1 i y n ? pullup ? tclk ? 1 i y n ? pullup ? tms ? 1 i y n ? pullup ? tdi ? 1 i y n ? pullup ? tdo ? 1 o (8) ? ? load ? st de ? 1 i/o y n load pullup od test test ? 1 i y n ? ? ? power supplies v ddf ? 1 i ? ? ? ? ? v ssf ? 1 i ? ? ? ? ? v stby ? 1 i ? ? ? ? ? v dd ? 5 i ? ? ? ? ? v ss ? 6 i ? ? ? ? ? v dd ? 3 i ? ? ? ? ? v ss ? 3 i ? ? ? ? ? to ta l 100 total with optional pins 144 1. shaded signals are for optional bond-out for 144-pin package. 2. synchronized input used only if signal configured as a digital i/o. reset signal is always synchronized, except in low- power stop mode. 3. load (chip configuration register bit), rdpsp0 (purd register bit in spi), rdpsci0 (scipurd register bit in both scis), rdpt (timscr2 register bit in both timers) 4. all pullups are disconnected when the signal is programmed as an output. 5. output driver type: st = standard, od = standard driver with open-drain pulldown option selected, sp = special 6. digital input function for rstout , clkout, oe , and digital output function for reset used only for jtag boundary scan 7. open-drain and pullup function selectable via programmer ? s model in module configuration registers 8. three-state output with no input function table 3-2. signal descriptions (sheet 3 of 3) name (1) alternate qty. dir. input hyst. input sync. (2) drive strength control (3) pullup (4) output driver (st/od/sp) (5) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . signal description chip specific implementation signal issues mmc2114 MMC2113 mmc2112 ? rev. 1.0 advance information motorola signal description 109 3.4 chip specific implementation signal issues most modules are designed to allow expanded capabilities if all the module signals to the pads are implemented. this subsection discusses how these modules are implemented on the mmc2114, MMC2113, and mmc2112. 3.4.1 rstout signal functions the rstout signal has these multiple functions: whenever the internal system reset is asserted, the rstout signal will always be asserted to indicate the reset condition to the system. if the internal reset is not asserted, then setting the frcrstout bit in the reset control register (rcr) will assert the rstout signal for as long as the frcrstout bit is set. see 5.6.1 reset control register . if the internal reset is not asserted and the frcrstout bit is not set, then setting the showint bit in the chip configuration register will reflect internal interrupt requests out to the rstout signal. if the internal reset is not asserted and the frcrstout bit is not set and the showint bit is not set, then the rstout signal will be negated to indicate to the system that there is no reset condition. caution: external logic used to drive reset configuration data during reset needs to be considered when using the rstout signal for a function other than an indication of reset. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . advance information mmc2114 MMC2113 mmc2112 ? rev. 1.0 110 signal description motorola signal description 3.4.2 int signal functions the int signals have these multiple functions: if the szen bit in the chip configuration register is set, then int[7:6] will be used to reflect the state of the tsiz[1:0] signals from the cpu. see 4.7.3.1 chip configuration register . if the psten bit in the chip configuration register (ccr) is set, then int[5:2] will be used to reflect the state of the pstat[3:0] signals from the cpu. see 4.7.3.1 chip configuration register . note: if the szen or psten bits are set during emulation mode, then the corresponding edge port int functions are lost and will not be emulated externally. the default reset value for the pupsc1 bit in scipurd is 0. thus, the pullup function is disabled by default. 3.4.3 serial peripheral interface (spi) pin functions the spi module can support up to eight external pins, but only the four pins required for the spi interface are implemented. full spi interface capabilities and gpio functions using the miso, mosi, sck, and ss pins are supported. swom register bit controls whether output buffers behave as open-drain outputs. default is not open-drain outputs. pupsp0 register bit enables internal weak pad pullup devices. default is pullups disabled. rdpsp0 register bit controls reduced drive function of output buffers. default is full drive. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . signal description chip specific implementation signal issues mmc2114 MMC2113 mmc2112 ? rev. 1.0 advance information motorola signal description 111 gpio [7:4] of spi module not implemented. writes to bits [7:4] of the spiport and spiddr registers have no effect except to change the register bit values. reads of bits [7:4] of the spiport when the corresponding spiddr bits are set for inputs always return 0. pupsp and rdpsp register bits have no effect. the default reset values for the pupsp bit in spipurd is 0. thus, the pullup function is disabled by default. 3.4.4 serial communications interface (sci1 and sci2) pin functions full sci interface capabilities and gpio functions using the txd1/2 and rxd1/2 pins are supported. woms register bit controls whether output buffers behave as open-drain outputs. default is not open-drain outputs. pupsci register bit enables internal weak pad pullup devices. default is pullups disabled. rdpsci register bit controls reduced drive function of output buffers. default is full drive. gpio [7:2] of sci modules not implemented. writes to bits [7:2] of the sciport and sciddr registers have no effect except to change the register bit values. reads of bits [7:2] of the sciport when the corresponding sciddr bits are set for inputs always return 0. pupsci and rdpsci register bits have no effect. the default reset value for pupsci is 0. thus, the pullup function is disabled by default. note: only the pins associated with each sci are controlled by the register bits for the corresponding sci. thus, the woms register bit from sci1 only affects txd1 and rxd1 and has no effect on txd2 and rxd2. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . advance information mmc2114 MMC2113 mmc2112 ? rev. 1.0 112 signal description motorola signal description 3.4.5 timer 1 and timer 2 pin functions the timer modules can support up to four external pins each. note: only the pins associated with each timer are controlled by the register bits for the corresponding timer. full timer port pin functions are supported. pupt register bit enables internal weak pad pullup devices. default disables pullups. rdpt register bit controls reduced drive function of output buffers. default is full drive. the default reset value for pupt is 0. thus, the pullup function is disabled by default. the sync input is tied off and this function is not supported. 3.4.6 queued analog-to-digital converter (qadc) pin functions this implementation is a limited pin out version of the original qadc. limiting the number of pins lowers the over all pin count of the complete package. the lower pin count is achieved by utilizing 8 of 16 pins of the original full pin set. the available pins are, pqa4 ? pqa3, pqa1 ? pqa0, and pqb3 ? pqb0. all of the original functionality of the module is implemented with exception of limiting the total number of multiplexed channels. by using four external multiplexer chips, the maximum number of channels is 18. in nonmultiplexed mode, the maximum number of channels is eight. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . signal description signal descriptions mmc2114 MMC2113 mmc2112 ? rev. 1.0 advance information motorola signal description 113 3.5 signal descriptions this subsection provides a brief description of the signals. for more detailed information, reference the specific module section. 3.5.1 reset signals these signals are used to either reset the chip or as a reset indication. 3.5.1.1 reset in (reset ) this active-low input signal is used as the external reset request. reset places the cpu in supervisor mode with default settings for all register bits. 3.5.1.2 reset out (rstout ) this active-low output signal is an indication that the internal reset controller has reset the chip. when rstout is active, the user may drive override configuration options on the data bus. see table 4-7. configuration during reset . rstout is three-stated in phase-lock loop (pll) test mode. rstout may also be used to reflect an indication of an internal interrupt request. 3.5.2 phase-lock loop (pll) and clock signals these signals are used to support the on-chip clock generation circuitry. 3.5.2.1 external clock in (extal) this input signal is always driven by an external clock input except when used as a connection to an external crystal when the internal oscillator circuit is used. the clock source is configured during reset. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . advance information mmc2114 MMC2113 mmc2112 ? rev. 1.0 114 signal description motorola signal description 3.5.2.2 crystal (xtal) this output signal is used as a connection to drive an external crystal when the internal oscillator circuit is used. xtal should be grounded when using an external clock input on extal. 3.5.2.3 clock out (clkout) this output signal reflects the internal system clock. 3.5.2.4 pll enable (pllen) this is an active high signal only required during reset if chip configuration is performed. if this signal is pulled high during reset, then the pll will be used to clock the device. pulling this signal low during reset selects external clock mode. see table 4-7. configuration during reset . 3.5.3 external memory interface signals in addition to the functions stated here, these signals can also be configured for discrete i/o. 3.5.3.1 data bus (d[31:0]) these three-state bidirectional signals provide the general-purpose data path between the microcontroller unit (mcu) and all other devices. some of these pins are used during reset for chip configuration. 3.5.3.2 show cycle strobe (shs ) this output signal is used in emulation mode as a strobe for capturing addresses, controls, and data during show cycles. this signal is also used as rcon . note: the rcon signal, used only during reset, indicates whether the states on the external signals affect the chip configuration. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . signal description signal descriptions mmc2114 MMC2113 mmc2112 ? rev. 1.0 advance information motorola signal description 115 3.5.3.3 transfer acknowledge (ta ) this input signal indicates that the external data transfer is complete. during a read cycle, when the processor recognizes ta , it latches the data and then terminates the bus cycle. during a write cycle, when the processor recognizes ta , the bus cycle is terminated. this signal is an input in master and emulation modes. this function is not used in single- chip mode and its pin defaults to digital i/o. 3.5.3.4 transfer error acknowledge (tea ) this signal indicates an error condition exists for the bus transfer. the bus cycle is terminated and the central processor unit (cpu) begins execution of the access error exception. this signal is an input in master and emulation modes. this function is not used in single-chip mode and its pin defaults to digital i/o. 3.5.3.5 emulation mode chip selects (cse[1:0]) these output signals provide chip select support in emulation mode. 3.5.3.6 transfer code (tc[2:0]) these output signals indicate the data transfer code for the current bus cycle. these signals are enabled by default only in emulation mode. see table 12-2. pepar reset values . 3.5.3.7 read/write (r/w ) this output signal indicates the direction of the data transfer on the bus. a logic 1 indicates a read from a slave device and a logic 0 indicates a write to a slave device. 3.5.3.8 address bus (a[22:0]) these output signals provide the address for the current bus transfer. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . advance information mmc2114 MMC2113 mmc2112 ? rev. 1.0 116 signal description motorola signal description 3.5.3.9 enable byte (eb[3:0] ) these output signals indicate which byte of data is valid during external cycles. 3.5.3.10 chip select (cs[3 : 0] ) these output signals select external devices for external bus transactions. 3.5.3.11 output enable (oe ) this output signal indicates when an external device can drive data during external read cycles. 3.5.4 edge port signals these signals are used by the edge port module. 3.5.4.1 external interrupts (int[7:6] ) these bidirectional signals function as either external interrupt sources or gpio. also, these signals may be used to reflect the internal tsiz[1:0] signals and externally to provide an indication of the cpu transfer size. see 4.7.3.1 chip configuration register and section 20. external bus interface module (ebi) . 3.5.4.2 external interrupts (int[5:2] ) these bidirectional signals function as either external interrupt sources or gpio. also, these signals may be used to reflect the internal pstat[3:0] signals and externally to provide an indication of the cpu processor status.see 4.7.3.1 chip configuration register and section 20. external bus interface module (ebi) . 3.5.4.3 external interrupts (int[1:0] ) these bidirectional signals function as either external interrupt sources or gpio. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . signal description signal descriptions mmc2114 MMC2113 mmc2112 ? rev. 1.0 advance information motorola signal description 117 3.5.5 serial peripheral interface module signals these signals are used by the spi module and may also be configured to be discrete i/o signals. 3.5.5.1 master out/slave in (mosi) this signal is the serial data output from the spi in master mode and the serial data input in slave mode. 3.5.5.2 master in/slave out (miso) this signal is the serial data input to the spi in master mode and the serial data output in slave mode. 3.5.5.3 serial clock (sck) the serial clock synchronizes data transmissions between master and slave devices. sck is an output if the spi is configured as a master. sck is an input if the spi is configured as a slave. 3.5.5.4 slave select (ss ) this i/o signal is the peripheral chip select signal in master mode and is an active-low slave select in slave mode. 3.5.6 serial communications interface module signals these signals are used by the two sci modules. 3.5.6.1 receive data (rxd1 and rxd2) these signals are used for the sci receiver data input and are also available for gpio when not configured for receiver operation. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . advance information mmc2114 MMC2113 mmc2112 ? rev. 1.0 118 signal description motorola signal description 3.5.6.2 transmit data (txd1 and txd2) these signals are used for the sci transmitter data output and are also available for gpio when not configured for transmitter operation. 3.5.7 timer signals (icoc1[3:0] and icoc2[3:0]) these signals provide the external interface to the timer functions. they may be configured as general-purpose i/o if the timer output function is not needed. the default state at reset is general-purpose input. 3.5.8 analog-to-digital converter signals these signals are used by the analog-to-digital converter (qadc) module. 3.5.8.1 analog inputs (pqa[4:3], pqa[1:0], and pqb[3:0]) these signals provide the analog inputs to the qadc. the pqa and pqb signals may also be used as general-purpose digital i/o. 3.5.8.2 analog reference (v rh and v rl ) these signals serve as the high (v rh ) and low (v rl ) reference potentials for the analog converter. 3.5.8.3 analog supply (v dda and v ssa ) these dedicated power supply signals isolate the sensitive analog circuitry from the normal levels of noise present on the digital power supply. 3.5.8.4 positive supply (v ddh ) this signal supplies positive power to the esd structures in the qadc pads. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . signal description signal descriptions mmc2114 MMC2113 mmc2112 ? rev. 1.0 advance information motorola signal description 119 3.5.9 debug and emulation support signals these signals are used as the interface to the on-chip jtag (joint test action group) controller and also to interface to the once logic. 3.5.9.1 test reset (trst ) this active-low input signal is used to initialize the jtag and once logic asynchronously. 3.5.9.2 test clock (tclk) this input signal is the test clock used to synchronize the jtag and once logic. 3.5.9.3 test mode select (tms) this input signal is used to sequence the jtag state machine. tms is sampled on the rising edge of tclk. 3.5.9.4 test data input (tdi) this input signal is the serial input for test instructions and data. tdi is sampled on the rising edge of tclk. 3.5.9.5 test data output (tdo) this output signal is the serial output for test instructions and data. tdo is three-stateable and is actively driven in the shift-ir and shift-dr controller states. tdo changes on the falling edge of tclk. 3.5.9.6 debug event (de ) this is a bidirectional, active-low signal. as an output, this signal will be asserted for three system clocks, synchronous to the rising clkout edge, to acknowledge that the cpu has entered debug mode as a result of a debug request or a breakpoint condition. as an input, this signal provides multiple functions. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . advance information mmc2114 MMC2113 mmc2112 ? rev. 1.0 120 signal description motorola signal description 3.5.10 test signal (test) this input signal (test) is reserved for factory testing only and should be connected to v ss to prevent unintentional activation of test functions. 3.5.11 power and ground signals these signals provide system power and ground to the chip. multiple signals are provided for adequate current capability. all power supply signals must have adequate bypass capacitance for high-frequency noise suppression. 3.5.11.1 standby power (v stby ) this signal is used to provide standby voltage to the ram array if v dd is lost. typically, if used, this signal would be connected to a battery. 3.5.11.2 positive supply (v dd ) this signal supplies positive power to the core logic and i/o pads. 3.5.11.3 ground (v ss ) this signal is the negative supply (ground) to the chip. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . mmc2114 MMC2113 mmc2112 ? rev. 1.0 advance information motorola chip configuration module (ccm) 121 advance information ? mmc2114, MMC2113, and mmc2112 section 4. chip configuration module (ccm) 4.1 contents 4.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .122 4.3 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .122 4.4 modes of operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .122 4.4.1 master mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .123 4.4.2 single-chip mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .123 4.4.3 emulation mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .123 4.4.4 factory access slave test (fast) mode . . . . . . . . . . . . .123 4.5 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124 4.6 signal descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .124 4.7 memory map and registers . . . . . . . . . . . . . . . . . . . . . . . . . .125 4.7.1 programming model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .125 4.7.2 memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .126 4.7.3 register descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . .126 4.7.3.1 chip configuration register . . . . . . . . . . . . . . . . . . . . . .126 4.7.3.2 reset configuration register . . . . . . . . . . . . . . . . . . . . .129 4.7.3.3 chip identification register . . . . . . . . . . . . . . . . . . . . . .131 4.7.3.4 chip test register . . . . . . . . . . . . . . . . . . . . . . . . . . . . .132 4.8 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .133 4.8.1 reset configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .133 4.8.2 chip mode selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . .135 4.8.3 boot device selection . . . . . . . . . . . . . . . . . . . . . . . . . . . .135 4.8.4 output pad strength configuration . . . . . . . . . . . . . . . . . .137 4.8.5 clock mode selection. . . . . . . . . . . . . . . . . . . . . . . . . . . . .137 4.8.6 internal flash configuration . . . . . . . . . . . . . . . . . . . . . .138 4.9 reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .138 4.10 interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .138 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . advance information mmc2114 MMC2113 mmc2112 ? rev. 1.0 122 chip configuration module (ccm) motorola chip configuration module (ccm) 4.2 introduction the chip configuration module (ccm) controls the chip configuration and mode of operation. 4.3 features the ccm performs these operations. selects the chip operating mode: ? master mode ? single-chip mode ? emulation mode ? factory access slave test (fast) mode for factory test only selects external clock or phase-lock loop (pll) mode with internal or external reference selects output pad strength selects boot device selects module configuration selects bus monitor configuration 4.4 modes of operation the ccm configures the chip for four modes of operation: master mode single-chip mode emulation mode fast mode for factory test only the operating mode is determined at reset and cannot be changed thereafter. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . chip configuration module (ccm) modes of operation mmc2114 MMC2113 mmc2112 ? rev. 1.0 advance information motorola chip configuration module (ccm) 123 4.4.1 master mode in master mode, the internal central processor unit (cpu) can access external memories and peripherals. full master mode functionality requires the bonding out of the optional pins. the external bus consists of a 32-bit data bus and 23 address lines. available bus control signals include r/w , tc[2:0], tsiz[1:0], ta , tea , oe , and eb[3:0] . up to four chip selects can be programmed to select and control external devices and to provide bus cycle termination. when interfacing to 16-bit ports, the ports c and d pins and eb[3:2] can be configured as general-purpose input/output (i/o). 4.4.2 single-chip mode in single-chip mode, all memory is internal to the chip. external bus pins are configured as digital i/o. 4.4.3 emulation mode emulation mode supports external port replacement logic. all ports are emulated and all primary pin functions are enabled. since the full external bus must be visible to support the external port replacement logic, the emulation mode pin configuration resembles master mode. full emulation mode functionality requires bonding out the optional pins. emulation mode chip selects are provided to give additional information about the bus cycle. also, the signal shs is provided as a strobe for capturing addresses and data during show cycles. 4.4.4 factory access slave test (fast) mode fast mode is for factory test only. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . advance information mmc2114 MMC2113 mmc2112 ? rev. 1.0 124 chip configuration module (ccm) motorola chip configuration module (ccm) 4.5 block diagram figure 4-1. chip configuration module block diagram 4.6 signal descriptions table 4-1 provides an overview of the ccm signals. for more detailed information, refer to section 3. signal description . reset chip mode selection boot device selection output pad strength selection clock mode selection module configuration configuration reset configuration register chip configuration register chip identification register chip test register table 4-1. signal properties name function reset state rcon reset configuration select internal weak pullup device pllen clock mode select ? d[26, 23, 22, 21, 19, 18, 17, 16] reset configuration overrides ? f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . chip configuration module (ccm) memory map and registers mmc2114 MMC2113 mmc2112 ? rev. 1.0 advance information motorola chip configuration module (ccm) 125 4.7 memory map and registers this subsection provides a description of the memory map and registers. 4.7.1 programming model the ccm programming model consists of these registers: the chip configuration register (ccr) controls the main chip configuration. see 4.7.3.1 chip configuration register . the reset configuration register (rcon) indicates the default chip configuration. see 4.7.3.2 reset configuration register . the chip identification register (cir) contains a unique part number. see 4.7.3.3 chip identification register . the chip test register (ctr) contains chip-specific test functions. see 4.7.3.4 chip test register . some control register bits are implemented as write-once bits. these bits are always readable, but once the bit has been written, additional writes have no effect, except during debug and test operations. some write-once bits and test bits can be read and written while in debug mode or test mode. when debug or test mode is exited, the chip configuration module resumes operation based on the current register values. if a write to a write-once register bit occurs while in debug or test mode, the register bit remains writable on exit from debug or test mode. table 4-2 shows the accessibility of write-once bits. table 4-2. write-once bits read/write accessibility configuration read/write access all configurations read-always debug operation (all modes) write-always test operation (all modes) write-always master mode write-once single-chip mode write-once fast mode write-once emulation mode write-once f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . advance information mmc2114 MMC2113 mmc2112 ? rev. 1.0 126 chip configuration module (ccm) motorola chip configuration module (ccm) 4.7.2 memory map 4.7.3 register descriptions the following subsection describes the ccm registers. 4.7.3.1 chip configuration register table 4-3. chip configuration module memory map address bits 31 ? 16 bits 15 ? 0 access (1) 0x00c1_0000 chip configuration register (ccr) reserved (2) s 0x00c1_0004 reset configuration register (rcon) chip identification register (cir) s 0x00c1_0008 chip test register (ctr) reserved (2) s 0x00c1_000c unimplemented (3) ? 1. s = cpu supervisor mode access only. user mode accesses to supervisor only addresses have no effect and result in a cycle termination transfer error. 2. writing to reserved addresses has no effect; reading returns 0s. 3. accessing an unimplemented address has no effect and causes a cycle termination transfer error. address: 0x00c1_0000 and 0x00c1_0001 bit 15 14 13 12 11 10 9 bit 8 read: load 0 shen emint 0 mode2 mode1 mode0 write: reset: note 1 0 note 2 note 2 0 note 1 note 1 note 1 bit 7654321bit 0 read: 0 szen psten shint bme bmd bmt1 bmt0 write: reset:0note 3note 201000 = writes have no effect and the access terminates without a transfer error exception. notes: 1. determined during reset configuration 2. 0 for all configurations except emulation mode, 1 for emulation mode 3. 0 for all configurations except emulation and master modes, 1 for emulation and master modes figure 4-2. chip configuration register (ccr) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . chip configuration module (ccm) memory map and registers mmc2114 MMC2113 mmc2112 ? rev. 1.0 advance information motorola chip configuration module (ccm) 127 load ? pad driver load bit the load bit selects full or default drive strength for selected pad output drivers. for maximum capacitive load, set the load bit to select full drive strength. for reduced power consumption, clear the load bit to select default drive strength. 1 = full drive strength 0 = default drive strength table 4-2 shows the read/write accessibility of this write-once bit. shen ? show cycle enable bit the shen bit enables the external memory interface to drive the external bus during internal transfer operations. 1 = show cycles enabled 0 = show cycles disabled in emulation mode, the shen bit is read-only. in all other modes, it is a read/write bit. emint ? emulate internal address space bit the emint bit enables chip select 1 (cs1) to decode the internal memory address space. 1 = cs1 decodes internal memory address space. 0 = cs1 decodes external memory address space. the emint bit is read-always but can be written only in emulation mode. mode[2:0] ? chip configuration mode field this read-only field reflects the chip configuration mode, as shown in table 4-4 . table 4-4. chip configuration mode selection mode[2:0] chip configuration mode 111 master mode 110 single-chip mode 10x fast mode 0xx emulation mode f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . advance information mmc2114 MMC2113 mmc2112 ? rev. 1.0 128 chip configuration module (ccm) motorola chip configuration module (ccm) szen ? tsiz[1:0] enable bits this read/write bit enables the tsiz[1:0] function of the external pins. 1 = tsiz[1:0] function enabled 0 = tsiz[1:0] function disabled psten ? pstat[3:0] signal enable bits this read/write bit enables the pstat[3:0] function of the external pins. 1 = pstat[3:0] function enabled 0 = pstat[3:0] function disabled shint ? show interrupt bit the shint bit allows visibility to any active interrupt request to the processor. if the shint bit is set, the rstout pin is the or of the fast and normal interrupt signals. 1 = internal requests reflected on rstout pin 0 = normal rstout pin function the shint bit is read/write always. note: the frcrstout function in the reset controller has a higher priority than the shint function. bme ? bus monitor external enable bit the bme bit enables the bus monitor to operate during external bus cycles. 1 = bus monitor enabled for external bus cycles 0 = bus monitor disabled for external bus cycles table 4-2 shows the read/write accessibility of this write-once bit. bmd ? bus monitor debug mode bit the bmd bit controls how the bus monitor responds during debug mode. 1 = bus monitor enabled in debug mode 0 = bus monitor disabled in debug mode this bit is read/write always. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . chip configuration module (ccm) memory map and registers mmc2114 MMC2113 mmc2112 ? rev. 1.0 advance information motorola chip configuration module (ccm) 129 bmt[1:0] ? bus monitor timing field the bmt field selects the timeout time for the bus monitor as shown in table 4-5 . table 4-2 shows the read/write accessibility of these write-once bits. 4.7.3.2 reset configuration register the reset configuration register (rcon) is a read-only register; writing to rcon has no effect. at reset, rcon determines the default operation of certain chip functions. all default functions defined by the rcon values may be overridden during reset configuration (see 4.8.1 reset configuration ) only if the external rcon pin is asserted. table 4-5. bus monitor timeout values bmt[1:0] timeout period (in system clocks) 00 64 01 32 10 16 11 8 address: 0x00c1_0004 and 0x00c1_0005 bit 15 14 13 12 11 10 9 bit 8 read: 0 0 000000 write: reset:00000000 bit 7654321bit 0 read: 1 rpllsel 1 rpllref 0 rload 0 1 bootps 0 bootsel 0 0 mode write: reset:11001000 = writes have no effect and the access terminates without a transfer error exception. figure 4-3. reset configuration register (rcon) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . advance information mmc2114 MMC2113 mmc2112 ? rev. 1.0 130 chip configuration module (ccm) motorola chip configuration module (ccm) rpllsel ? pll mode select bit when the pll is enabled, the read-only rpllsel bit reflects the default pll mode. 1 = normal pll mode 0 = 1:1 pll mode the default pll mode can be overridden during reset configuration. if the default mode is overridden, the pllsel bit in the clock module synsr reflects the pll mode. rpllref ? pll reference bit when the pll is enabled in normal pll mode, the read-only rpllref bit reflects the default pll reference. 1 = crystal oscillator is pll reference. 0 = external clock is pll reference. the default pll reference can be overridden during reset configuration. if the default mode is overridden, the pllref bit in the clock module synsr reflects the pll reference. rload ? pad driver load bit the read-only rload bit reflects the pad driver strength configuration. 1 = full drive strength 0 = default drive strength the default function of the pad driver strength can be overridden during reset configuration. if the default mode is overridden, the load bit in ccr reflects the pad driver strength configuration. bootps ? boot port size bit if the boot device is configured to be external, the read-only bootps bit reflects the default selection for the boot port size. 1 = boot device uses 32-bit port. 0 = boot device uses 16-bit port. the default function of the boot port size can be overridden during reset configuration. if the default mode is overridden, the ps bit in cscr0 reflects the boot device port size configuration. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . chip configuration module (ccm) memory map and registers mmc2114 MMC2113 mmc2112 ? rev. 1.0 advance information motorola chip configuration module (ccm) 131 bootsel ? boot select bit this read-only bit reflects the default selection for the boot device. 1 = boot from external boot device 0 = boot from internal boot device the default function of the boot select can be overridden during reset configuration. if the default mode is overridden, the csen bit in cscr0 bit reflects the boot device configuration. mode ? chip configuration mode bit the read-only mode bit reflects the chip configuration mode. 1 = master mode 0 = single-chip mode the default mode can be overridden during reset configuration. if the default mode is overridden, the mode bits in ccr reflect the mode configuration. 4.7.3.3 chip identification register the chip identification register (cir) is a read-only register; writing to cir has no effect. address: 0x00c1_0006 and 0x00c1_0007 bit 15 14 13 12 11 10 9 bit 8 read: 0 pin7 0 pin6 0 pin5 1 pin4 1 pin3 1 pin2 1 pin1 0 pin0 write: reset:00011110 bit 7654321bit 0 read: 0 prn7 0 prn6 0 prn5 0 prn4 0 prn3 0 prn2 0 prn1 0 prn0 write: reset:00000000 = writes have no effect and the access terminates without a transfer error exception. figure 4-4. chip identification register (cir) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . advance information mmc2114 MMC2113 mmc2112 ? rev. 1.0 132 chip configuration module (ccm) motorola chip configuration module (ccm) pin[7:0] ? part identification number field this read-only field contains a unique identification number for the part. prn[7:0] ? part revision number field this read-only field contains the full-layer mask revision number. this number is increased by one for each new full-layer mask set of this part. the revision numbers are assigned in chronological order. 4.7.3.4 chip test register the chip test register (ctr) is reserved for factory testing. note: to safeguard against unintentionally activating test logic, write $0000 to the lock out test features. setting any bit in ctr may lead to unpredictable results. address: 0x00c1_0008 and 0x00c1_0009 bit 15 14 13 12 11 10 9 bit 8 read: 0 0 000000 write: reset:00000000 bit 7654321bit 0 read: 0 0 000000 write: reset:00000000 = writes have no effect and the access terminates without a transfer error exception. figure 4-5. chip test register (ctr) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . chip configuration module (ccm) functional description mmc2114 MMC2113 mmc2112 ? rev. 1.0 advance information motorola chip configuration module (ccm) 133 4.8 functional description six functions are defined within the chip configuration module: 1. reset configuration 2. chip mode selection 3. boot device selection 4. output pad strength configuration 5. clock mode selection 6. module configuration these functions are described here. 4.8.1 reset configuration during reset, the pins for the reset override functions are immediately configured to known states. table 4-6 shows the states of the external pins while in reset. if the rcon pin is not asserted during reset, the chip configuration and the reset configuration pin functions after reset are determined by rcon or fixed defaults, regardless of the states of the external data pins. the internal configuration signals are driven to levels specified by the rcon register ? s reset state for default module configuration. table 4-6. reset configuration pin states during reset pin pin function (1) 1. if the external rcon pin is not asserted during reset, pin functions are determined by the default operation mode defined in the rcon register. if the external rcon pin is asserted, pin functions are determined by the chip operation mode defined by the override values driven on the external data bus pins. i/o output state input state d[26, 23:21, 19:16], pa[4, 2], pb[7:5, 3:0] digital i/o or primary function input ? must be driven by external logic rcon rcon function for all modes (2) 2. during reset, the external rcon pin assumes its rcon pin function, but this pin changes to the function defined by the chip operation mode immediately after reset. see table 4-7 . input ? internal weak pullup device pllen not affected input ? must be driven by external logic f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . advance information mmc2114 MMC2113 mmc2112 ? rev. 1.0 134 chip configuration module (ccm) motorola chip configuration module (ccm) if the external rcon pin is asserted during reset, then various chip functions, including the reset configuration pin functions after reset, are configured according to the levels driven onto the external data pins. (see table 4-7 .) the internal configuration signals are driven to reflect the levels on the external configuration pins to allow for module configuration. table 4-7. configuration during reset (1) pin(s) affected default configuration override pins in reset (2),(3) function d[31:0], shs , ta , tea , cse[1:0], tc[2:0], oe, a[22:0], eb[3:0] , cs[3:0] rcon0 = 0 d[26,17:16] chip mode selected 111 master mode 110 single-chip mode (4) 10x fast mode 0xx emulation mode cs[1:0] rcon[3:2] = 10 d[19:18] boot device x0 internal with 32-bit port (4) 01 external with 16-bit port 11 external with 32-bit port all output pins rcon5 = 0 d21 output pad drive strength 0 default strength (4) 1 full strength clock mode rcon[7:6] = 11 pllen, d[23:22] clock mode 0xx external clock mode (pll disabled) 10x 1:1 pll mode 110 normal pll mode with external clock reference 111 normal pll mode w/crystal oscillator reference (4) 1. modifying the default configurations is possible only if the external rcon pin is asserted. 2. the d[31:29, 28, 27, 25:24, 20, 15:0] pins do not affect reset configuration. 3. the external reset override circuitry drives the data bus pins with the override values while rstout is asserted. it must stop driving the data bus pins within one clkout cycle after rstout is negated. to prevent contention with the external reset override circuitry, the reset override pins are forced to inputs during reset and do not become outputs until at least one clkout cycle after rstout is negated. 4. default configuration f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . chip configuration module (ccm) functional description mmc2114 MMC2113 mmc2112 ? rev. 1.0 advance information motorola chip configuration module (ccm) 135 4.8.2 chip mode selection the chip mode is selected during reset and reflected in the mode field of the chip configuration register (ccr). (see 4.7.3.1 chip configuration register .) once reset is exited, the operating mode cannot be changed. table 4-8 shows the mode selection during reset configuration. during reset, certain module configurations depend on whether emulation mode is active as determined by the state of the internal emulation signal. 4.8.3 boot device selection during reset configuration, the cs0 chip select pin is optionally configured to select an external boot device. in this case, the csen bit in cscr0 is set, enabling cs0 after reset. cs0 will be asserted for the initial boot fetch accessed from address 0x0. it is assumed that the reset vector loaded from address 0x0 causes the cpu to start executing from external memory space decoded by cs0 . also, the ps bit is configured for either a 16-bit or 32-bit port size depending on the external boot device. see table 4-9 . in emulation mode, the cs1 chip select pin is optionally configured for emulating an internal memory. in emulation mode and booting from internal memory, the csen bit in cscr1 is set, enabling cs1 after reset. table 4-8. chip configuration mode selection (1) 1. modifying the default configurations is possible only if the external rcon pin is asserted. chip configuration mode ccr register mode field mode2 mode1 mode0 master mode d26 driven high d17 driven high d16 driven high single-chip mode d26 driven high d17 driven high d16 driven low fast mode d26 driven high d17 driven low d16 don ? t care emulation mode d26 driven low d17 don ? t care d16 don ? t care f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . advance information mmc2114 MMC2113 mmc2112 ? rev. 1.0 136 chip configuration module (ccm) motorola chip configuration module (ccm) once reset is exited, the states of the csen and ps bits in cscr0 and the csen bit in cscr1 remain, but can be modified by software. the boot device selection during reset configuration is summarized in table 4-10 . table 4-9. chip select cs0 configuration encoding chip select cs0 control cscr0 register cscr1 register csen bit ps bit csen bit chip select disabled (32-bit port size) 0 1 1 (1) 1. cscr1 csen is initially set only in emulation mode when booting from internal memory and is cleared otherwise. chip select enabled with 16-bit port size 1 0 0 chip select enabled with 32-bit port size 1 1 0 table 4-10. boot device selection (1) 1. modifying the default configurations is possible only if the external rcon pin is asserted. boot device selection cscr0 register cscr1 register csen bit ps bit csen bit internal boot device; default 32-bit port d18 driven low d19 don ? t care d18 driven low external boot device with 16-bit port d18 driven high d19 driven low d18 driven high external boot device with 32-bit port d18 driven high d19 driven high d18 driven high f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . chip configuration module (ccm) functional description mmc2114 MMC2113 mmc2112 ? rev. 1.0 advance information motorola chip configuration module (ccm) 137 4.8.4 output pad strength configuration output pad strength is determined during reset configuration as shown in table 4-11 . see 23.7 dc electrical specifications for drive capability for each setting. once reset is exited, the output pad strength configuration can be changed by programming the load bit of the chip configuration register. 4.8.5 clock mode selection the clock mode is selected during reset and reflected in the pllmode, pllsel, and pllref bits of synsr. once reset is exited, the clock mode cannot be changed. table 4-12 summarizes clock mode selection during reset configuration. table 4-11. output pad driver strength selection (1) 1. modifying the default configurations is possible only if the external rcon pin is asserted low. optional pin function selection ccr register load bit output pads configured for default strength d21 driven low output pads configured for full strength d21 driven high table 4-12. clock mode selection (1) clock mode synthesizer status register (synsr) mode bit pllsel bit pllref bit external clock mode; pll disabled pllen driven low d23 don ? t care d22 don ? t care 1:1 pll mode pllen driven high d23 driven low d22 don ? t care normal pll mode; external clock reference pllen driven high d23 driven high d22 driven low normal pll mode; crystal oscillator reference pllen driven high d23 driven high d22 driven high 1. modifying the default configurations is possible only if the external rcon pin is asserted low. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . advance information mmc2114 MMC2113 mmc2112 ? rev. 1.0 138 chip configuration module (ccm) motorola chip configuration module (ccm) 4.8.6 internal flash configuration the internal flash in the MMC2113 and mmc2114 is always enabled. 4.9 reset reset initializes ccm registers to a known startup state as described in 4.7 memory map and registers . the ccm controls chip configuration at reset as described in 4.8 functional description . 4.10 interrupts the ccm does not generate interrupt requests. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . mmc2114 MMC2113 mmc2112 ? rev. 1.0 advance information motorola reset controller module 139 advance information ? mmc2114, MMC2113, and mmc2112 section 5. reset controller module 5.1 contents 5.2 overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .140 5.3 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .140 5.4 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141 5.5 signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .141 5.5.1 reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .142 5.5.2 rstout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .142 5.6 memory map and registers . . . . . . . . . . . . . . . . . . . . . . . . . .142 5.6.1 reset control register . . . . . . . . . . . . . . . . . . . . . . . . . . . .143 5.6.2 reset status register . . . . . . . . . . . . . . . . . . . . . . . . . . . .145 5.7 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .147 5.7.1 reset sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .147 5.7.1.1 power-on reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .148 5.7.1.2 external reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .148 5.7.1.3 watchdog timer reset . . . . . . . . . . . . . . . . . . . . . . . . .148 5.7.1.4 loss of clock reset . . . . . . . . . . . . . . . . . . . . . . . . . . . .148 5.7.1.5 loss of lock reset . . . . . . . . . . . . . . . . . . . . . . . . . . . .149 5.7.1.6 software reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .149 5.7.1.7 lvd reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .149 5.7.2 reset control flow. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .149 5.7.2.1 synchronous reset requests . . . . . . . . . . . . . . . . . . . .151 5.7.2.2 internal reset request . . . . . . . . . . . . . . . . . . . . . . . . .151 5.7.2.3 power-on reset/low-voltage detect reset . . . . . . . . .151 5.7.3 concurrent resets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .152 5.7.3.1 reset flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .152 5.7.3.2 reset status flags. . . . . . . . . . . . . . . . . . . . . . . . . . . . .152 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . advance information mmc2114 MMC2113 mmc2112 ? rev. 1.0 140 reset controller module motorola reset controller module 5.2 overview the reset controller is provided to determine the cause of reset, assert the appropriate reset signals to the system, and then to keep a history of what caused the reset. the power management cpu (pmm) control registers that generate low-voltage detect (lvd) bits are implemented in the reset module. 5.3 features module features include: six sources of reset: ? external ? power-on reset (por) ? watchdog timer ? phase locked-loop (pll) loss of lock ? pll loss of clock ? software ? lvd reset software-assertable rstout pin independent of chip reset state software-readable status flags indicating the cause of the last reset lvd control and status bits for setup and use of lvd reset or interrupt f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . reset controller module block diagram mmc2114 MMC2113 mmc2112 ? rev. 1.0 advance information motorola reset controller module 141 5.4 block diagram figure 5-1 illustrates the reset controller and pmm controller and is explained in the following sections. figure 5-1. reset controller block diagram 5.5 signals table 5-1 provides a summary of the reset controller signal properties. the signals are described in the following paragraphs. power-on reset watchdog timer timeout pll loss of clock pll loss of lock software reset lvd detect reset pin reset controller and pmm controller rsout pin to internal resets to pmm hard block table 5-1. reset controller signal properties name direction input hysteresis input synchronization reset pin i y y (1) 1. reset is always synchronized except when in low-power stop mode. rstout pin o ?? f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . advance information mmc2114 MMC2113 mmc2112 ? rev. 1.0 142 reset controller module motorola reset controller module 5.5.1 reset asserting the external reset pin for at least four rising clkout edges causes the external reset request to be recognized and latched. 5.5.2 rstout this active-low output signal is driven low when the internal reset controller module resets the chip. when rstout is active, the user can drive override options on the data bus. 5.6 memory map and registers the reset controller programming model consists of these registers: reset control register (rcr) ? selects reset controller functions reset status register (rsr) ? reflects the state of the last reset source see table 5-2 for the address map and the following paragraphs for a description of the registers. table 5-2. reset controller address map address bits 7:0 access (1) 1. s/u = supervisor or user mode access. 0x00c4_0000 rcr ? reset control register s/u 0x00c4_0001 rsr ? reset status register s/u 0x00c4_0002 reserved (2) ? 0x00c4_0003 reserved (2) 2. writes to reserved address locations have no effect and reads return 0s. ? f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . reset controller module memory map and registers mmc2114 MMC2113 mmc2112 ? rev. 1.0 advance information motorola reset controller module 143 5.6.1 reset control register the reset control register (rcr) allows software control for requesting a reset, for independently asserting the external rstout pin, and for controlling low-voltage detect (lvd) functions. softrst ? software reset request the softrst bit allows software to request a reset. the reset caused by setting this bit clears this bit. 1 = software reset request 0 = no software reset request frcrstout ? force rstout pin the frcrstout bit allows software to assert or negate the external rstout pin. 1 = assert rstout pin 0 = negate rstout pin caution: external logic driving reset configuration data during reset needs to be considered when asserting the rstout pin when setting frcrstout. address: 0x00c4_0000 bit 7654321bit 0 read: softrst frcr- stout 0 lvdf lvdie lvdre lvdse lvde write: reset:000 see note0111 note: reset dependent = writes have no effect and terminate without transfer error exception. figure 5-2. reset control register (rcr) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . advance information mmc2114 MMC2113 mmc2112 ? rev. 1.0 144 reset controller module motorola reset controller module lvdf ? lvd flag the lvdf bit indicates the low-voltage detect status if lvde is set. write a 1 to clear the lvdf bit. 1 = low voltage has been detected 0 = low voltage has not been detected note: the setting of this flag causes an lvd interrupt if lvde and lvdie bits are set and lvdre is cleared when the supply voltage v dd drops below v dd (minimum). the vector for this interrupt is shared with int0 of the eport module. interrupt arbitration in the interrupt service routine is necessary if both of these interrupts are enabled. lvdie ? lvd interrupt enable the lvdie bit controls the lvd interrupt if lvde is set. this bit has no effect if the lvde bit is a logic 0. 1 = lvd interrupt enabled 0 = lvd interrupt disabled lvdre ? lvd reset enable the lvdre bit controls the lvd reset if lvde is set. this bit has no effect if the lvde bit is a logic 0. lvd reset has priority over lvd interrupt, if both are enabled. 1 = lvd reset enabled 0 = lvd reset disabled lvdse ? lvd stop enable the lvdse bit controls the behavior of the lvd when the mcu stop mode is entered if lvde is set. this bit has no effect if the lvde bit is a logic 0. 1 = lvd enabled in mcu stop mode 0 = lvd disabled in mcu stop mode lvde ? lvd enable the lvde bit controls whether the lvd is enabled. 1 = lvd is enabled 0 = lvd is disabled f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . reset controller module memory map and registers mmc2114 MMC2113 mmc2112 ? rev. 1.0 advance information motorola reset controller module 145 5.6.2 reset status register the reset status register (rsr) contains a status bit for every reset source. when reset is entered, the cause of the reset condition is latched along with a value of 0 for the other reset sources that were not pending at the time of the reset condition. these values are then reflected in rsr. one or more status bits may be set at the same time. the cause of any subsequent reset is also recorded in the register, overwriting status from the previous reset condition. rsr can be read at any time. writing to rsr has no effect. lvd ? low-voltage detect this bit indicates that the last reset state was caused by an lvd reset. 1 = last reset state was caused by an lvd reset 0 = last reset state was not caused by an lvd reset soft ? software reset flag soft indicates that the last reset was caused by software. 1 = last reset caused by software 0 = last reset not caused by software wdr ? watchdog timer reset flag wdr indicates that the last reset was caused by a watchdog timer timeout. 1 = last reset caused by watchdog timer timeout 0 = last reset not caused by watchdog timer timeout address: 0x00c4_0001 bit 7654321bit 0 read: 0 lvd soft wdr por ext loc lol write: reset: 0 reset dependent = writes have no effect and terminate without transfer error exception. figure 5-3. reset status register (rsr) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . advance information mmc2114 MMC2113 mmc2112 ? rev. 1.0 146 reset controller module motorola reset controller module por ? power-on reset flag por indicates that the last reset was caused by a power-on reset. 1 = last reset caused by power-on reset 0 = last reset not caused by power-on reset ext ? external reset flag ext indicates that the last reset was caused by an external device asserting the external reset pin. 1 = last reset state caused by external reset 0 = last reset not caused by external reset loc ? loss of clock reset flag loc indicates that the last reset state was caused by a pll los of clock. 1 = last reset caused by loss of clock 0 = last reset not caused by loss of clock lol ? loss of lock reset flag lol indicates that the last reset state was caused by a pll loss of lock. 1 = last reset caused by a loss of lock 0 = last reset not caused by loss of lock f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . reset controller module functional description mmc2114 MMC2113 mmc2112 ? rev. 1.0 advance information motorola reset controller module 147 5.7 functional description 5.7.1 reset sources table 5-3 defines the sources of reset and the signals driven by the reset controller. to protect data integrity, a synchronous reset source is not acted upon by the reset control logic until the end of the current bus cycle. reset is then asserted on the next rising edge of the system clock after the cycle is terminated. whenever the reset control logic must synchronize reset to the end of the bus cycle, the internal bus monitor is automatically enabled regardless of the bme bit state in the chip configuration module ccr register. then, if the current bus cycle is not terminated normally the bus monitor terminates the cycle based on the length of time programmed in the bmt field of the ccr register. internal single-byte, half-word, or word writes are guaranteed to complete without data corruption when a synchronous reset occurs. external writes, including word writes to 16-bit ports, are also guaranteed to complete. asynchronous reset sources usually indicate a catastrophic failure. therefore, the reset control logic does not wait for the current bus cycle to complete. reset is asserted immediately to the system. table 5-3. reset source summary source type power on asynchronous external reset pin (not stop mode) synchronous external reset pin (during stop mode) asynchronous watchdog timer synchronous loss of clock asynchronous loss of lock asynchronous software synchronous lvd reset asynchronous f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . advance information mmc2114 MMC2113 mmc2112 ? rev. 1.0 148 reset controller module motorola reset controller module 5.7.1.1 power-on reset at power up, the reset controller asserts rstout . rstout continues to be asserted until v dd has reached a minimum acceptable level and, if pll clock mode is selected, until the pll achieves phase lock. then after approximately another 512 cycles, rstout is negated and the part begins operation. 5.7.1.2 external reset asserting the external reset pin for at least four rising clkout edges causes the external reset request to be recognized and latched. the bus monitor is enabled and the current bus cycle is completed. the reset controller asserts rstout for approximately 512 cycles after the reset pin is negated and the pll has acquired lock. the part then exits reset and begins operation. in low-power stop mode, the system clocks are stopped. asserting the external reset pin in stop mode causes an external reset to be recognized. 5.7.1.3 watchdog timer reset a watchdog timer timeout causes timer reset request to be recognized and latched. the bus monitor is enabled and the current bus cycle is completed. if the reset pin is negated and the pll has acquired lock, the reset controller asserts rstout for approximately 512 cycles. then the part exits reset and begins operation. 5.7.1.4 loss of clock reset this reset condition occurs in pll clock mode when the locre bit in the syncr register is set and either the pll reference or the pll fails. the reset controller asserts rstout for approximately 512 cycles after the pll has acquired lock. the part then exits reset and begins operation. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . reset controller module functional description mmc2114 MMC2113 mmc2112 ? rev. 1.0 advance information motorola reset controller module 149 5.7.1.5 loss of lock reset this reset condition occurs in pll clock mode when the lolre bit in the syncr register is set and the pll loses lock. the reset controller asserts rstout for approximately 512 cycles after the pll has acquired lock. the part then exits reset and resumes operation. 5.7.1.6 software reset a software reset occurs the softrst bit is set. if the reset pin is negated and the pll has acquired lock, the reset controller asserts rstout for approximately 512 cycles. then the part exits reset and resumes operation. 5.7.1.7 lvd reset the lvd reset will occur when the supply input voltage drops below v dd (minimum). 5.7.2 reset control flow the reset logic control flow is shown in figure 5-4 . in this figure, the control state boxes have been numbered, and these numbers are referred to (within parentheses) in the flow description that follows. all cycle counts given are approximate. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . advance information mmc2114 MMC2113 mmc2112 ? rev. 1.0 150 reset controller module motorola reset controller module figure 5-4. reset control flow reset pin or wd timeout or sw reset? loss of clock? loss of lock? reset negated? pll mode? bus cycle complete? rcon asserted? pll locked? enable bus monitor assert rstout and latch reset status wait 512 clkout cycles latch configuration negate rstout por or lvd assert rstout and latch reset status n n n y y y 1 2 3 n n n 0 5 6 7 8 9 10 11 y y n n y y 12 4 9a 11a y f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . reset controller module functional description mmc2114 MMC2113 mmc2112 ? rev. 1.0 advance information motorola reset controller module 151 5.7.2.1 synchronous reset requests in this discussion, the reference in parentheses refer to the state numbers in figure 5-4 . all cycle counts given are approximate. if either the external reset pin is asserted by an external device for at least four rising clkout edges (3), or the watchdog timer times out, or software requests a reset, the reset control logic latches the reset request internally and enables the bus monitor (5). when the current bus cycle is completed (6), rstout is asserted (7). the reset control logic waits until the reset pin is negated (8) and for the pll to attain lock (9, 9a) before waiting 512 clkout cycles (1).the reset control logic may latch the configuration according to the rcon pin level (11, 11a) before negating rstout (12). if the external reset pin is asserted by an external device for at least four rising clkout edges during the 512 count (10) or during the wait for pll lock (9a), the reset flow switches to (8) and waits for the reset pin to be negated before continuing. 5.7.2.2 internal reset request if reset is asserted by an asynchronous internal reset source, such as loss of clock (1) or loss of lock (2), the reset control logic asserts rstout (4). the reset control logic waits for the pll to attain lock (9, 9a) before waiting 512 clkout cycles (1). then the reset control logic may latch the configuration according to the rcon pin level (11, 11a) before negating rstout (12). if loss of lock occurs during the 512 count (10), the reset flow switches to (9a) and waits for the pll to lock before continuing. 5.7.2.3 power-on reset/low-voltage detect reset when the reset sequence is initiated by power-on reset (0), the same reset sequence is followed as for the other asynchronous reset sources. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . advance information mmc2114 MMC2113 mmc2112 ? rev. 1.0 152 reset controller module motorola reset controller module 5.7.3 concurrent resets this section describes the concurrent resets. as in the previous discussion references in parentheses refer to the state numbers in figure 5-4 . 5.7.3.1 reset flow if a power-on reset or low-voltage detect condition is detected during any reset sequence, the reset sequence starts immediately (0). if the external reset pin is asserted for at least four rising clkout edges while waiting for pll lock or the 512 cycles, the external reset is recognized. reset processing switches to wait for the external reset pin to negate (8). if a loss of clock or loss of lock condition is detected while waiting for the current bus cycle to complete (5, 6) for an external reset request, the cycle is terminated. the reset status bits are latched (7) and reset processing waits for the external reset pin to negate (8). if a loss of clock or loss of lock condition is detected during the 512 cycle wait, the reset sequence continues after a pll lock (9, 9a). 5.7.3.2 reset status flags for a por reset, the por and lvd bits in the rsr register are set, and the soft, wdr, ext, loc, and lol bits are cleared even if another type of reset condition is detected during the reset sequence for the por. if a loss of clock or loss of lock condition is detected while waiting for the current bus cycle to complete (5, 6) for an external reset request, the ext, soft, and/or wdr bits along with the loc and/or lol bits are set. if the rsr bits are latched (7) during the ext, soft, and/or wdr reset sequence with no other reset conditions detected, only the ext, soft, and/or wdr bits are set. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . reset controller module functional description mmc2114 MMC2113 mmc2112 ? rev. 1.0 advance information motorola reset controller module 153 if the rsr bits are latched (4) during the internal reset sequence with the reset pin not asserted and no soft or wdr event, then the loc and/or lol bits are the only bits set. for a lvd reset, the lvd bit in the reset status register (rsr) is set, and the soft, wdr, ext, loc, and lol bits are cleared to 0 even if another type of reset condition is detected during the reset sequence for lvd. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . advance information mmc2114 MMC2113 mmc2112 ? rev. 1.0 154 reset controller module motorola reset controller module f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . mmc2114 MMC2113 mmc2112 ? rev. 1.0 advance information motorola power management 155 advance information ? mmc2114, MMC2113, and mmc2112 section 6. power management 6.1 contents 6.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .156 6.3 low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .156 6.3.1 run mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .156 6.3.2 wait mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .157 6.3.3 doze mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .157 6.3.4 stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .157 6.3.5 peripheral shut down . . . . . . . . . . . . . . . . . . . . . . . . . . . .157 6.4 peripheral behavior in low-power modes . . . . . . . . . . . . . . .158 6.4.1 reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .158 6.4.2 clocks. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158 6.4.3 once . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .159 6.4.4 jtag . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .160 6.4.5 interrupt controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .160 6.4.6 edge port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .160 6.4.7 random-access memory (ram) . . . . . . . . . . . . . . . . . . . .160 6.4.8 flash . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .161 6.4.9 queued analog-to-digital converter (qadc) . . . . . . . . . .161 6.4.10 watchdog timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .161 6.4.11 programmable interrupt timers (pit1 and pit2). . . . . . . .162 6.4.12 serial peripheral interface (spi). . . . . . . . . . . . . . . . . . . . .162 6.4.13 serial communication interfaces (sci1 and sci2) . . . . . .162 6.4.14 timers (tim1 and tim2). . . . . . . . . . . . . . . . . . . . . . . . . . .163 6.5 summary of peripheral state during low-power modes . . . .163 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . advance information mmc2114 MMC2113 mmc2112 ? rev. 1.0 156 power management motorola power management 6.2 introduction the following features support low power operation. four modes of operation: ? run ? wait ? doze ? stop ability to shut down most peripherals independently ability to shut down the external clkout pin 6.3 low-power modes the system enters a low-power mode by execution of a stop, wait, or doze instruction.this idles the cpu with no cycles active. an internal signal indicates to the system and clock controller to power down and stop the clocks appropriately. during stop mode, the system clock is stopped low. a wakeup event is required to exit a low-power mode and return to run mode. wakeup events consist of any of these conditions: any type of reset assertion of the de pin to request entry into debug mode debug request bit set in the once control register to request entry into debug mode any valid interrupt request 6.3.1 run mode run mode is the normal system operating mode. current consumption in this mode is related directly to the system clock frequency. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . power management low-power modes mmc2114 MMC2113 mmc2112 ? rev. 1.0 advance information motorola power management 157 6.3.2 wait mode wait mode is intended to be used to stop only the cpu and memory clocks until a wakeup event is detected. in this mode, peripherals may be programmed to continue operating and can generate interrupts, which cause the cpu to exit from wait mode. 6.3.3 doze mode doze mode affects the cpu in the same manner as wait mode, except that each peripheral defines individual operational characteristics in doze mode. peripherals which continue to run and have the capability of producing interrupts may cause the cpu to exit the doze mode and return to run mode. peripherals which are stopped will restart operation on exit from doze mode as defined for each peripheral. 6.3.4 stop mode stop mode affects the cpu in the same manner as the wait and doze modes, except that all clocks to the system are stopped and the peripherals cease operation. stop mode must be entered in a controlled manner to ensure that any current operation is properly terminated. when exiting stop mode, most peripherals retain their pre-stop status and resume operation. the following subsections specify the operation of each module while in and when exiting low-power modes. 6.3.5 peripheral shut down most peripherals may be disabled by software in order to cease internal clock generation and remain in a static state. each peripheral has its own specific disabling sequence (refer to each peripheral description for further details). a peripheral may be disabled at any time and will remain disabled during any low-power mode of operation. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . advance information mmc2114 MMC2113 mmc2112 ? rev. 1.0 158 power management motorola power management 6.4 peripheral behavior in low-power modes 6.4.1 reset a power-on reset (por) will always cause a chip reset and exit from any low-power mode. in wait and doze modes, asserting the external reset pin for at least four clocks will cause an external reset that will reset the chip and exit any low-power modes. in stop mode, the reset pin synchronization is disabled and asserting the external reset pin will asynchronously generate an internal reset and exit any low-power modes. registers will loose current values and must be reconfigured from reset state if needed. if the phase lock loop (pll) is active, then any loss of clock or loss of lock will reset the chip and exit any low-power modes. if the watchdog timer is still enabled during wait or doze modes, then a watchdog timer timeout may generate a reset to exit these low-power modes. when the cpu is inactive, a software reset can not be generated to exit any low-power mode. 6.4.2 clocks during the low power wait and doze modes, the clocks to the cpu, flash, and random-access memory (ram) will be stopped and the system clocks to the peripherals are enabled. each module may disable the module clocks locally at the module level. during the low-power stop mode, all clocks to the system will be stopped. during stop mode, there are several options for enabling/disabling the pll and/or crystal oscillator (osc) compromising between wakeup recovery time and stop mode power. the pll may be disabled during stop. a wakeup time of up to 200 s is required for the pll to re-lock. the osc may also be disabled during stop. a wakeup time required f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . power management peripheral behavior in low-power modes mmc2114 MMC2113 mmc2112 ? rev. 1.0 advance information motorola power management 159 for the osc to restart is dependent upon the startup time of the crystal used. power consumption can be reduced in stop mode by disabling either or both of these functions via the stmpd bits of the synthesizer control register (syncr). see 11.7.2.1 synthesizer control register . the external clkout signal may be enabled during low-power stop (if the pll is still enabled) to support systems using this signal as the clock source. the system clocks may be enabled during wakeup from stop mode without waiting for the pll to lock. this eliminates the wakeup recovery time, but at the risk of sending a potentially unstable clock to the system. it is recommended, if this option is used, that the pll frequency divider is set so that the targeted system frequency is no more than half the maximum allowed. this will allow for any frequency overshoot of the pll while still keeping the system clock within specification. in external clock mode, there are no wait times for the osc startup or pll lock. during wakeup from stop mode, the flash clock will always clock through 16 cycles before the system clocks are enabled. this allows the flash module time to recover from the low-power mode. thus, software may immediately continue to fetch instructions from the flash memory. the external clkout output pin may be disabled in the low state to lower power consumption via the disable clkout (disclk) bit in the syncr. the external clkout pin function is enabled by default at reset. 6.4.3 once the once logic is clocked using the tclk input and is not affected by the system clock. entering debug mode via the once port (or asserting the external de pin) will cause the cpu to exit any low-power mode. toggling tclk during any low-power mode will increase the system current consumption. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . advance information mmc2114 MMC2113 mmc2112 ? rev. 1.0 160 power management motorola power management 6.4.4 jtag the jtag (joint test action group) controller logic is clocked using the tclk input and is not affected by the system clock. the jtag cannot generate an event to cause the cpu to exit any low-power mode. toggling tclk during any low-power mode will increase the system current consumption. 6.4.5 interrupt controller the interrupt controller is not affected by any of the low-power modes. all logic between the input sources and generating the interrupt to the m core processor will be combinational to allow the ability to wakeup the cpu processor during low-power stop mode when all system clocks are stopped. a fast interrupt request will cause the cpu to exit a low-power mode only if the fe bit in the cpu ? s psr register is set. a normal interrupt request will cause the cpu to exit a low-power mode only if the ie and ee bits in the cpu ? s psr register are set. 6.4.6 edge port in wait and doze modes, the edge port continues to operate normally and may be configured to generate interrupts (either an edge transition or low level on an external pin) to exit the low-power modes. in stop mode, there are no clocks available to perform the edge detect function. thus, only the level detect logic is active (if configured) to allow any low level on the external interrupt pin to generate an interrupt (if enabled) to exit the stop mode. 6.4.7 random-access memory (ram) the random-access memory (ram) is disabled during any low-power mode. no recovery time is required when exiting any low-power mode. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . power management peripheral behavior in low-power modes mmc2114 MMC2113 mmc2112 ? rev. 1.0 advance information motorola power management 161 6.4.8 flash the flash is in a low-power state if not being accessed. no recovery time is required after exit from any low-power mode. 6.4.9 queued analog-to-digital converter (qadc) setting the queued analog-to-digital converter (qadc) stop bit (qstop) will disable the qadc. the qadc is unaffected by either wait or doze mode and may generate an interrupt to exit these modes. low-power stop mode (or setting the qstop bit), immediately freezes operation, register values, state machines, and external pins. this stops the clock signals to the digital electronics of the module and eliminates the quiescent current draw of the analog electronics. any conversion sequences in progress are stopped. exit from low-power stop mode (or clearing the qstop bit), returns the qadc to operation from the state prior to stop mode entry, but any conversions in progress are undefined and the qadc requires recovery time (t sr in 23.9 qadc electrical characteristics ) to stabilize the analog circuits before new conversions can be performed. 6.4.10 watchdog timer in stop mode (or in wait/doze mode, if so programmed), the watchdog ceases operation and freezes at the current value.when exiting these modes, the watchdog resumes operation from the stopped value. it is the responsibility of software to avoid erroneous operation. when not stopped, the watchdog may generate a reset to exit the low-power modes. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . advance information mmc2114 MMC2113 mmc2112 ? rev. 1.0 162 power management motorola power management 6.4.11 programmable interrupt timers (pit1 and pit2) in stop mode (or in doze mode, if so programmed), the programmable interrupt timer (pit) ceases operation, and freezes at the current value. when exiting these modes, the pit resumes operation from the stopped value. it is the responsibility of software to avoid erroneous operation. when not stopped, the pit may generate an interrupt to exit the low-power modes. 6.4.12 serial peripheral interface (spi) when not stopped, the serial peripheral interface (spi) may generate an interrupt to exit the low-power modes. clearing the spi enable bit (spe) disables the spi function. the spi is unaffected by wait mode and may generate an interrupt to exit this mode. spi operation in doze mode is programmable. depending on the state of internal bits, the spi can operate normally when the cpu is in doze mode or the spi clock generation can be turned off and the spi module enters a power conservation state during doze mode. during doze mode, any master transmission in progress stops. reception and transmission of a byte as slave continues so that the slave is synchronized to the master. the spi is inactive in stop mode for reduced power consumption. 6.4.13 serial communication interfaces (sci1 and sci2) when not stopped, the serial communications interface (sci) may generate an interrupt to exit the low-power modes. clearing the transmit enable bit (te) or the receiver enable bit (re) disables sci functions. the scis are unaffected by wait mode and may generate an interrupt to exit this mode. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . power management summary of peripheral state during low-power modes mmc2114 MMC2113 mmc2112 ? rev. 1.0 advance information motorola power management 163 in stop mode (or doze mode, if so programmed), the scis stop immediately and freeze their operation, register values, state machines, and external pins. during these modes, the sci clocks are shut down. coming out of the doze or stop modes, returns the scis to operation from the state prior to the low-power mode entry. 6.4.14 timers (tim1 and tim2) when not stopped, the timers may generate an interrupt to exit the low-power modes. clearing the timer enable bit (te) in the timer system control register 1 (timscr1) or the pulse accumulator enable bit (pae) in the pulse accumulator control register (timpactl) disables timer functions. timer and pulse accumulator registers are still accessible by the cpu and once interface, but the remaining functions of the timer are disabled. see 16.7.6 timer system control register 1 and 16.7.15 pulse accumulator control register . the timer is unaffected by either the wait or doze modes and may generate an interrupt to exit these modes. in stop mode, the timers stop immediately and freeze their operation, register values, state machines, and external pins. upon exiting stop mode, the timer will resume operation unless stop mode was exited by reset. 6.5 summary of peripheral state during low-power modes the functionality of each of the peripherals and cpu during the various low-power modes is summarized in table 6-1 . the status of each peripheral during a given mode refers to the condition the peripheral automatically assumes when the particular instruction (wait, doze, or stop) is executed. individual peripherals may be disabled by programming its dedicated control bits. the wakeup capability field refers to the ability of an interrupt or reset by that peripheral to force the cpu into run mode. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . advance information mmc2114 MMC2113 mmc2112 ? rev. 1.0 164 power management motorola power management table 6-1. cpu and peripherals in low-power modes module peripheral status (1) / wakeup capability run mode wait mode doze mode stop mode cpu enabled stopped no stopped no stopped no reset enabled enabled yes (2) enabled yes (2) enabled yes (2) clock enabled enabled yes (2) enabled yes (2) program yes (2) once enabled enabled yes (3) enabled yes (3) enabled yes (3) jtag enabled enabled no enabled no enabled no interrupt controller enabled enabled yes (4) enabled yes (4) enabled yes (4) edge port enabled enabled yes (4) enabled yes (4) stopped yes (4) ram enabled stopped no stopped no stopped no flash enabled stopped no stopped no stopped no qadc enabled enabled yes (4) enabled yes (4) stopped no watchdog timer enabled program yes (2) program yes (2) stopped no pit1 and pit2 enabled enabled yes (4) program yes (4) stopped no spi enabled enabled yes (4) program yes (4) stopped no sci1 and sci2 enabled enabled yes (4) program yes (4) stopped no tim1 and tim2 enabled enabled yes (4) enabled yes (4) stopped no 1. ? program ? indicates that the peripheral function during the low-power mode is dependent on programmable bits in the peripheral register map. 2. these modules can generate a reset which will exit any low-power mode. 3. the once logic is clocked by a separate tclk clock. entering debug mode via the once port (or assertion of the external de pin) exits any low-power mode. upon exit from debug mode, the previous low-power mode will be re-entered and the changes made during debug mode will remain in effect. 4. these modules can generate a interrupt which will exit any low-power mode. the cpu will begin to service the interrupt exception after wakeup. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . mmc2114 MMC2113 mmc2112 ? rev. 1.0 advance information motorola m core m210 central processor unit (cpu) 165 advance information ? mmc2114, MMC2113, and mmc2112 section 7. m core m210 central processor unit (cpu) 7.1 contents 7.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .165 7.3 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .166 7.4 microarchitecture summary . . . . . . . . . . . . . . . . . . . . . . . . . .167 7.5 programming model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .169 7.6 data format summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .171 7.7 operand addressing capabilities . . . . . . . . . . . . . . . . . . . . . .172 7.8 instruction set overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . .172 7.2 introduction the m core m210 central processor unit (cpu) architecture is one of the most compact, full 32-bit core implementations available. the pipelined reduced instruction set computer (risc) execution unit uses 16-bit instructions to achieve maximum speed and code efficiency, while conserving on-chip memory resources. the instruction set is designed to support high-level language implementation. a non-intrusive resident debugging system supports product development and in-situ testing. total system power consumption is determined by all the system components, rather than the cpu alone. in particular, memory power consumption (both on-chip and external) is a dominant factor in total power consumption of the cpu plus memory subsystem. with this in mind, the cpu instruction set architecture trades absolute performance capability for reduced total energy consumption. this is accomplished while maintaining a high level of performance at a given clock frequency. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . advance information mmc2114 MMC2113 mmc2112 ? rev. 1.0 166 m core m210 central processor unit (cpu) motorola m core m210 central processor unit (cpu) a strictly defined load/store architecture minimizes control complexity. use of a fixed, 16-bit instruction encoding significantly lowers the memory bandwidth needed to sustain a high rate of instruction execution, and careful selection of the instruction set allows the code density and overall memory efficiency of the cpu architecture to surpass those of complex instruction set computer (cisc) architectures. these factors reduce system energy consumption significantly, and the fully static cpu design uses other techniques to reduce power consumption even more. the cpu uses dynamic clock management to automatically power-down internal functions that are not in use on a clock-by-clock basis. it also incorporates three power-conservation operating modes, which are invoked via dedicated instructions as detailed in section 6. power management . 7.3 features the main features of the cpu are: 32-bit load/store risc architecture fixed 16-bit instruction length 13 entry, 32-bit control register file 16 entry, 32-bit general-purpose register file efficient 4-stage execution pipeline single-cycle execution for most instructions, 2-cycle branches and memory accesses support for byte/half-word/word memory access fast interrupt support availability of alternate general purpose register file vectored and autovectored interrupt support on-chip emulation support (once) full static design for minimal power consumption f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . m core m210 central processor unit (cpu) microarchitecture summary mmc2114 MMC2113 mmc2112 ? rev. 1.0 advance information motorola m core m210 central processor unit (cpu) 167 7.4 microarchitecture summary figure 7-1 is a block diagram of the m core processor. the processor utilizes a 4-stage pipeline for instruction execution. the instruction fetch, instruction decode/register file read, execute, and register file writeback stages operate in an overlapped fashion, allowing single clock instruction execution for most instructions. the execution unit consists of a 32-bit arithmetic/logic unit (alu), a 32-bit barrel shifter, a find-first-one unit, result feed-forward hardware, support hardware for multiplication and division, and multiple-register load and store instructions. figure 7-1. m core processor block diagram scale address generation address mux general-purpose register file 32 bits x 16 alternate register file 32 bits x 16 control register file 32 bits x 13 immediate mux sign ext. mux barrel shifter multiplier divider adder/logical priority encoder/ zero detect result mux data calculation pc increment branch adder instruction pipeline instruction decode address bus data x port y port mux writeback bus h/w accelerator interface bus bus f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . advance information mmc2114 MMC2113 mmc2112 ? rev. 1.0 168 m core m210 central processor unit (cpu) motorola m core m210 central processor unit (cpu) arithmetic and logical operations are executed in a single cycle. multiplication is implemented with a 2-bit per clock, overlapped-scan, modified booth algorithm with early-out capability, to reduce execution time for operations with small multipliers. divide is implemented with a 1-bit per clock early-in algorithm. the find-first-one unit operates in one clock cycle. the program counter unit incorporates a dedicated branch address adder to minimize delays during change of flow operations. branch target addresses are calculated in parallel with branch instruction decode. taken branches and jumps require only two clocks; branches which are not taken execute in one clock cycle. memory load and store operations are provided for 8-bit (byte), 16-bit (halfword), and 32-bit (word) data, with automatic zero extension for byte and half-word load operations. these instructions can execute in as few as two clock cycles. load and store multiple register instructions allow low overhead context save and restore operations. these instructions can execute in (n+1) clock cycles, where n is the number of registers to transfer. a condition code/carry (c) bit is provided for condition testing or for use in implementing arithmetic and logical operations with operands/results greater than 32 bits. the c bit is typically set by explicit test/comparison operations, not as a side-effect of normal instruction operation. exceptions to this rule occur for specialized operations where it is desirable to combine condition setting with actual computation. the processor uses autovectors for both normal and fast interrupt requests. fast interrupts take precedence over normal interrupts. both types have dedicated exception shadow registers. for service requests of either kind, an automatic vector is generated when the request is made. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . m core m210 central processor unit (cpu) programming model mmc2114 MMC2113 mmc2112 ? rev. 1.0 advance information motorola m core m210 central processor unit (cpu) 169 7.5 programming model figure 7-2 shows the m core processor programming model. the model is defined differently for supervisor and user privilege modes. by convention, in both modes r15 serves as the link register for subroutine calls. r0 is typically used as the stack pointer. figure 7-2. programming model the user programming model consists of 16 general-purpose 32-bit registers (r0 ? r15), the 32-bit pc, and the c bit. the c bit is implemented as bit 0 of the processor status register (psr) and is the only portion of the psr accessible in the user model. r0 ? r0 r1 r2 r3 r4 r5 r6 r7 r8 r9 r12 r13 r14 r15 r11 r10 c user programmer ? s model alternate file supervisor programmer ? s model pc pc c * bit 0 of psr psr vbr epsr fpsr epc fpc ss0 ss1 ss2 cr0 cr1 cr2 cr3 cr4 cr5 cr6 cr7 cr8 cr9 ss4 cr10 gcr cr11 ss3 gsr cr12 r15 r0 r1 r2 r3 r4 r5 r6 r7 r8 r9 r12 r13 r14 r11 r10 * * f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . advance information mmc2114 MMC2113 mmc2112 ? rev. 1.0 170 m core m210 central processor unit (cpu) motorola m core m210 central processor unit (cpu) the supervisor programming model consists of the user model plus 16 additional 32-bit general-purpose registers (r0 ? r15), called the alternate file and a set of status/control registers (cr0 ? cr12) which includes the entire psr. setting the s bit in the psr enables supervisor mode operation. the alternate file allows very low overhead context switching for real-time event handling. while the alternate file is enabled, general-purpose registers are accessed from it. the vector base register (vbr) determines the base address of the exception vector table. exception shadow registers epc and epsr are used to save the states of the program counter and psr, respectively, when an exception occurs. shadow registers fpc and fpsr save the states of the program counter and psr, respectively, when a fast interrupt exception occurs. five scratch registers (ss0 ? ss4) are used to handle exception events. the global control (gcr) and status (gsr) registers can be used for a variety of system monitoring tasks at the discretion of the compiler used. they serve no specific function by or for the cpu. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . m core m210 central processor unit (cpu) data format summary mmc2114 MMC2113 mmc2112 ? rev. 1.0 advance information motorola m core m210 central processor unit (cpu) 171 7.6 data format summary the operand data formats supported by the integer unit are standard two ? s-complement data formats. the operand size for each instruction is either explicitly encoded in the instruction (load/store instructions) or implicitly defined by the instruction operation (index operations, byte extraction). typically, instructions operate on all 32 bits of the source operand(s) and generate a 32-bit result. memory is viewed from a big-endian byte ordering perspective. the most significant byte (byte 0) of word 0 is located at address 0. bits are numbered within a word starting with bit 31 as the most significant bit. figure 7-3. data organization in memory figure 7-4. data organization in registers byte 0 byte 1 byte 2 byte 3 word at 0x0000 000 0 31 0 byte 4 byte 5 byte 6 byte 7 word at 0x0000 000 4 byte 8 byte 9 byte a byte b word at 0x0000 000 8 byte c byte d byte e byte f word at 0x0000 000 c byte signed byte s s s s s ss sssssssssssssss s s s 0 8 7 31 byte unsigned byte 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 8 7 31 half-word signed s s s s s s s s s s s s s s s s s 0 16 15 31 half-word half-word unsigned 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 16 15 31 half-word 0 31 word byte 3 byte 2 byte 1 byte 0 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . advance information mmc2114 MMC2113 mmc2112 ? rev. 1.0 172 m core m210 central processor unit (cpu) motorola m core m210 central processor unit (cpu) 7.7 operand addressing capabilities the m core processor accesses all memory operands through load and store instructions, transferring data between the general-purpose registers and memory. register-plus-four-bit scaled displacement addressing mode is used for load and store instructions addressing byte, half-word, and word data. load and store multiple instructions allow a subset of the 16 general-purpose registers to be transferred to or from a base address pointed to by register r0 (the default stack pointer by convention). load and store register quadrant instructions use register indirect addressing to transfer a register quadrant to or from memory. 7.8 instruction set overview the instruction set is tailored to support high-level languages and is optimized for those instructions most commonly executed. a standard set of arithmetic and logical instructions is provided, as well as instruction support for bit operations, byte extraction, data movement, control flow modification, and a small set of conditionally executed instructions which can be useful in eliminating short conditional branches. table 7-1 is an alphabetized listing of the m core instruction set. refer to the m?core reference manual (motorola document order number mcorerm/ad) for more details on instruction operation. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . m core m210 central processor unit (cpu) instruction set overview mmc2114 MMC2113 mmc2112 ? rev. 1.0 advance information motorola m core m210 central processor unit (cpu) 173 table 7-1. m core instruction set (sheet 1 of 3) mnemonic description execution time (cycles) abs addc addi addu and andi andn asr asrc absolute value add with c bit add immediate add unsigned logical and logical and immediate and not arithmetic shift right arithmetic shift right, update c bit 1 1 1 1 1 1 1 1 1 bclri bf bgeni bgenr bkpt bmaski br brev bseti bsr bt btsti bit clear immediate branch on condition false bit generate immediate bit generate register breakpoint bit mask immediate branch bit reverse bit set immediate branch to subroutine branch on condition true bit test immediate 1 1/2 (1) 1 1 indet (2) 1/2 (1) 1 1 1/2 (1) 1/2 (1) 1 clrf clrt cmphs cmplt cmplti cmpne cmpnei clear register on condition false clear register on condition true compare higher or same compare less than compare less than immediate compare not equal compare not equal immediate 1 1 1 1 1 1 1 decf decgt declt decne dect divs divu doze decrement on condition false decrement register and set condition if result greater than zero decrement register and set condition if result less than zero decrement register and set condition if result not equal to zero decrement on condition true divide signed integer divide unsigned integer doze 1 1 1 1 1 3 ? 37 (3) 3 ? 37 (3) indet (2) ff1 find first one 1 incf inct ixh ixw increment on condition false increment on condition true index half-word index word 1 1 1 1 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . advance information mmc2114 MMC2113 mmc2112 ? rev. 1.0 174 m core m210 central processor unit (cpu) motorola m core m210 central processor unit (cpu) jmp jmpi jsr jsri jump jump indirect jump to subroutine jump to subroutine indirect 2 3 2 3 ld.[bhw] ldm ldq loopt lrw lsl, lsr lslc, lsrc lsli, lsri load load multiple registers load register quadrant decrement with c-bit update and branch if condition true load relative word logical shift left and right logical shift left and right, update c bit logical shift left and right by immediate 2 n+1 (4) 5 1/2 (1) 2 1 1 1 mfcr mov movi movf movt mtcr mult mvc mvcv move from control register move move immediate move on condition false move on condition true move to control register multiply move c bit to register move inverted c bit to register 2 1 1 1 1 2 3 ? 18 (3) 1 1 not logical complement 1 or logical inclusive-or 1 rotli rsub rsubi rte rfi rotate left by immediate reverse subtract reverse subtract immediate return from exception return from interrupt 1 1 1 3 3 sextb sexth st.[bhw] stm stq stop subc subu subi sync sign-extend byte sign-extend half-word store store multiple registers store register quadrant stop subtract with c bit subtract subtract immediate synchronize 1 1 2 n+1 (4) 5 indet (2) 1 1 1 1 trap tst tstnbz trap test operands test for no byte equal zero 5 1 1 wait wait indet (2) table 7-1. m core instruction set (sheet 2 of 3) mnemonic description execution time (cycles) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . m core m210 central processor unit (cpu) instruction set overview mmc2114 MMC2113 mmc2112 ? rev. 1.0 advance information motorola m core m210 central processor unit (cpu) 175 xor xsr xtrb0 xtrb1 xtrb2 xtrb3 exclusive or extended shift right extract byte 0 extract byte 1 extract byte 2 extract byte 3 1 1 1 1 1 1 zextb zexth zero-extend byte zero-extend half-word 1 1 1. 1 cycle if branch not taken, 2 cycles if branch taken 2. execution time of bkpt, doze, wait, and stop is 1 cycle but execution does not take place until allcurrent bus trans- actions have completed. 3. cycle time is dependent upon magnitude of result. 4. number of cycles is equal to number of registers loaded/stored plus 1. table 7-1. m core instruction set (sheet 3 of 3) mnemonic description execution time (cycles) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . advance information mmc2114 MMC2113 mmc2112 ? rev. 1.0 176 m core m210 central processor unit (cpu) motorola m core m210 central processor unit (cpu) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . mmc2114 MMC2113 mmc2112 ? rev. 1.0 advance information motorola interrupt controller module 177 advance information ? mmc2114, MMC2113, and mmc2112 section 8. interrupt controller module 8.1 contents 8.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .178 8.3 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .178 8.4 low-power mode operation . . . . . . . . . . . . . . . . . . . . . . . . . .178 8.5 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 179 8.6 external signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .179 8.7 memory map and registers . . . . . . . . . . . . . . . . . . . . . . . . . .179 8.7.1 memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .180 8.7.2 registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .181 8.7.2.1 interrupt control register. . . . . . . . . . . . . . . . . . . . . . . .181 8.7.2.2 interrupt status register . . . . . . . . . . . . . . . . . . . . . . . .183 8.7.2.3 interrupt force registers . . . . . . . . . . . . . . . . . . . . . . . .184 8.7.2.4 interrupt pending register . . . . . . . . . . . . . . . . . . . . . . .186 8.7.2.5 normal interrupt enable register. . . . . . . . . . . . . . . . . .187 8.7.2.6 normal interrupt pending register. . . . . . . . . . . . . . . . .188 8.7.2.7 fast interrupt enable register . . . . . . . . . . . . . . . . . . . .189 8.7.2.8 fast interrupt pending register . . . . . . . . . . . . . . . . . . .190 8.7.2.9 priority level select registers . . . . . . . . . . . . . . . . . . . . 191 8.8 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .191 8.8.1 interrupt sources and prioritization . . . . . . . . . . . . . . . . . .192 8.8.2 fast and normal interrupt requests . . . . . . . . . . . . . . . . .192 8.8.3 autovectored and vectored interrupt requests . . . . . . . . .193 8.8.4 interrupt configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . .195 8.8.4.1 cpu configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . .195 8.8.4.2 interrupt controller configuration. . . . . . . . . . . . . . . . . .195 8.8.4.3 interrupt source configuration . . . . . . . . . . . . . . . . . . . .196 8.8.5 interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .196 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . advance information mmc2114 MMC2113 mmc2112 ? rev. 1.0 178 interrupt controller module motorola interrupt controller module 8.2 introduction the interrupt controller collects requests from multiple interrupt sources and provides an interface to the cpu interrupt logic. 8.3 features features of the interrupt controller module include: up to 40 interrupt sources 32 unique programmable priority levels for each interrupt source independent enable/disable of pending interrupts based on priority level select normal or fast interrupt request for each priority level fast interrupt requests always have priority over normal interrupts ability to mask interrupts at and below a defined priority level ability to select between autovectored or vectored interrupt requests vectored interrupts generated based on priority level ability to generate a separate vector number for normal and fast interrupts ability for software to self-schedule interrupts software visibility of pending interrupts and interrupt signals to core asynchronous operation to support wakeup from low-power modes 8.4 low-power mode operation the interrupt controller is not affected by any low-power modes. all logic between the input sources and generating the raw interrupt to the cpu is combinational. this allows the cpu to wake up during low-power stop mode when all system clocks are stopped. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . interrupt controller module block diagram mmc2114 MMC2113 mmc2112 ? rev. 1.0 advance information motorola interrupt controller module 179 8.5 block diagram figure 8-1. interrupt controller block diagram 8.6 external signals no interrupt controller signals connect off-chip. 8.7 memory map and registers this subsection describes the memory map (see table 8-1 ) and registers. interrupt sources f i e r f i p r n i p r icr vector n i e r 32-to-5 priority encoder or or & fve normal ae i f r m u c 32 32 32 40 32 40 x 5 bits 32 32 40 plsr plsr autovector s y n c s y n c & & 5 or priority level select i p r isr & me 5 decode mask mfi 32 32 32 & & fmask nmask nmask & fmask plsr plsr select and fast interrupts number f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . advance information mmc2114 MMC2113 mmc2112 ? rev. 1.0 180 interrupt controller module motorola interrupt controller module 8.7.1 memory map table 8-1. interrupt controller module memory map address bits 31 ? 24 bits 23 ? 16 bits 15 ? 8bits 7 ? 0 access (1) 0x00c5_0000 interrupt control register (icr) interrupt status register (isr) s/u 0x00c5_0004 interrupt force register high (ifrh) s/u 0x00c5_0008 interrupt force register low (ifrl) s/u 0x00c5_000c interrupt pending register (ipr) s/u 0x00c5_0010 normal interrupt enable register (nier) s/u 0x00c5_0014 normal interrupt pending register (nipr) s/u 0x00c5_0018 fast interrupt enable register (fier) s/u 0x00c5_001c fast interrupt pending register (fipr) s/u 0x00c5_0020 through 0x00c5_003c unimplemented (2) ? priority level select registers (plsr0 ? plsr39) 0x00c5_0040 plsr0 plsr1 plsr2 plsr3 s 0x00c5_0044 plsr4 plsr5 plsr6 plsr7 s 0x00c5_0048 plsr8 plsr9 plsr10 plsr11 s 0x00c5_004c plsr12 plsr13 plsr14 plsr15 s 0x00c5_0050 plsr16 plsr17 plsr18 plsr19 s 0x00c5_0054 plsr20 plsr21 plsr22 plsr23 s 0x00c5_0058 plsr24 plsr25 plsr26 plsr27 s 0x00c5_005c plsr28 plsr29 plsr30 plsr31 s 0x00c5_0060 plsr32 plsr33 plsr34 plsr35 s 0x00c5_0064 plsr36 plsr37 plsr38 plsr39 s 0x00c5_0068 through 0x00c5_007c unimplemented (2) ? 1. s = cpu supervisor mode access only. s/u = cpu supervisor or user mode access. user mode accesses to supervisor only addresses have no effect and result in a cycle termination transfer error. 2. accesses to unimplemented address locations have no effect and result in a cycle termination transfer error. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . interrupt controller module memory map and registers mmc2114 MMC2113 mmc2112 ? rev. 1.0 advance information motorola interrupt controller module 181 8.7.2 registers this subsection contains a description of the interrupt controller module register set. 8.7.2.1 interrupt control register the 16-bit interrupt control register (icr) selects whether interrupt requests are autovectored or vectored, and if vectored, whether fast interrupts generate a different vector number than normal interrupts. this register also controls the masking functions. ae ? autovector enable bit the read/write ae bit enables fast and normal autovectored interrupt requests. reset sets ae. 1 = autovectored interrupt requests 0 = vectored interrupt requests fve ? fast vector enable bit the read/write fve bit enables fast vectored interrupt requests to have vector numbers separate from normal vectored interrupt requests. reset clears fve. 1 = unique vector numbers for fast vectored interrupt requests 0 = same vector number for fast and normal vectored interrupt requests address: 0x00c5_0000 and 0x00c5_0001 bit 15 14 13 12 11 10 9 bit 8 read: ae fve me mfi 0000 write: reset:10000000 bit 7654321bit 0 read: 0 0 0 mask4 mask3 mask2 mask1 mask0 write: reset:00000000 = writes have no effect and the access terminates without a transfer error exception. figure 8-2. interrupt control register (icr) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . advance information mmc2114 MMC2113 mmc2112 ? rev. 1.0 182 interrupt controller module motorola interrupt controller module me ? mask enable bit the read/write me bit enables interrupt masking. reset clears me. 1 = interrupt masking enabled 0 = interrupt masking disabled mfi ? mask fast interrupts bit the read/write mfi bit enables masking of fast interrupt requests. reset clears mfi. 1 = fast interrupt requests masked by mask value. all normal interrupt requests are masked. 0 = fast interrupt requests are not masked regardless of the mask value. the mask only applies to normal interrupts. reset clears mfi. mask[4:0] ? interrupt mask field the read/write mask[4:0] field determines which interrupt priority levels are masked. when the me bit is set, all pending interrupt requests at priority levels at and below the current mask value are masked. to mask all normal interrupts without masking any fast interrupts, set the mask value to 31 with the mfi bit cleared. see table 8-2 . reset clears mask[4:0]. table 8-2. mask encoding mask[4:0] masked priority levels decimal binary 0 00000 0 1 00001 1 ? 0 2 00010 2 ? 0 3 00011 3 ? 0 31 11111 31 ? 0 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . interrupt controller module memory map and registers mmc2114 MMC2113 mmc2112 ? rev. 1.0 advance information motorola interrupt controller module 183 8.7.2.2 interrupt status register the 16-bit, read-only interrupt status register (isr) reflects the state of the interrupt controller outputs to the cpu. writes to this register have no effect and are terminated normally. int ? normal interrupt request flag the read-only int flag indicates whether the normal interrupt request signal to the cpu is asserted or negated. reset clears int. 1 = normal interrupt request asserted 0 = normal interrupt request negated fint ? fast interrupt request flag the read-only fint flag indicates whether the fast interrupt request signal to the cpu is asserted or negated. reset clears fint. 1 = fast interrupt request asserted 0 = fast interrupt request negated vec[6:0] ? interrupt vector number field the read-only vec[6:0] field contains the 7-bit interrupt vector number (see table 8-5 ). reset clears vec[6:0]. address: 0x00c5_0002 and 0x00c5_0003 bit 15 14 13 12 11 10 9 bit 8 read: 0 0 0000intfint write: reset:00000000 bit 7654321bit 0 read: 0 vec6 vec5 vec4 vec3 vec2 vec1 vec0 write: reset:00000000 = writes have no effect and the access terminates without a transfer error exception. figure 8-3. interrupt status register (isr) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . advance information mmc2114 MMC2113 mmc2112 ? rev. 1.0 184 interrupt controller module motorola interrupt controller module 8.7.2.3 interrupt force registers the two 32-bit read/write interrupt force registers (ifrh and ifrl) individually force interrupt source requests. address: 0x00c5_0004 through 0x00c5_0007 bit 31 30 29 28 27 26 25 bit 24 read: 0 0 000000 write: reset:00000000 bit 23 22 21 20 19 18 17 bit 16 read: 0 0 000000 write: reset:00000000 bit 15 14 13 12 11 10 9 bit 8 read: 0 0 000000 write: reset:00000000 bit 7654321bit 0 read: if39 if38 if37 if36 if35 if34 if33 if32 write: reset:00000000 = writes have no effect and the access terminates without a transfer error exception. figure 8-4. interrupt force register high (ifrh) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . interrupt controller module memory map and registers mmc2114 MMC2113 mmc2112 ? rev. 1.0 advance information motorola interrupt controller module 185 if[39:0] ? interrupt force field this read/write field forces interrupt requests at the corresponding source numbers. reference table 8-6 for interrupt source numbers to determine which bit(s) to set in this register. ifrh and ifrl allow software generation of interrupt requests for functional or debug purposes. writing 0 to an if bit negates the interrupt request. reset clears the if[39:0] field. 1 = force interrupt request 0 = interrupt source not forced address: 0x00c5_0008 through 0x00c5_000b bit 31 30 29 28 27 26 25 bit 24 read: if31 if30 if29 if28 if27 if26 if25 if24 write: reset:00000000 bit 23 22 21 20 19 18 17 bit 16 read: if23 if22 if21 if20 if19 if18 if17 if16 write: reset:00000000 bit 15 14 13 12 11 10 9 bit 8 read: if15 if14 if13 if12 if11 if10 if9 if8 write: reset:00000000 bit 7654321bit 0 read: if7 if6 if5 if4 if3 if2 if1 if0 write: reset:00000000 figure 8-5. interrupt force register low (ifrl) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . advance information mmc2114 MMC2113 mmc2112 ? rev. 1.0 186 interrupt controller module motorola interrupt controller module 8.7.2.4 interrupt pending register the 32-bit, read-only interrupt pending register (ipr) reflects any currently pending interrupts which are assigned to each priority level. writes to this register have no effect and are terminated normally. ip[31:0] ? interrupt pending field a read-only ipx bit is set when at least one interrupt request is asserted at priority level x. reset clears ip[31:0]. 1 = at least one interrupt request asserted at priority level x 0 = all interrupt requests at level x negated address: 0x00c5_000c through 0x00c5_000f bit 31 30 29 28 27 26 25 bit 24 read: ip31 ip30 ip29 ip28 ip27 ip26 ip25 ip24 write: reset:00000000 bit 23 22 21 20 19 18 17 bit 16 read: ip23 ip22 ip21 ip20 ip19 ip18 ip17 ip16 write: reset:00000000 bit 15 14 13 12 11 10 9 bit 8 read: ip15 ip14 ip13 ip12 ip11 ip10 ip9 ip8 write: reset:00000000 bit 7654321bit 0 read: ip7 ip6 ip5 ip4 ip3 ip2 ip1 ip0 write: reset:00000000 = writes have no effect and the access terminates without a transfer error exception. figure 8-6. interrupt pending register (ipr) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . interrupt controller module memory map and registers mmc2114 MMC2113 mmc2112 ? rev. 1.0 advance information motorola interrupt controller module 187 8.7.2.5 normal interrupt enable register the read/write, 32-bit normal interrupt enable register (nier) individually enables any current pending interrupts which are assigned to each priority level as a normal interrupt source. enabling an interrupt source which has an asserted request causes that request to become pending, and a request to the cpu is asserted if not already outstanding. nie[31:0] ? normal interrupt enable field the read/write nie[31:0] field enables interrupt requests from sources at the corresponding priority level as normal interrupt requests. reset clears nie[31:0]. 1 = normal interrupt request enabled 0 = normal interrupt request disabled address: 0x00c5_0010 through 0x00c5_0013 bit 31 30 29 28 27 26 25 bit 24 read: nie31 nie30 nie29 nie28 nie27 nie26 nie25 nie24 write: reset:00000000 bit 23 22 21 20 19 18 17 bit 16 read: nie23 nie22 nie21 nie20 nie19 nie18 nie17 nie16 write: reset:00000000 bit 15 14 13 12 11 10 9 bit 8 read: nie15 nie14 nie13 nie12 nie11 nie10 nie9 nie8 write: reset:00000000 bit 7654321bit 0 read: nie7 nie6 nie5 nie4 nie3 nie2 nie1 nie0 write: reset:00000000 figure 8-7. normal interrupt enable register (nier) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . advance information mmc2114 MMC2113 mmc2112 ? rev. 1.0 188 interrupt controller module motorola interrupt controller module 8.7.2.6 normal interrupt pending register the read-only, 32-bit normal interrupt pending register (nipr) reflects any currently pending normal interrupts which are assigned to each priority level. writes to this register have no effect and are terminated normally. nip[31:0] ? normal interrupt pending field a read-only nipx bit is set when at least one normal interrupt request is asserted at priority level x. reset clears nip[31:0]. 1 = at least one normal interrupt request asserted at priority level x 0 = all normal interrupt requests at priority level x negated address: 0x00c5_0014 through 0x00c5_0017 bit 31 30 29 28 27 26 25 bit 24 read: nip31 nip30 nip29 nip28 nip27 nip26 nip25 nip24 write: reset:00000000 bit 23 22 21 20 19 18 17 bit 16 read: nip23 nip22 nip21 nip20 nip19 nip18 nip17 nip16 write: reset:00000000 bit 15 14 13 12 11 10 9 bit 8 read: nip15 nip14 nip13 nip12 nip11 nip10 nip9 nip8 write: reset:00000000 bit 7654321bit 0 read: nip7 nip6 nip5 nip4 nip3 nip2 nip1 nip0 write: reset:00000000 = writes have no effect and the access terminates without a transfer error exception. figure 8-8. normal interrupt pending register (nipr) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . interrupt controller module memory map and registers mmc2114 MMC2113 mmc2112 ? rev. 1.0 advance information motorola interrupt controller module 189 8.7.2.7 fast interrupt enable register the read/write, 32-bit fast interrupt enable register (fier) enables any current pending interrupts which are assigned at each priority level as a fast interrupt source. enabling an interrupt source which has an asserted request causes that interrupt to become pending, and a request to the cpu is asserted if not already outstanding. fie[31:0] ? fast interrupt enable field the read/write fie[31:0] field enables interrupt requests from sources at the corresponding priority level as fast interrupts. reset clears fie[31:0]. 1 = fast interrupt enabled 0 = fast interrupt disabled address: 0x00c5_0018 through 0x00c5_001b bit 31 30 29 28 27 26 25 bit 24 read: fie31 fie30 fie29 fie28 fie27 fie26 fie25 fie24 write: reset:00000000 bit 23 22 21 20 19 18 17 bit 16 read: fie23 fie22 fie21 fie20 fie19 fie18 fie17 fie16 write: reset:00000000 bit 15 14 13 12 11 10 9 bit 8 read: fie15 fie14 fie13 fie12 fie11 fie10 fie9 fie8 write: reset:00000000 bit 7654321bit 0 read: fie7 fie6 fie5 fie4 fie3 fie2 fie1 fie0 write: reset:00000000 figure 8-9. fast interrupt enable register (fier) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . advance information mmc2114 MMC2113 mmc2112 ? rev. 1.0 190 interrupt controller module motorola interrupt controller module 8.7.2.8 fast interrupt pending register the read-only, 32-bit fast interrupt pending register (fipr) reflects any currently pending fast interrupts which are assigned to each priority level. writes to this register have no effect and are terminated normally. fip[31:0] ? fast interrupt pending field a read-only fip[x] bit is set when at least one interrupt request at priority level x is pending and enabled as a fast interrupt. reset clears fip[31:0]. 1 = at least one fast interrupt request asserted at priority level x 0 = any fast interrupt requests at priority level x negated address: 0x00c5_001c through 0x00c5_001f bit 31 30 29 28 27 26 25 bit 24 read: fip31 fip30 fip29 fip28 fip27 fip26 fip25 fip24 write: reset:00000000 bit 23 22 21 20 19 18 17 bit 16 read: fip23 fip22 fip21 fip20 fip19 fip18 fip17 fip16 write: reset:00000000 bit 15 14 13 12 11 10 9 bit 8 read: fip15 fip14 fip13 fip12 fip11 fip10 fip9 fip8 write: reset:00000000 bit 7654321bit 0 read: fip7 fip6 fip5 fip4 fip3 fip2 fip1 fip0 write: reset:00000000 = writes have no effect and the access terminates without a transfer error exception. figure 8-10. fast interrupt pending register (fipr) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . interrupt controller module functional description mmc2114 MMC2113 mmc2112 ? rev. 1.0 advance information motorola interrupt controller module 191 8.7.2.9 priority level select registers the read/write 8-bit priority level select registers (plsrx) are 40 read/write, 8-bit priority level select registers plsr0 ? plsr39, one for each of the interrupt source. the plsrx register assigns a priority level to interrupt source x. pls[4:0] ? priority level select field the pls[4:0] field assigns a priority level from 0 to 31 to the corresponding interrupt source. reset clears pls[4:0]. 8.8 functional description the interrupt controller collects interrupt requests from multiple interrupt sources and provides an interface to the cpu interrupt logic. interrupt controller functions include: interrupt source prioritization fast and normal interrupt requests autovectored and vectored interrupt requests interrupt configuration address: 0x00c5_0040 through 0x00c5_0067 bit 7654321bit 0 read: 0 0 0 pls4 pls3 pls2 pls1 pls0 write: reset:00000000 = writes have no effect and the access terminates without a transfer error exception. figure 8-11. priority level select registers (plsr0 ? plsr39) table 8-3. priority select encoding pls[4:0] priority level vector number 00000 0 (lowest) 00000 00001 ? 11110 1 ? 30 00001 ? 11110 11111 31 (hi ghest) 11111 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . advance information mmc2114 MMC2113 mmc2112 ? rev. 1.0 192 interrupt controller module motorola interrupt controller module 8.8.1 interrupt sources and prioritization each interrupt source in the system sends a unique signal to the interrupt controller. up to 40 interrupt sources are supported. each interrupt source can be programmed to one of 32 priority levels by programing the pls bits of the plsr in the interrupt controller. the highest priority level is 31 and lowest priority level is 0. by default, each interrupt source is assigned to the priority level 0. each interrupt source is associated with a 5-bit priority level select value that selects one of 32 priority levels. the interrupt controller uses the priority levels as the basis for the generation of all interrupt signals to the cpu. interrupt requests may be forced by software by writing to ifrh and ifrl. each bit of ifrh and ifrl is logically ored with the corresponding interrupt source signal before the priority level select logic. to negate the forced interrupt request, the interrupt handler can clear the appropriate ifr bit. ipr reflects the state of each priority level. 8.8.2 fast and normal interrupt requests fier allows individual enabling or masking of pending fast interrupt requests. fier is logically anded with ipr, and the result is stored in fipr. fipr bits are bit-wise ored together and inverted to form the fast interrupt signal routed to the cpu (see figure 8-1 ). the fipr allows software to quickly determine the highest priority pending fast interrupt. the output of fipr also feeds into a 32-to-5 priority encoder to generate the vector number to present to the cpu if vectored interrupts are required. nier allows individual enabling or masking of pending normal interrupt requests. nier is logically anded with ipr, and the result is stored in nipr. nipr bits are bit-wise ored together and inverted to form the normal interrupt signal routed to the cpu. the normal interrupt signal is only asserted if the fast interrupt signal is negated. the nipr allows software to quickly determine the highest priority pending normal interrupt. the output of nipr also feeds into a 32-to-5 priority encoder to generate the vector number to present to the cpu if vectored interrupts are required. if the fast interrupt signal is asserted, then the vector number is determined by the highest priority fast interrupt. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . interrupt controller module functional description mmc2114 MMC2113 mmc2112 ? rev. 1.0 advance information motorola interrupt controller module 193 if an interrupt is pending at a given priority level and both the corresponding fier and nier bits are set, then both the corresponding fipr and nipr bits are set, assuming these bits are not masked. fast interrupt requests always have priority over normal interrupt requests, even if the normal interrupt request is at a higher priority level than the highest fast interrupt request. if the fast interrupt signal is asserted when the normal interrupt signal is already asserted, then the normal interrupt signal is negated. ipr, nipr, and fipr are read-only. to clear a pending interrupt, the interrupt must be cleared at the source using a special clearing sequence defined by each source. all interrupt sources to the interrupt controller are to be held until recognized and cleared by the interrupt service routine. the interrupt controller does not have any edge-detect logic. edge-triggered interrupt sources are handled at the source module. in icr, the mask[4:0] bits can mask interrupt sources at and below a selected priority level. the mfi bit determines whether the mask applies only to normal interrupts or to fast interrupts with all normal interrupts being masked. the me bit enables interrupt masking. isr reflects the current vector number and the states of the signals to the cpu. the vector number and fast/normal interrupt sources are synchronized before being sent to the cpu. thus, the interrupt controller adds one clock of latency to the interrupt sequence. the fast and normal interrupt raw sources are not synchronized and are used to wake up the cpu during stop mode. 8.8.3 autovectored and vectored interrupt requests the ae bit in icr enables autovectored interrupt requests to the cpu. ae is set by default, and all interrupt requests are autovectored. an interrupt handler may read fipr or nipr to determine the priority of the interrupt source. if multiple interrupt sources share the same priority f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . advance information mmc2114 MMC2113 mmc2112 ? rev. 1.0 194 interrupt controller module motorola interrupt controller module level, then it is up to the interrupt service routine to determine the correct source of the interrupt. if the ae bit is 0, then each interrupt request is presented with a vector number. the low five bits of the vector number (4 ? 0) are determined based on the highest pending priority, with active fast interrupts having priority over active normal interrupts. the remaining two bits (vector bits 5 and 6) are determined based on whether the interrupt request is a fast interrupt and the setting of the fve bit. if fve is set, then a fast interrupt request has a vector number different from that of a normal interrupt request as shown in table 8-4 . if fve is 0, both normal and fast interrupts have the same vector and requests assigned to priority levels 0 ? 31 are mapped to vector numbers 32 ? 63 in the vector table. if fve is 1, normal interrupt requests assigned to priority levels 0 ? 31 are mapped to vector numbers 32 ? 63 and fast interrupt requests assigned to priority levels 0 ? 31 are mapped to vector numbers 64 ? 95 in the vector table. see table 8-5 . table 8-4. fast interrupt vector number fast interrupt fve interrupt vector bits 6:5 no x 01 x0 01 yes 1 10 table 8-5. vector table mapping vector number usage interrupt vector bits 6:5 0 ? 31 fixed exceptions (including autovectors) 00 32 ? 63 normal only (fve = 1) or normal/fast (fve = 0) vectored interrupts 32 = lowest priority 63 = highest priority 01 64 ? 95 fast vectored interrupts (fve = 1) 64 = lowest priority 95 = highest priority 10 96 ? 127 vectored interrupts (not used) 11 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . interrupt controller module functional description mmc2114 MMC2113 mmc2112 ? rev. 1.0 advance information motorola interrupt controller module 195 8.8.4 interrupt configuration after reset, all interrupts are disabled by default. to properly configure the system to handle interrupt requests, configuration must be performed at three levels: cpu interrupt controller local interrupt sources configure the cpu first, the interrupt controller second, and the local interrupt sources last. 8.8.4.1 cpu configuration for fast interrupts, set the fie[x] bit in fier in the cpu. for normal interrupts, set the nie[x] bit. both fie and nie are cleared at reset. note: to allow long latency, multicycle instructions to be interrupted before completion, set the ic bit in the psr. vbr in the cpu defines the base address of the exception vector table. if autovectors are to be used, then initialize the int and fint autovectors (vector numbers 10 and 11, respectively). if vectored interrupts are to be used, then initialize the vectored interrupts (vector numbers 32 ? 63 and/or 64 ? 95). whether 32 or 64 vectors are required depends on whether the fast interrupts share vectors with the normal interrupt sources based on the fve bit in the interrupt controller icr. for each vector number, create an interrupt service routine to service the interrupt, clear the local interrupt flag, and return from the interrupt routine. 8.8.4.2 interrupt controller configuration by default, each interrupt source to the interrupt controller is assigned a priority level of 0 and disabled. each interrupt source can be programmed to one of 32 priority levels and enabled as either a fast or normal interrupt source. also, the fve and ae bits in icr can be programmed to select autovectored/vectored interrupts and also f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . advance information mmc2114 MMC2113 mmc2112 ? rev. 1.0 196 interrupt controller module motorola interrupt controller module determine if the fast interrupt vector number is to be separate from the normal interrupt vector. 8.8.4.3 interrupt source configuration each module that is capable of generating an interrupt request has an interrupt request enable/disable bit. to allow the interrupt source to be asserted, set the local interrupt enable bit. once an interrupt request is asserted, the module keeps the source asserted until the interrupt service routine performs a special sequence to clear the interrupt flag. clearing the flag negates the interrupt request. 8.8.5 interrupts the interrupt controller assigns a number to each interrupt source, as table 8-6 shows. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . interrupt controller module functional description mmc2114 MMC2113 mmc2112 ? rev. 1.0 advance information motorola interrupt controller module 197 table 8-6. interrupt source assignment source module flag source description flag clearing mechanism 0 adc pf1 queue 1 conversion pause write pf1 = 0 after reading pf1 = 1 1 cf1 queue 1 conversion complete write cf1 = 0 after reading cf1 = 1 2 pf2 queue 2 conversion pause write pf2 = 0 after reading pf2 = 1 3 cf2 queue 2 conversion complete write cf2 = 0 after reading cf2 = 1 4 spi modf mode fault write to spicr1 after reading modf = 1 5 spif transfer complete access spidr after reading spif = 1 6 sci1 tdre transmit data register empty write scidrl after reading tdre = 1 7 tc transmit complete write scidrl after reading tc = 1 8 rdrf receive data register full read scidrl after reading rdrf = 1 9 or receiver overrun read scidrl after reading or = 1 10 idle receiver line idle read scidrl after reading idle = 1 11 sci2 tdre transmit data register empty write scidrl after reading tdre = 1 12 tc transmit complete write scidrl after reading tc = 1 13 rdrf receive data register full read scidrl after reading rdrf = 1 14 or receiver overrun read scidrl after reading or = 1 15 idle receiver line idle read scidrl after reading idle = 1 16 tim1 c0f timer channel 0 write c0f = 1 or access ic/oc if tffca = 1 17 c1f timer channel 1 write 1 to c1f or access ic/oc if tffca = 1 18 c2f timer channel 2 write 1 to c2f or access ic/oc if tffca = 1 19 c3f timer channel 3 write 1 to c3f or access ic/oc if tffca = 1 20 tof timer overflow write tof = 1 or access timcnth/l if tffca = 1 21 paif pulse accumulator input write paif = 1 or access pac if tffca = 1 22 paovf pulse accumulator overflow write paovf = 1 or access pac if tffca = 1 continued on next page f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . advance information mmc2114 MMC2113 mmc2112 ? rev. 1.0 198 interrupt controller module motorola interrupt controller module 23 tim2 c0f timer channel 0 write c0f = 1 or access ic/oc if tffca = 1 24 c1f timer channel 1 write c1f = 1 or access ic/oc if tffca = 1 25 c2f timer channel 2 write c2f = 1 or access ic/oc if tffca = 1 26 c3f timer channel 3 write c3f = 1 or access ic/oc if tffca = 1 27 tof timer overflow write tof = 1 or access timcnth/l if tffca = 1 28 paif pulse accumulator input write paif = 1 or access pac if tffca = 1 29 paovf pulse accumulator overflow write paovf = 1 or access pac if tffca = 1 30 pit1 pif pit interrupt flag write pif = 1 or write pmr 31 pit2 pif pit interrupt flag write pif = 1 or write pmr 32 eport/ pmm (1) epf0/ lvdf edge port flag 0/lvd write epf0 = 1/write lvdf = 1 33 eport/ sgfm (2) epf1 cbeif/ ccif edge port flag 1/sgfm buffer empty/sgfm command complete write epf1 = 1/write cbeif = 1; ccif cleared automatically 34 eport epf2 edge port flag 2 write epf2 = 1 35 epf3 edge port flag 3 write epf3 = 1 36 epf4 edge port flag 4 write epf4 = 1 37 epf5 edge port flag 5 write epf5 = 1 38 epf6 edge port flag 6 write epf6 = 1 39 epf7 edge port flag 7 write epf7 = 1 1. interrupt source 32 is shared by int0 of the eport and low voltage detect (lvd) of the power management module (pmm), a sub-module of the reset mode (see section 5. reset controller module ). 2. interrupt source 33 is shared by int1 of the eport and two interrupts from the second generation flash for m core (sgfm) module. see 10.7.2.5 sgfm user status register for a description of the flags set when these two interrupts occur. table 8-6. interrupt source assignment (continued) source module flag source description flag clearing mechanism f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . mmc2114 MMC2113 mmc2112 ? rev. 1.0 advance information motorola static random access memory (sram) 199 advance information ? mmc2114, MMC2113, and mmc2112 section 9. static random access memory (sram) 9.1 contents 9.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .199 9.3 modes of operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .200 9.4 low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .200 9.5 standby power supply pin (v stby ) . . . . . . . . . . . . . . . . . . . .200 9.6 standby operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .200 9.7 reset operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .201 9.8 interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .201 9.2 introduction features of the static random access memory (sram) include: on-chip 8-kbyte sram (MMC2113) or on-chip 32-kbyte sram (mc2112 and mmc2114) fixed address space byte, half-word (16-bit), or word (32-bit) read/write accesses one clock per access (including bytes, half-words, and words) supervisor or user mode access standby power supply switch to support an external power supply f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . advance information mmc2114 MMC2113 mmc2112 ? rev. 1.0 200 static random access memory (sram) motorola static random access memory (sram) 9.3 modes of operation access to the sram is not restricted in any way. the array can be accessed in supervisor and user modes. note: the MMC2113 may contain more than 8k of internal sram, but only the 8k range from 0x0080_0000 to 0x0080_1fff is tested and guaranteed to be operational. it is recommended that internal sram outside this range not be used. accesses to sram outside this range terminate without a transfer error exception. 9.4 low-power modes in wait, doze, and stop modes, clocks to the sram are disabled. no recovery time is required when exiting these modes. 9.5 standby power supply pin (v stby ) the standby power supply pin (v stby ) provides standby voltage to the sram array if v dd is lost. v stby is isolated from all other v dd nodes. 9.6 standby operation when the chip is powered down, the contents of the sram array are maintained by the standby power supply, v stby . if the standby voltage falls below the minimum required voltage, the sram contents may be corrupted. the sram automatically switches to standby operation with no loss of data when the voltage on v dd is below the voltage on v stby . in standby mode, the sram does not respond to any bus cycles. unexpected operation may occur if the central processor unit (cpu) requests data from the sram in standby mode. if standby operation is not needed, then the v stby pin should be connected to v dd . the current on v stby may exceed its specified maximum value at some time during the transition time during which v dd is at or below the voltage switch threshold to a threshold above v ss . if the standby power supply cannot provide enough current to maintain v stby above the f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . static random access memory (sram) reset operation mmc2114 MMC2113 mmc2112 ? rev. 1.0 advance information motorola static random access memory (sram) 201 required minimum value, then a capacitor must be provided from v stby to v ss . the value of the capacitor, c, can be calculated as: where: i is the difference between the transition current requirement and the maximum power supply current, t is the duration of the v dd transition near the voltage switch threshold, and v is the difference between the minimum available supply voltage and the required minimum v stby voltage. 9.7 reset operation the sram contents are undefined immediately following a power-on reset. sram contents are unaffected by system reset. if a synchronous reset occurs during a read or write access, then the access completes normally and any pipelined access in progress is stopped without corruption of the sram contents. 9.8 interrupts the sram module does not generate interrupt requests. ci t v --- - = f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . advance information mmc2114 MMC2113 mmc2112 ? rev. 1.0 202 static random access memory (sram) motorola static random access memory (sram) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . mmc2114 MMC2113 mmc2112 ? rev. 1.0 advance information motorola second generation flash for m core (sgfm) 203 advance information ? mmc2114, MMC2113, and mmc2112 section 10. second generation flash for m core (sgfm) 10.1 contents 10.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .204 10.3 glossary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .205 10.4 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .206 10.5 modes of operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .206 10.6 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .207 10.7 module memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .209 10.7.1 unbanked register descriptions . . . . . . . . . . . . . . . . . . . .213 10.7.1.1 sgfm configuration register . . . . . . . . . . . . . . . . . . . .213 10.7.1.2 sgfm clock divider register . . . . . . . . . . . . . . . . . . . . 215 10.7.1.3 sgfm test register . . . . . . . . . . . . . . . . . . . . . . . . . . .216 10.7.1.4 sgfm security register . . . . . . . . . . . . . . . . . . . . . . . .217 10.7.1.5 sgfm monitor data register. . . . . . . . . . . . . . . . . . . . .219 10.7.2 banked register descriptions . . . . . . . . . . . . . . . . . . . . . .220 10.7.2.1 sgfm protection register . . . . . . . . . . . . . . . . . . . . . . .220 10.7.2.2 sgfm supervisor access register . . . . . . . . . . . . . . . .222 10.7.2.3 sgfm data access register . . . . . . . . . . . . . . . . . . . . .223 10.7.2.4 sgfm test status register . . . . . . . . . . . . . . . . . . . . . .224 10.7.2.5 sgfm user status register. . . . . . . . . . . . . . . . . . . . . .224 10.7.2.6 sgfm command register. . . . . . . . . . . . . . . . . . . . . . .226 10.7.2.7 sgfm control register . . . . . . . . . . . . . . . . . . . . . . . . . 227 10.7.2.8 sgfm address register . . . . . . . . . . . . . . . . . . . . . . . .228 10.7.2.9 sgfm data register . . . . . . . . . . . . . . . . . . . . . . . . . . .229 10.8 sgfm user mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .230 10.8.1 read operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .230 10.8.2 write operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .230 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . advance information mmc2114 MMC2113 mmc2112 ? rev. 1.0 204 second generation flash for m core (sgfm) motorola second generation flash for m core (sgfm) 10.8.3 program and erase operations . . . . . . . . . . . . . . . . . . . . .231 10.8.3.1 setting the sgfmclkd register. . . . . . . . . . . . . . . . . .231 10.8.3.2 program, erase, and verify sequences. . . . . . . . . . . . .232 10.8.3.3 flash user mode valid commands. . . . . . . . . . . . . . .234 10.8.3.4 flash user mode illegal operations . . . . . . . . . . . . . .236 10.8.4 stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .237 10.8.5 master mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .238 10.8.6 emulation mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .238 10.8.7 debug mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .238 10.9 flash security operation . . . . . . . . . . . . . . . . . . . . . . . . . . .238 10.9.1 back door access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 239 10.9.2 erase verify check. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .239 10.10 resets. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .240 10.11 interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .240 10.2 introduction the second generation flash for m core (sgfm) is constructed with building blocks of 32,768 by 16 bits that can be used to generate 128-, 256-, 384- and 512-kbyte electrically erasable and programmable read-only memory arrays using two, four, six, and eight blocks respectively. the sgfm is ideal for program and data storage for single-chip applications and allows for field reprogramming without external high-voltage sources. the voltages required to program and erase the flash is generated internally by on-chip charge pumps. program and erase operations are performed under cpu control through a command driven interface to an internal state machine. all flash physical blocks can be programmed or erased at the same time; however, it is not possible to read from a flash physical block while the same block is being programmed or erased. for 256-kbyte and larger arrays, it is possible to program or erase one pair of flash physical blocks under the control of software routines executing out of another pair. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . second generation flash for m core (sgfm) glossary mmc2114 MMC2113 mmc2112 ? rev. 1.0 advance information motorola second generation flash for m core (sgfm) 205 10.3 glossary sgfm ? second generation flash for m core. acronym used throughout this document to reference this module. sgfm module ? includes the bus interface, command controller, built-in self test (bist) controller, and the flash physical blocks. flash physical block ? a 64-kbyte flash hard block organized as 32,768 halfwords (32k x 16 bits) that includes high voltage generation and parametric test features. flash logical sector ? an 8-kbyte sector of contiguous flash memory that can be protected from program and erase operations. a logical sector can have supervisor/user and program/data space access restrictions. flash erase page ? eight rows of 64 bytes (512 bytes) in one flash physical block. two pages, one from each interleaving physical block, are erased at one time. banked register ? a register that operates on two interleaved flash physical blocks. banked registers share the same control register addresses as the equivalent registers for the other flash physical blocks. the active register bank is selected by a bank select field in the unbanked register space. the sgfm module contains one to four sets of banked registers depending on the size of the array. unbanked register ? a register which operates upon all flash physical blocks. command sequence ? a three step sequence to program, erase, or verify the flash. flash user mode ? the mode in which the flash module operates when executing user code and software controlled program and erase operations. sato ? acronym used for sense amplifier timeout analog hard-macro block. the sato saves power at low system clock frequencies by limiting the time during which sense amps are enabled. erased state ? bit state that reads as a 1. programmed state ? bit state that reads as a 0. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . advance information mmc2114 MMC2113 mmc2112 ? rev. 1.0 206 second generation flash for m core (sgfm) motorola second generation flash for m core (sgfm) 10.4 features features of the sgfm include: 128- (MMC2113), 256- (mmc2114), 384-, or 512-kbytes of flash memory 33 mhz single cycle reads of bytes, aligned halfwords (16 bits), and aligned words (32 bits) automated program and erase operation concurrent verify, program, and erase of all array blocks read-while-write capability for 256-kbyte and larger arrays optional interrupt on command completion flexible scheme for protection against accidental program or erase operations access restriction controls for both supervisor/user and data/program space operations security for single-chip applications single power supply (system v dd ) used for all module operations auto sense amplifier timeout for low-power, low-frequency read operations 10.5 modes of operation the sgfm has two operating modes: 1. flash user mode ? in this mode, the sgfm is used for non-volatile program and data storage. flash program and erase operations are controlled by user software. 2. flash test mode ? this is used at the factory only to test the sgfm. refer to 10.8 sgfm user mode for a description of flash user mode operations. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . second generation flash for m core (sgfm) block diagram mmc2114 MMC2113 mmc2112 ? rev. 1.0 advance information motorola second generation flash for m core (sgfm) 207 10.6 block diagram the sgfm module shown in figure 10-1 contains the flash physical blocks, the m core local bus (mlb) and ip bus interfaces, flash interface, register blocks, and the bist engine. each 64-kbyte flash physical block is arranged as 32,768 halfwords (16 bits) and may be read as either bytes or aligned halfwords. aligned word access is provided by concatenating the outputs of two flash physical blocks. reads of bytes, aligned halfwords, and aligned words require one clock cycle. misaligned read accesses are not supported and will result in a cycle termination transfer error. all flash program, erase, and verify commands operate on adjacent flash physical blocks and are initiated with a single aligned 32-bit write to the appropriate array location. any other write operation will cause a cycle termination transfer error. for erase purposes, a flash physical block is organized as 1024 rows of 64 bytes with a single erase page consisting of 8 rows (512 bytes). page erase operates simultaneously on two interleaving erase pages in adjacent flash physical blocks, making the minimum effective erase size 1 kbyte. mass erase operates simultaneously on two adjacent flash physical blocks in their entirety and erases a total of 128 kbytes of array space. each pair of flash physical blocks requires a banked set of registers to control program and erase operations. figure 10-1 shows a 512-kbyte module configured with four sets of banked registers. a 128 k-byte module would only require one set, a 256-kbyte module would require two sets and a 384-kbyte module would require three sets of banked registers. an erased flash bit reads 1 and a programmed flash bit reads 0. the sgfm features a sense amplifier timeout block that automatically reduces current consumption during reads at low clock frequencies. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . advance information mmc2114 MMC2113 mmc2112 ? rev. 1.0 208 second generation flash for m core (sgfm) motorola second generation flash for m core (sgfm) figure 10-1. sgfm module block diagram flash interface ip bus interface mlb interface d[31:16] d[15:0] d[31:16] d[15:0] sato sato sato sato v ssf v ddf bist engine control register bank 0 control register bank 3 common registers m core local bus (mlb) block 0h 32 k x 16 block 0l 32 k x 16 block 3h 32 k x 16 block 3l 32 k x 16 ip bus f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . second generation flash for m core (sgfm) module memory map mmc2114 MMC2113 mmc2112 ? rev. 1.0 advance information motorola second generation flash for m core (sgfm) 209 10.7 module memory map the sgfm memory array is mapped starting at address 0x0000_0000. figure 10-2 shows how multiple 32,768 by 16-bit flash physical blocks interleave to form a contiguous non-volatile memory space. each pair of blocks (upper and lower) interleave every 2 bytes to form 128 kbytes of memory. figure 10-2. sgfm array memory map 0x0000_0000 0x0007_ffff 0x0002_0000 block 0h (2bytes) block 0l (2bytes) block 0h (2bytes) block 0l (2bytes) block 1h (2bytes) block 1l (2bytes) block 1h (2bytes) block 1l (2bytes) block 2h (2bytes) block 2l (2bytes) block 2h (2bytes) block 2l (2bytes) block 3h (2bytes) block 3l (2bytes) block 3h (2bytes) block 3l (2bytes) 0x0004_0000 0x0006_0000 128 kbytes configuration field (0x0000_0200 ? 0x0000_022b) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . advance information mmc2114 MMC2113 mmc2112 ? rev. 1.0 210 second generation flash for m core (sgfm) motorola second generation flash for m core (sgfm) the sgfm module has hardware interlocks to protect data from accidental corruption. the sgfm memory array is logically divided into 8-kbyte sectors for the purpose of data protection and access control. a flexible scheme allows the protection of any combination of logical sectors (see 10.7.2.1 sgfm protection register ). a similar mechanism is available to control supervisor/user and program/data space access to these sectors. the sgfm configuration field comprises 44 bytes of reserved array memory space that determines the module protection and access restrictions out of reset. data to secure the flash from unauthorized access is also stored in the sgfm configuration field. table 10-1 describes each byte used in this field. the sgfm module also contains a set of control and status registers. the memory map for these registers and their accessibility in supervisor and user modes is shown in table 10-2 . the sgfm module contains one to four sets of banked registers depending on the size of the array. the active register bank is selected via the bksel field in the unbanked module configuration register (sgfmcr). each set of banked registers controls the operation of two interleaving flash physical blocks such that block 0l and block 0h are controlled with one register bank. other blocks are controlled in a similar fashion as shown in figure 10-2 . f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . second generation flash for m core (sgfm) module memory map mmc2114 MMC2113 mmc2112 ? rev. 1.0 advance information motorola second generation flash for m core (sgfm) 211 table 10-1. sgfm configuration field address size in bytes description 0x0000_0200 ? 0x0000_0207 8 back door comparison key 0x0000_0208 ? 0x0000_0209 2 flash program/erase sector protection blocks 0h/0l (see 10.7.2.1 sgfm protection register ) 0x0000_020a ? 0x0000_020b 2 reserved 0x0000_020c ? 0x0000_020d 2 flash supervisor/user space restrictions blocks 0h/0l (see 10.7.2.2 sgfm supervisor access register ) 0x0000_020e ? 0x0000_020f 2 flash program/data space restrictions blocks 0h/0l (see 10.7.2.3 sgfm data access register ) 0x0000_0210 ? 0x0000_0211 2 flash program/erase sector protection (1) blocks 1h/1l (see 10.7.2.1 sgfm protection register ) 0x0000_0212 ? 0x0000_0213 2 reserved 0x0000_0214 ? 0x0000_0215 2 flash supervisor/user space restrictions (1) blocks 1h/1l (see 10.7.2.2 sgfm supervisor access register ) 0x0000_0216 ? 0x0000_0217 2 flash program/data space restrictions (1) blocks 1h/1l (see 10.7.2.3 sgfm data access register ) 0x0000_0218 ? 0x0000_0219 2 flash program/erase sector protection (2) blocks 2h/2l (see 10.7.2.1 sgfm protection register ) 0x0000_021a ? 0x0000_021b 2 reserved 0x0000_021c ? 0x0000_021d 2 flash supervisor/user space restrictions (2) blocks 2h/2l (see 10.7.2.2 sgfm supervisor access register ) 0x0000_021e ? 0x0000_021f 2 flash program/data space restrictions (2) blocks 2h/2l (see 10.7.2.3 sgfm data access register ) 0x0000_021e ? 0x0000_0221 2 flash program/erase sector protection (3) blocks 3h/3l (see 10.7.2.1 sgfm protection register ) 0x0000_0222 ? 0x0000_0223 2 reserved 0x0000_0224 ? 0x0000_0225 2 flash supervisor/user space restrictions (3) blocks 3h/3l (see 10.7.2.2 sgfm supervisor access register ) 0x0000_0226 ? 0x0000_0227 2 flash program/data space restrictions (3) blocks 3h/3l (see 10.7.2.3 sgfm data access register ) 0x0000_0228 ? 0x0000_022b 4 flash security word (see 10.7.1.4 sgfm security register ) 1. these configuration bytes are only required for 256-kbyte arrays and larger. 2. these configuration bytes are only required for 384-kbyte arrays and larger. 3. these configuration bytes are only required for 512-kbyte arrays. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . advance information mmc2114 MMC2113 mmc2112 ? rev. 1.0 212 second generation flash for m core (sgfm) motorola second generation flash for m core (sgfm) table 10-2. sgfm register address map address bits 31 ? 24 bits 23 ? 16 bits 15 ? 8bits 7 ? 0 access (1) banked register 0x00d0_0000 sgfmcr sgfmclkd reserved (2) sno 0x00d0_0004 sgfmtst reserved (2) sno 0x00d0_0008 sgfmsec s no 0x00d0_000c sgfmmntr s no 0x00d0_0010 sgfmprot reserved (2) syes 0x00d0_0014 sgfmsacc sgfmdacc s yes 0x00d0_0018 sgfmtstat reserved (2) syes 0x00d0_001c sgfmustat reserved (2) syes 0x00d0_0020 sgfmcmd reserved (2) syes 0x00d0_0024 sgfmctl sgfmadr s yes 0x00d0_0028 sgfmdata s yes 0x00d0_002c ? 0x00d0_003c unimplemented (3) ? yes 1. s = supervisor access only. user mode accesses to supervisor only addresses have no effect and result in a cycle termi- nation transfer error. 2. writes to reserved address locations have no effect and reads return 0s. 3. accesses to unimplemented addresses have no effect and result in a cycle termination transfer error. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . second generation flash for m core (sgfm) module memory map mmc2114 MMC2113 mmc2112 ? rev. 1.0 advance information motorola second generation flash for m core (sgfm) 213 10.7.1 unbanked register descriptions the unbanked registers are described in this subsection. 10.7.1.1 sgfm configuration register the sgfm configuration register (sgfmcr) is unbanked and is used to configure and control the operation of the sgfm array and bus interface unit (biu). frz ? freeze enable bit the frz bit is readable and writable in all modes. in debug mode the sgfm behaves exactly as it does in user mode except that the lock bit in sgfmcr and sgfmclkd[6:0] bits are writable. 1 = enter debug mode if debug signal on mlb is asserted 0 = ignore debug mode if debug signal on mlb is asserted eme ? emulation enable bit the eme bit is always readable and only writable when lock = 0. eme places the sgfm in emulation mode, during which the sgfm biu will not assert ta or tea to terminate read bus cycles of the address: 0x00d0_0000 and 0x00d0_0001 bit 15 14 13 12 11 10 9 bit 8 read: 0 frz 0 eme 0 lock 00 write: reset:000note 10000 bit 7654321bit 0 read: cbeie ccie keyacc 000 bksel1 bksel0 write: reset:00000000 = reserved note 1. reset state determined by chip reset configuration. figure 10-3. sgfm module configuration register (sgfmcr) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . advance information mmc2114 MMC2113 mmc2112 ? rev. 1.0 214 second generation flash for m core (sgfm) motorola second generation flash for m core (sgfm) sgfm array. instead, external memory that emulates the flash must drive the data bus, and the ebi emulation chip select mechanism terminates the bus cycle instead of the sgfm. note: in emulation mode, writes to the sgfm array will generate an sgfm access error and set the accerr bit (see 10.8.3.4 flash user mode illegal operations ). 1 = emulation mode 0 = user mode lock ? write lock control bit the lock bit is always readable but can only be set once in user mode. in debug or test mode, the lock bit is always writable. 1 = the eme bit, sgfmprot, sgfmsacc, and sgfmdacc registers are write-locked 0 = the eme bit, sgfmprot, sgfmsacc, and sgfmdacc registers are writable cbeie ? command buffer empty interrupt enable bit the cbeie bit is readable and writable in all modes. cbeie enables an interrupt request when the command buffer for the flash physical blocks selected by bksel[1:0] is empty. 1 = request an interrupt whenever the cbeif flag is set. 0 = command buffer empty interrupts disabled ccie ? command complete interrupt enable bit the ccie bit is readable and writable in all modes. ccie enables an interrupt when the command executing for the flash physical blocks selected by bksel[1:0] is complete. 1 = request an interrupt whenever the ccif flag is set. 0 = command complete interrupts disabled keyacc ? enable security key writing bit the keyacc bit is readable in all modes and only writable if the keyen bit in the sgfmsec register is set. 1 = writes to the flash array are interpreted as keys to open the back door. 0 = writes to the flash array are interpreted as the start of a program, erase, or verify sequence. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . second generation flash for m core (sgfm) module memory map mmc2114 MMC2113 mmc2112 ? rev. 1.0 advance information motorola second generation flash for m core (sgfm) 215 bksel[1:0] ? register bank select field the bksel bits are readable and writable in all modes and select which set of bank registers is accessible. table 10-3 shows which set of banked registers is selected by the bksel field depending on the size of the flash memory array. 10.7.1.2 sgfm clock divider register the sgfm clock divider register (sgfmclkd) is unbanked and is used to set the frequency of the clock used for timed events in program and erase algorithms. in user mode, all bits in sgfmclkd are readable while bits 6 ? 0 can only be written once. in test and debug modes, all bits in sgfmclkd are readable and writable at anytime, except bit 7 which is a status-only bit and is not writable in any mode. table 10-3. register bank select decoding bksel[1:0] 128 kbytes 256 kbytes 384 kbytes 512 kbytes 00 bank 0 bank 0 bank 0 bank 0 01 bank 0 bank 1 bank 1 bank 1 10 bank 0 bank 0 bank 2 bank 2 11 bank 0 bank 1 bank 2 bank 3 address: 0x00d0_0002 bit 7654321bit 0 read: divld prdivdiv5div4div3div2div1div0 write: reset:00000000 = reserved figure 10-4. sgfm clock divider register (sgfmclkd) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . advance information mmc2114 MMC2113 mmc2112 ? rev. 1.0 216 second generation flash for m core (sgfm) motorola second generation flash for m core (sgfm) divld ? clock divider loaded bit 1 = sgfmclkd has been written since the last reset. 0 = sgfmclkd has not been written. prdiv8 ? enable prescaler divide by 8 bit 1 = enables a prescaler that divides the sgfm clock by 8 before it enters the sgfmclkd divider. 0 = the sgfm clock is fed directly into the sgfmclkd divider. div[5:0] ? clock divider field the combination of prdiv8 and div[5:0] effectively divides the sgfm input clock down to a frequency between 150 khz and 200 khz. the frequency range of the sgfm clock is 150 khz to 102.4 mhz. note: sgfmclkd must be written with an appropriate value before programming or erasing the flash array. refer to 10.8.3.1 setting the sgfmclkd register . 10.7.1.3 sgfm test register the sgfm test register (sgfmtst) is unbanked and is used only for factory testing. accesses to sgfmtst when not in test mode will result in a cycle termination transfer error. address: 0x00d0_0004 bit 7654321bit 0 read: rsvd7 rsvd6 rsvd5 rsvd4 00 rsvd1 rsvd0 write: reset:00000000 = reserved figure 10-5. sgfm test register (sgfmtst) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . second generation flash for m core (sgfm) module memory map mmc2114 MMC2113 mmc2112 ? rev. 1.0 advance information motorola second generation flash for m core (sgfm) 217 10.7.1.4 sgfm security register the sgfm security register (sgfmsec) is unbanked and controls the flash security features. sgfmsec is readable in all modes but is not writable in any mode. address: 0x00d0_0008 through 0x00d0_000b bit 31 30 29 28 27 26 25 bit 24 read: keyen secstat 000000 write: reset: f (1) note 2000000 bit 23 22 21 20 19 18 17 bit 16 read: 0 0 000000 write: reset:00000000 bit 15 14 13 12 11 10 9 bit 8 read: sec15 sec14 sec13 sec12 sec11 sec10 sec9 sec8 write: reset: f (1) f (1) f (1) f (1) f (1) f (1) f (1) f (1) bit 7654321bit 0 read: sec7 sec6 sec5 sec4 sec3 sec2 sec1 sec0 write: reset: f (1) f (1) f (1) f (1) f (1) f (1) f (1) f (1) = reserved notes: 1. reset state loaded from flash configuration field during reset. 2. reset state determined by security state of module. figure 10-6. sgfm security register (sgfmsec) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . advance information mmc2114 MMC2113 mmc2112 ? rev. 1.0 218 second generation flash for m core (sgfm) motorola second generation flash for m core (sgfm) sgfmsec register bits with a reset state denoted by f in figure 10-6 are loaded from the flash configuration at address 0x0000_0228 during the reset sequence. keyen ? enable back door key to security bit 1 = back door to flash is enabled. 0 = back door to flash is disabled. secstat ? flash security status bit 1 = flash security is enabled 0 = flash security is disabled sec[15:0] ? security field the sec bits define the security state of the device. table 10-4 lists the single code that enables security. the security features of the sgfm are described in 10.9 flash security operation . table 10-4. security states sec[15:0] description $000b flash secured (1) 1. the $000b value was chosen because it represents the m core trap #3 opcode, making it unlikely that compiled code accidentally programmed at the security word in the flash configuration field location would unintentionally secure the device. all other combinations flash unsecured f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . second generation flash for m core (sgfm) module memory map mmc2114 MMC2113 mmc2112 ? rev. 1.0 advance information motorola second generation flash for m core (sgfm) 219 10.7.1.5 sgfm monitor data register the sgfm monitor data register (sgfmmntr) is unbanked and is used only for factory testing. accesses to sgfmmntr when not in test mode will result in a cycle termination transfer error. address: 0x00d0_000c through 0x00d0_000f bit 31 30 29 28 27 26 25 bit 24 read: rsvd31 rsvd30 rsvd29 rsvd28 rsvd27 rsvd26 rsvd25 rsvd24 write: reset: note 1 bit 23 22 21 20 19 18 17 bit 16 read: rsvd23 rsvd22 rsvd21 rsvd20 rsvd19 rsvd18 rsvd17 rsvd16 write: reset: note 1 bit 15 14 13 12 11 10 9 bit 8 read: rsvd15 rsvd14 rsvd13 rsvd12 rsvd11 rsvd10 rsvd9 rsvd8 write: reset: note 1 bit 7654321bit 0 read: rsvd7 rsvd6 rsvd5 rsvd4 rsvd3 rsvd2 rsvd1 rsvd0 write: reset: note 1 = reserved note 1. sgfmmntr does not have a default reset state. figure 10-7. sgfm monitor data register (sgfmmntr) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . advance information mmc2114 MMC2113 mmc2112 ? rev. 1.0 220 second generation flash for m core (sgfm) motorola second generation flash for m core (sgfm) 10.7.2 banked register descriptions the banked registers are described in this subsection. 10.7.2.1 sgfm protection register the sgfm protection register (sgfmprot) is banked and specifies which flash logical sectors are protected from program and erase operations. the sgfmprot register is always readable and only writable when lock = 0. to change which logical sectors are protected on a temporary basis, write sgfmprot with a new value after the lock bit in sgfmcr has been cleared. to change the value of sgfmprot that will be loaded on reset, the protection byte in the flash configuration field must be reprogrammed for the interleaved flash physical blocks currently selected by bksel[1:0]. if necessary, the logical sector containing the flash configuration field must be temporarily unprotected using the method just described before reprogramming the protection bytes. prot[15:0] ? sector protection bits each flash logical sector can be protected from program and erase operations by setting its corresponding prot bit. 1 = logical sector is protected. 0 = logical sector is not protected. address: 0x00d0_0010 and 0x00d0_0011 bit 15 14 13 12 11 10 9 bit 8 read: prot15 prot14 prot13 prot12 prot11 prot10 prot9 prot8 write: reset: f (1) f (1) f (1) f (1) f (1) f (1) f (1) f (1) bit 7654321bit 0 read: prot7 prot6 prot5 prot4 prot3 prot2 prot1 prot0 write: reset: f (1) f (1) f (1) f (1) f (1) f (1) f (1) f (1) note 1. reset state loaded from flash configuration field during reset. figure 10-8. sgfm protection register (sgfmprot) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . second generation flash for m core (sgfm) module memory map mmc2114 MMC2113 mmc2112 ? rev. 1.0 advance information motorola second generation flash for m core (sgfm) 221 each banked sgfmprot register controls the protection of sixteen 8-kbyte flash logical sectors in a 128-kbyte bank of memory (two interleaved flash physical blocks). figure 10-9 shows the association between each bit in the sgfmprot register and its corresponding logical sector. figure 10-9. sgfmprot protection diagram sector 15 sector 14 sector 13 sector 12 sector 11 sector 10 sector 9 sector 8 sector 7 sector 6 sector 5 sector 4 sector 3 sector 2 sector 1 sector 0 sector 15 sector 14 sector 13 sector 12 sector 11 sector 10 sector 9 sector 8 sector 7 sector 6 sector 5 sector 4 sector 3 sector 2 sector 1 sector 0 sector 15 sector 14 sector 13 sector 12 sector 11 sector 10 sector 9 sector 8 sector 7 sector 6 sector 5 sector 4 sector 3 sector 2 sector 1 sector 0 sector 15 sector 14 sector 13 sector 12 sector 11 sector 10 sector 9 sector 8 sector 7 sector 6 sector 5 sector 4 sector 3 sector 2 sector 1 sector 0 prot1 prot0 8-kbyte logical sector 8-kbyte logical sector prot13 prot12 0x0001_e000 0x0001_ffff { { 0x0007_e000 0x0007_ffff 0x0005_e000 0x0005_ffff 0x0003_e000 0x0003_ffff 0x0006_0000 0x0006_2000 0x0004_0000 0x0004_2000 0x0002_0000 0x0002_2000 0x0000_0000 0x0000_2000 bksel[1:0] = %11 bksel[1:0] = %10 bksel[1:0] = %01 bksel[1:0] = %00 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . advance information mmc2114 MMC2113 mmc2112 ? rev. 1.0 222 second generation flash for m core (sgfm) motorola second generation flash for m core (sgfm) 10.7.2.2 sgfm supervisor access register the sgfm supervisor access register (sgfmsacc) is banked and specifies the supervisor/user access permissions of flash logical sectors. supv[15:0] ? supervisor address space assignment bits the supv[15:0] bits are always readable and only writable when lock = 0. each flash logical sector can be mapped into supervisor or unrestricted address space. sgfmsacc uses the same correspondence between logical sectors and register bits as does sgfmprot. see figure 10-9 for details. when a logical sector is mapped into supervisor address space, only cpu supervisor accesses will be allowed. a cpu user access to a location in supervisor address space will result in a cycle termination transfer error. when a logical sector is mapped into unrestricted address space both supervisor and user accesses are allowed. 1 = logical sector is mapped in supervisor address space. 0 = logical sector is mapped in unrestricted address space. address: 0x00d0_0014 and 0x00d0_0015 bit 15 14 13 12 11 10 9 bit 8 read: supv15 supv14 supv13 supv12 supv11 supv10 supv9 supv8 write: reset: f (1) f (1) f (1) f (1) f (1) f (1) f (1) f (1) bit 7654321bit 0 read: supv7 supv6 supv5 supv4 supv3 supv2 supv1 supv0 write: reset: f (1) f (1) f (1) f (1) f (1) f (1) f (1) f (1) note 1. reset state loaded from flash configuration field during reset. figure 10-10. sgfm supervisor access register (sgfmasacc) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . second generation flash for m core (sgfm) module memory map mmc2114 MMC2113 mmc2112 ? rev. 1.0 advance information motorola second generation flash for m core (sgfm) 223 10.7.2.3 sgfm data access register the sgfm data access register (sgfmdacc) is banked and specifies the data/program access permissions of flash logical sectors. data[15:0] ? data address space assignment bits the data[15:0] bits are always readable and only writable when lock = 0. each flash logical sector can be mapped into data or both data and program address space. sgfmdacc uses the same correspondence between logical sectors and register bits as does sgfmprot. see figure 10-9 for details. when a logical sector is mapped into data address space, only cpu data accesses will be allowed. a cpu program access to a location in data address space will result in a cycle termination transfer error. when an array sector is mapped into both data and program address space both data and program accesses are allowed. 1 = logical sector is mapped in data address space. 0 = logical sector is mapped in data and program address space. address: 0x00d0_0016 and 0x00d0_0017 bit 15 14 13 12 11 10 9 bit 8 read: data15 data14 data13 data12 data11 data10 data9 data8 write: reset: f (1) f (1) f (1) f (1) f (1) f (1) f (1) f (1) bit 7654321bit 0 read: data7 data6 data5 data4 data3 data2 data1 data0 write: reset: f (1) f (1) f (1) f (1) f (1) f (1) f (1) f (1) note 1. reset state loaded from flash configuration field during reset. figure 10-11. sgfm data access register (sgfmdacc) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . advance information mmc2114 MMC2113 mmc2112 ? rev. 1.0 224 second generation flash for m core (sgfm) motorola second generation flash for m core (sgfm) 10.7.2.4 sgfm test status register the sgfm test status register (sgfmtstat) is banked and is used only for factory testing. accesses to sgfmstat when not in test mode will result in a cycle termination transfer error. 10.7.2.5 sgfm user status register the sgfm user status register (sgfmustat) is banked reports flash state machine command status, array access errors, protection violations, and blank check status. sgfmustat bits 7, 5, 4, and 2 are readable and writable in all modes. bits 3, 1, and 0 always read 0 and writes have no effect. bit 6 is a read-only bit in all modes. note: only one sgfmtustat bit should be cleared at a time. address: 0x00d0_0018 bit 7654321bit 0 read: 0 0 0 0 rsvd3 0 rsvd1 rsvd0 write: reset:00000000 = reserved figure 10-12. sgfm test status register (sgfmtstat) address: 0x00d0_001c bit 7654321bit 0 read: cbeif ccif pviol accerr 0 blank 00 write: reset:11000000 = reserved figure 10-13. sgfm user status register (sgfmustat) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . second generation flash for m core (sgfm) module memory map mmc2114 MMC2113 mmc2112 ? rev. 1.0 advance information motorola second generation flash for m core (sgfm) 225 cbeif ? command buffer empty interrupt flag the cbeif flag indicates that the command buffer for the interleaved flash physical blocks selected by bksel[1:0] is empty and that a new command sequence can be started. clear cbeif by writing it to 1. writing a 0 to cbeif has no effect but can be used to abort a command sequence. the cbeif bit can trigger an interrupt request if the cbeie bit is set in sgfmmcr. while cbeif is clear, the sgfmcmd register is not writable. 1 = command buffer is ready to accept a new command. 0 = command buffer is full. ccif ? command complete interrupt flag the ccif flag indicates that no commands are pending for the flash physical blocks selected by bksel[1:0]. ccif is set and cleared automatically upon start and completion of a command. writing to ccif has no effect. the ccif bit can trigger an interrupt request if the ccie bit is set in sgfmcr. 1 = all commands are completed 0 = command in progress pviol ? protection violation flag the pviol flag indicates an attempt was made to initiate a program or erase operation in a flash logical sector denoted as protected by sgfmprot. clear pviol by writing it to 1. writing a 0 to pviol has no effect. while pviol is set in any banked register, it is not possible to launch another command. 1 = a protection violation has occurred 0 = no failure accerr ? access error flag the accerr flag indicates an illegal access to the sgfm array or registers caused by a bad program or erase sequence. accerr is cleared by writing it to 1. writing a 0 to accerr has no effect. while accerr is set in any banked register, it is not possible to launch another command. see 10.8.3.4 flash user mode illegal operations for details on what sets the accerr flag. 1 = access error has occurred 0 = no failure f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . advance information mmc2114 MMC2113 mmc2112 ? rev. 1.0 226 second generation flash for m core (sgfm) motorola second generation flash for m core (sgfm) blank ? erase verified flag the blank flag indicates that the erase verify command (rdary1) has checked the two interleaved flash physical blocks selected by bksl[1:0] and found them to be blank. clear blank by writing it to 1. writing a 0 has no effect. 1 = flash physical blocks verify as erased. 0 = if an erase verify command has been requested, and the ccif flag is set, then the selected flash physical blocks are not blank. 10.7.2.6 sgfm command register the sgfm command register (sgfmcmd) is banked and is the register to which flash program, erase, and verify commands are written. sgfmcmd is readable and writable in all modes. writes to bit 7 have no effect and reads return 0. cmd[6:0] ? command field valid flash user mode commands are shown in table 10-5 . writing a command in user mode other than those listed in table 10-5 will set the accerr flag in sgfmustat. address: 0x00d0_0020 bit 7654321bit 0 read: 0 cmd6 cmd5 cmd4 cmd3 cmd2 cmd1 cmd0 write: reset:00000000 = reserved figure 10-14. sgfm command register (sgfmcmd) table 10-5. sgfmcmd user mode commands command name description $05 rdary1 erase verify (all 1s) $20 pgm word program $40 pgers page erase $41 masers mass erase f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . second generation flash for m core (sgfm) module memory map mmc2114 MMC2113 mmc2112 ? rev. 1.0 advance information motorola second generation flash for m core (sgfm) 227 10.7.2.7 sgfm control register the sgfm control register (sgfmctl) is banked and is used only for factory testing. accesses to sgfmctl when not in test mode will result in a cycle termination transfer error. address: 0x00d0_0024 and 0x00d0_0025 bit 15 14 13 12 11 10 9 bit 8 read: rsvd15 0000000 write: reset:00000000 bit 7654321bit 0 read: rsvd7 rsvd6 rsvd5 rsvd4 rsvd3 rsvd2 rsvd1 rsvd0 write: reset:00000000 = reserved figure 10-15. sgfm control register (sgfmctl) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . advance information mmc2114 MMC2113 mmc2112 ? rev. 1.0 228 second generation flash for m core (sgfm) motorola second generation flash for m core (sgfm) 10.7.2.8 sgfm address register the sgfm address register (sgfmadr) is a banked register and is used only for factory testing. access to sgfmadr when not in test mode will result in a cycle termination transfer error. address: 0x00d0_0026 and 0x00d0_0027 bit 15 14 13 12 11 10 9 bit 8 read: 0 rsvd14 rsvd13 rsvd12 rsvd11 rsvd10 rsvd9 rsvd8 write: reset:00000000 bit 7654321bit 0 read: rsvd7 rsvd6 rsvd5 rsvd4 rsvd3 rsvd2 rsvd1 rsvd0 write: reset:00000000 = reserved figure 10-16. sgfm address register (sgfmadr) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . second generation flash for m core (sgfm) module memory map mmc2114 MMC2113 mmc2112 ? rev. 1.0 advance information motorola second generation flash for m core (sgfm) 229 10.7.2.9 sgfm data register the sgfm data register (sgfmdata) is a banked register and is used only for factory testing. accesses to sgfmdata when not in test mode will result in a cycle termination transfer error. address: 0x00d0_0028 through 0x00d0_002b bit 31 30 29 28 27 26 25 bit 24 read: rsvd31 rsvd30 rsvd29 rsvd28 rsvd27 rsvd26 rsvd25 rsvd24 write: reset:00000000 bit 23 22 21 20 19 18 17 bit 16 read: rsvd23 rsvd22 rsvd21 rsvd20 rsvd19 rsvd18 rsvd17 rsvd16 write: reset:00000000 bit 15 14 13 12 11 10 9 bit 8 read: rsvd15 rsvd14 rsvd13 rsvd12 rsvd11 rsvd10 rsvd9 rsvd8 write: reset:00000000 bit 7654321bit 0 read: rsvd7 rsvd6 rsvd5 rsvd4 rsvd3 rsvd2 rsvd1 rsvd0 write: reset:00000000 figure 10-17. sgfm data register (sgfmdata) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . advance information mmc2114 MMC2113 mmc2112 ? rev. 1.0 230 second generation flash for m core (sgfm) motorola second generation flash for m core (sgfm) 10.8 sgfm user mode normal operation of the sgfm occurs in user mode. the sgfm registers, subject to the restrictions previously noted, can generally be read and written. reads of the sgfm array generally occur normally and writes behave according to the setting of the keyacc bit in sgfmcr. program, erase, and verify operations are initiated by the cpu. special cases of user mode apply when the cpu is in low power or debug modes and when the mcu boots in master mode or emulation mode. 10.8.1 read operations a valid read operation occurs whenever a transfer request is initiated by the m core, the mlb address is equal to an address within the valid range of the sgfm memory space, and the read/write control indicates a read cycle. aligned read accesses (byte, halfword, or word) complete in one system clock cycle. misaligned accesses are not allowed and result in a cycle termination transfer error. in order to reduce power at low system clock frequencies, the sense amplifier timeout (sato) block minimizes the time during which the sense amplifiers are enabled for read operations. the sense amplifier enable signals to the flash timeout after approximately 50 ns. 10.8.2 write operations a valid write operation occurs whenever a transfer request is initiated by the m core, the mlb address is equal to an address within the valid range of the sgfm memory space, and the read/write control indicates a write cycle. the action taken on a valid sgfm array write depends on the subsequent user command issued as part of a valid command sequence. only aligned 32-bit write operations are allowed to the sgfm array. byte and halfword write operations will result in a cycle termination transfer error. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . second generation flash for m core (sgfm) sgfm user mode mmc2114 MMC2113 mmc2112 ? rev. 1.0 advance information motorola second generation flash for m core (sgfm) 231 10.8.3 program and erase operations read and write operations are both used for the program and erase algorithms described in this subsection. these algorithms are controlled by a state machine whose timebase is derived from the sgfm module clock via a programmable counter. the command register and associated address and data buffers operate as a two stage fifo so that a new command along with the necessary address and data can be stored while the previous command is still in progress. this pipelining speeds when programming more than one word on a specific row, as the charge pumps can be kept on in between two programming commands, thus saving the overhead needed to setup the charge pumps. buffer empty and command completion are indicated by flags in the sgfm user status register. interrupts will be requested if enabled. 10.8.3.1 setting the sgfmclkd register prior to issuing any program or erase commands, sgfmclkd must be written to set the flash state machine clock (fclk). the sgfm module runs at the system clock frequency, but fclk must be divided down from the system clock to a frequency between 150 khz and 200 khz. use the following procedure to set the prdiv8 and div[5:0] bits in sgfmclkd: 1. if f sys is greater than 12.8 mhz, prdiv8 = 1, otherwise prdiv8 = 0. 2. determine div[5:0] by using the following equation. keep only the integer portion of the result and discard any fraction. do not round the result. 3. thus the flash state machine clock will be: f sys 1 + (prdiv8 x 7) 200 khz div[5:0] = f sys 1 + (prdiv8 x 7) div[5:0] + 1 fclk = f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . advance information mmc2114 MMC2113 mmc2112 ? rev. 1.0 232 second generation flash for m core (sgfm) motorola second generation flash for m core (sgfm) consider the following example for f sys = 33 mhz: so, for f sys = 33 mhz, writing $54 to sgfmclkd will set fclk to 196.43 khz which is a valid frequency for the timing of program and erase operations. warning: for proper program and erase operations, it is critical to set fclk between 150 khz and 200 khz. array damage due to overstress can occur when fclk is less than 150 khz. incomplete programming and erasure can occur when fclk is greater than 200 khz. note: command execution time increases proportionally with the period of fclk. when sgfmclkd is written, the divld bit is set automatically. if divld is 0, sgfmclkd has not been written since the last reset. program and erase commands will not execute if this register has not been written (see 10.8.3.4 flash user mode illegal operations ). 10.8.3.2 program, erase, and verify sequences a command state machine is used to supervise the write sequencing of program, erase, and verify commands. before any command write sequence is started, it is necessary to write the bksel field sgfmmcr to select the banked set of registers associated with the flash physical blocks to be programmed or erased (see figure 10-2 for more details). to prepare for a command, the cbeif flag should be tested to ensure that the address, data, and command buffers are empty. if cbeif is set, the command write sequence can be started. f sys 1 + (prdiv8 x 7) 200 khz div[5:0] = f sys = 12.8 mhz, so prdiv8 = 1 33 mhz 1 + (1 x 7) 200 khz = = 20 f sys 1 + (prdiv8 x 7) div[5:0] + 1 fclk = 33 mhz 1 + (1 x 7) 20 + 1 = = 196.43 khz f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . second generation flash for m core (sgfm) sgfm user mode mmc2114 MMC2113 mmc2112 ? rev. 1.0 advance information motorola second generation flash for m core (sgfm) 233 this three-step command write sequence must be strictly followed. no intermediate writes to the sgfm module are permitted between these three steps. the command write sequence is: 1. write the 32-bit word to be programmed to its location in the sgfm array. the address and data will be stored in internal buffers. all address bits are valid for program commands. the value of the data written for verify and erase commands is ignored. for mass erase or verify, the address can be any location in the sgfm array. for page erase, address bits [9:0] are ignored. note: the page erase command operates simultaneously on adjacent erase pages in two interleaved flash physical blocks. thus, a single erase page is effectively 1 kbyte. 2. write the program, erase, or verify command to sgfmcmd, the command buffer. see 10.8.3.3 flash user mode valid commands . 3. launch the command by writing a 1 to the cbeif flag. this will clear cbeif. when command execution is complete, the flash state machine will set the ccif flag. the cbeif flag will also be set again, indicating that the address, data, and command buffers are ready for a new command sequence to begin. note: on devices with 256 kbytes of flash or more, concurrent command execution is possible. after a command is launched for the flash physical blocks serviced by the current set of banked registers, bksel[1:0] can be changed in order to launch a command for another pair of flash physical blocks. a command launched for one pair of flash physical blocks will not interfere with the execution of commands launched for other flash physical blocks and will only set the ccif flag in the sgfmustat register selected by bksel[1:0] at the time the command was launched. the flash state machine will flag errors in command write sequences by means of the accerr and pviol flags in the sgfmustat register. an erroneous command write sequence will self-abort and set the appropriate flag. the accerr or pviol flags must be cleared before commencing another command write sequence. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . advance information mmc2114 MMC2113 mmc2112 ? rev. 1.0 234 second generation flash for m core (sgfm) motorola second generation flash for m core (sgfm) note: by writing a 0 to cbeif, a command sequence can be aborted after the word write to the sgfm array or the command write to the sgfmcmd and before the command is launched. the accerr flag will be set on aborted commands and must be cleared before a new command write sequence. a summary of the programming algorithm is shown in figure 10-18 . the flow is similar for the erase and verify algorithms with the exceptions noted in step 1 above. 10.8.3.3 flash user mode valid commands table 10-6 summarizes the valid flash user commands. table 10-6. flash user mode commands sgfmcmd meaning description $05 erase verify verify that all 128 kbytes of flash from two interleaving physical blocks are erased. if both blocks are erased, the blank bit will set in the sgfmustat register upon command completion. $20 program program a 32-bit word. $40 page erase erase 1 kbyte of flash. two 512 byte pages from interleaving physical blocks are erased in this operation. $41 mass erase erase all 128 kbytes of flash from two interleaving physical blocks. a mass erase is only possible when no protect bits are set for that block. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . second generation flash for m core (sgfm) sgfm user mode mmc2114 MMC2113 mmc2112 ? rev. 1.0 advance information motorola second generation flash for m core (sgfm) 235 figure 10-18. example program algorithm write sgfmclkd read sgfmclkd divld set? write program data write program command $20 to sgfmcmd write $80 to clear sgfmustat yes no cbeif bit yes clock register written check 1. 2. 3. sgfmustat accerr bit write $10 to clear no yes no protection violation check access error check read sgfmustat no no address, data, command buffer empty check next write? yes no to array address sgfmustat pviol bit write $20 to clear yes bit polling for command completion check read sgfmustat yes note: command sequence aborted by writing $00 to sgfmustat note: command sequence aborted by writing $00 to sgfmustat exit read sgfmustat no start yes cbeif set? pviol set? accerr set? cbeif set? ccif set? f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . advance information mmc2114 MMC2113 mmc2112 ? rev. 1.0 236 second generation flash for m core (sgfm) motorola second generation flash for m core (sgfm) 10.8.3.4 flash user mode illegal operations the accerr flag will be set during a command write sequence if any of the illegal operations below are performed. such operations will cause the command sequence to immediately abort. 1. writing to the sgfm array before initializing sgfmclkd. 2. writing to the sgfm array while in emulation mode. 3. writing a byte or a halfword to the sgfm array. only 32-bit word programming is allowed. 4. writing to the sgfm array at a location that does not match bksel[1:0]. depending on the size of the flash array. mlb address bits [18:17] must match bksel[1:0]. 5. writing to the sgfm array while cbeif is not set. 6. writing a second word to the sgfm array before executing a command on the previously written word. 7. writing an invalid user command to the sgfmcmd. 8. writing to any sgfm other than sgfmcmd after writing a word to the sgfm array. 9. writing a second command to sgfmcmd before executing the previously written command. 10. writing to any sgfm register other than sgfmustat (to clear cbeif) after writing to the command register. 11. entering stop mode while a program or erase command is in progress. 12. aborting a command sequence by writing a 0 to cbeif after the word write to the sgfm array or after writing a command to sgfmcmd and before launching it. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . second generation flash for m core (sgfm) sgfm user mode mmc2114 MMC2113 mmc2112 ? rev. 1.0 advance information motorola second generation flash for m core (sgfm) 237 the pviol flag will be set during a command write sequence after the word write to the sgfm array if any of the illegal operations below are performed. such operations will cause the command sequence to immediately abort. 1. writing to an address in a protected area of the sgfm array. 2. writing a mass erase command to sgfmcmd while any logical sector is protected (see 10.7.2.1 sgfm protection register ). if a flash physical block is read during a program or erase operation on that block (sgfmustat bit ccif = 0), the read will return non-valid data and the accerr flag will not be set. 10.8.4 stop mode if a command is active (ccif = 0) when the mcu enters stop mode, the command sequence monitor will perform the following: 1. the command in progress will be aborted. 2. the flash high voltage circuitry will be switched off and any pending command (cbeif = 0) will not be executed when the mcu exits stop mode. 3. the ccif and accerr flags will be set if a command is active when the mcu enters stop mode. note: the state of any word(s) being programmed or any erase pages/physical blocks being erased is not guaranteed if the mcu enters stop mode with a command in progress. warning: active commands are immediately aborted when the mcu enters stop mode. do not execute the stop instruction during program and erase operations. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . advance information mmc2114 MMC2113 mmc2112 ? rev. 1.0 238 second generation flash for m core (sgfm) motorola second generation flash for m core (sgfm) 10.8.5 master mode if the mcu is booted in master mode with an external memory selected as the boot device, the sgfm will not respond to the first transfer request out of reset, even if the mlb address is equal to an address within the sgfm array. this will allow the external boot device to provide the reset vector and terminate the bus cycle. 10.8.6 emulation mode in emulation mode, the sgfm module will not terminate the bus cycles by asserting ta or tea in response to array read requests. external memory that emulates the flash will drive the data bus and the ebi emulation chip mechanism will terminate the bus cycle instead of the sgfm module. note: in emulation mode, write accesses to the sgfm array will generate an sgfm access error and set the accerr bit. 10.8.7 debug mode in debug mode, the sgfm module behaves exactly as it does in user mode, except that the lock bit in sgfmmcr and the sgfmclkd[6:0] register bits are always writable. 10.9 flash security operation the sgfm array provides security information to the integration module and the rest of the mcu. a word in the flash configuration field stores this information. this word is read automatically after each reset and is stored in the sgfmsec register. in user mode, security can be bypassed via a back door access scheme using an 8-byte long key. upon successful completion of the back door access sequence, the module output signal and status bit indicating that the chip is secure are cleared. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . second generation flash for m core (sgfm) flash security operation mmc2114 MMC2113 mmc2112 ? rev. 1.0 advance information motorola second generation flash for m core (sgfm) 239 the sgfm may be unsecured via one of two methods: 1. executing a back door access scheme. 2. passing an erase verify check. 10.9.1 back door access if the keyen bit is set, security can be bypassed by: 1. setting the keyacc bit in the sgfm configuration register (sgfmmcr). 2. writing the correct 8-byte back door comparison key to the sgfm array at addresses 0x0000_0200 to 0x0000_0207. this operation must consist of two 32-bit writes to address 0x0000_0200 and 0x0000_0204 in that order. the two back door write cycles can be separated by any number of bus cycles. 3. clearing the keyacc bit. 4. if all 8 bytes written match the array contents at addresses 0x0000_0200 to 0x0000_0207, then security is bypassed until the next reset. note: the security of the flash as defined by the flash security word at address 0x0000_0228 is not changed by the back door method of unsecuring the device. after the next reset the device is again secured and the same back door key remains in effect unless changed by program or erase operations. the back door method of unsecuring the device has no effect on the program and erase protections defined by the sgfm protection register (sgfmprot). 10.9.2 erase verify check security can be disabled by verifying that the sgfm array is blank. if required, the mass erase command can be executed for each pair of flash physical blocks that comprise the array. the erase verify command must then be executed for all flash physical blocks within the array. the sgfm will be unsecured if the erase verify command determines that the entire array is blank. after the next reset, the security f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . advance information mmc2114 MMC2113 mmc2112 ? rev. 1.0 240 second generation flash for m core (sgfm) motorola second generation flash for m core (sgfm) state of the sgfm will be determined by the flash security word, which, after being erased, will read 0xffff_ffff, thus unsecuring the module. 10.10 resets the sgfm array is not accessible for any operations via the address and data buses during reset. if a reset occurs while any command is in progress that command will immediately abort. the state of any word being programmed or any erase pages/physical blocks being erased is not guaranteed. 10.11 interrupts the sgfm module can request an interrupt when all commands are completed or when the address, data, and command buffers are empty. figure 10-19 shows the sgfm interrupt mechanism. this system uses the cbeie and ccie bits as well as the register bank select signals to enable interrupt requests. by taking into account the selected register bank, false interrupt requests are not generated when the command buffer is empty in an unselected register bank. table 10-7 sgfm interrupt sources interrupt source interrupt flag local enable global mask (psr) command, data and address buffers empty cbeif (sgfmustat) cbeie (sgfmmcr) ie/fe bit all commands are completed ccif (sgfmustat) ccie (sgfmmcr) ie/fe bit f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . second generation flash for m core (sgfm) interrupts mmc2114 MMC2113 mmc2112 ? rev. 1.0 advance information motorola second generation flash for m core (sgfm) 241 figure 10-19. sgfm interrupt implementation bank 0 cbeif bank 0 select bank 1 cbeif bank 1 select cbeie bank 0 ccif bank 0 select bank 1 ccif bank 1 select ccie sgfm interrupt request f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . advance information mmc2114 MMC2113 mmc2112 ? rev. 1.0 242 second generation flash for m core (sgfm) motorola second generation flash for m core (sgfm) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . mmc2114 MMC2113 mmc2112 ? rev. 1.0 advance information motorola clock module 243 advance information ? mmc2114, MMC2113, and mmc2112 section 11. clock module 11.1 contents 11.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .244 11.3 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .244 11.4 modes of operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .245 11.4.1 normal pll mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .245 11.4.2 1:1 pll mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .245 11.4.3 external clock mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . .245 11.4.4 low-power options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .245 11.4.4.1 wait and doze modes . . . . . . . . . . . . . . . . . . . . . . . . . .245 11.4.4.2 stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .246 11.5 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .247 11.6 signal descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .248 11.6.1 extal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .248 11.6.2 xtal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .248 11.6.3 clkout. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 248 11.6.4 pllen . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .248 11.6.5 rstout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .249 11.7 memory map and registers . . . . . . . . . . . . . . . . . . . . . . . . . .249 11.7.1 module memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . .249 11.7.2 register descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . .250 11.7.2.1 synthesizer control register . . . . . . . . . . . . . . . . . . . . .250 11.7.2.2 synthesizer status register. . . . . . . . . . . . . . . . . . . . . .253 11.7.2.3 synthesizer test register . . . . . . . . . . . . . . . . . . . . . . .256 11.7.2.4 synthesizer test register 2 . . . . . . . . . . . . . . . . . . . . . .257 11.8 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .258 11.8.1 system clock modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . .258 11.8.2 system clocks generation. . . . . . . . . . . . . . . . . . . . . . . . .259 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . advance information mmc2114 MMC2113 mmc2112 ? rev. 1.0 244 clock module motorola clock module 11.8.3 pll lock detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .259 11.8.3.1 pll loss of lock conditions . . . . . . . . . . . . . . . . . . . . .261 11.8.3.2 pll loss of lock reset . . . . . . . . . . . . . . . . . . . . . . . . .261 11.8.4 loss of clock detection . . . . . . . . . . . . . . . . . . . . . . . . . . . 261 11.8.4.1 alternate clock selection . . . . . . . . . . . . . . . . . . . . . . . .262 11.8.4.2 loss-of-clock reset. . . . . . . . . . . . . . . . . . . . . . . . . . . .265 11.8.5 clock operation during reset . . . . . . . . . . . . . . . . . . . . . .266 11.8.6 pll operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .266 11.8.6.1 phase and frequency detector (pfd). . . . . . . . . . . . . .268 11.8.6.2 charge pump/loop filter . . . . . . . . . . . . . . . . . . . . . . . .268 11.8.6.3 voltage control output (vco) . . . . . . . . . . . . . . . . . . . .269 11.8.6.4 multiplication factor divider (mfd) . . . . . . . . . . . . . . . . 269 11.9 reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 269 11.10 interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .269 11.2 introduction the clock module contains: crystal oscillator (osc) phase-locked loop (pll) reduced frequency divider (rfd) status and control registers control logic 11.3 features features of the clock module include: 2- to 10-mhz reference crystal oscillator support for low-power modes separate clock out signal f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . clock module modes of operation mmc2114 MMC2113 mmc2112 ? rev. 1.0 advance information motorola clock module 245 11.4 modes of operation the clock module can be operated in normal pll mode (default), 1:1 pll mode, or external clock mode. 11.4.1 normal pll mode in normal pll mode, the pll is fully programmable. it can synthesize frequencies ranging from 2x to 9x the reference frequency and has a post divider capable of reducing this synthesized frequency without disturbing the pll. the pll reference can be either a crystal oscillator or an external clock. 11.4.2 1:1 pll mode in 1:1 pll mode, the pll synthesizes a frequency equal to the external clock input reference frequency. the post divider is not active. 11.4.3 external clock mode in external clock mode, the pll is bypassed, and the external clock is applied to extal. the resulting operating frequency is one-half the external clock frequency. 11.4.4 low-power options during wakeup from a low-power mode, the flash clock always clocks through at least 16 cycles before the cpu clocks are enabled. this allows the flash module time to recover from the low-power mode, and software can immediately resume fetching instructions from the flash memory. 11.4.4.1 wait and doze modes in wait and doze modes, the system clocks to the peripherals are enabled, and the clocks to the cpu, flash, and sram are stopped. each module can disable the module clocks locally at the module level. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . advance information mmc2114 MMC2113 mmc2112 ? rev. 1.0 246 clock module motorola clock module 11.4.4.2 stop mode in stop mode, all system clocks are disabled. there are several options for enabling/disabling the pll and/or crystal oscillator in stop mode at the price of increased wakeup recovery time. the pll can be disabled in stop mode, but then it requires a wakeup period before it can relock. the osc can also be disabled during stop mode, but then it requires a wakeup period to restart. when the pll is enabled in stop mode (stpmd[1:0]), the external clkout signal can support systems using clkout as the clock source. there is also a fast wakeup option for quickly enabling the system clocks during stop recovery. this eliminates the wakeup recovery time but at a risk of sending a potentially unstable clock to the system. to prevent a non-locked pll frequency overshoot when using the fast wakeup option, change the rfd divisor to the current rfd value plus one before entering stop mode. in external clock mode, there are no wakeup periods for osc startup or pll lock. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . clock module block diagram mmc2114 MMC2113 mmc2112 ? rev. 1.0 advance information motorola clock module 247 11.5 block diagram figure 11-1. clock module block diagram clkout xtal external clock osc pllref reference clock pll mfd pllmode locen pllen rstout clkout locks lock locs rfd to reset module lolre locre stpmd[1:0] stop mode pllsel disclk pll clock out scaled pll clock out internal clock pllmode clkgen ( 2) stop mode internal clocks lock fwkup extal f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . advance information mmc2114 MMC2113 mmc2112 ? rev. 1.0 248 clock module motorola clock module 11.6 signal descriptions the clock module signals are summarized in table 11-1 and a brief description follows. for more detailed information, refer to section 3. signal description . 11.6.1 extal this input is driven by an external clock except when used as a connection to the external crystal when using the internal oscillator. 11.6.2 xtal this output is an internal oscillator connection to the external crystal. 11.6.3 clkout this output reflects the internal system clock. 11.6.4 pllen this input must be at v dd potential to enable the pll. table 11-1. signal properties name function extal oscillator or clock input xtal oscillator output clkout system clock output pllen pll enable input rstout reset signal from reset controller f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . clock module memory map and registers mmc2114 MMC2113 mmc2112 ? rev. 1.0 advance information motorola clock module 249 11.6.5 rstout the rstout pin is asserted by: internal system reset signal, or frcrstout bit in the reset control status register (rcr); see 5.6.1 reset control register 11.7 memory map and registers the clock programming model consists of these registers: synthesizer control register (syncr) ? defines clock operation, refer to 11.7.2.1 synthesizer control register synthesizer status register (synsr) ? reflects clock status, refer to 11.7.2.2 synthesizer status register synthesizer test register (syntr) ? used for factory test, refer to 11.7.2.3 synthesizer test register synthesizer test register 2 (syntr2) ? used only for factory test, refer to 11.7.2.4 synthesizer test register 2 11.7.1 module memory map table 11-2. clock module memory map address register name access (1) 1. s = cpu supervisor mode access only. 0x00c3_0000 synthesizer control register (syncr) s 0x00c3_0002 synthesizer status register (synsr) s 0x00c3_0003 synthesizer test register (syntr) s 0x00c3_0004 synthesizer test register 2 (syntr2) s f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . advance information mmc2114 MMC2113 mmc2112 ? rev. 1.0 250 clock module motorola clock module 11.7.2 register descriptions this subsection provides a description of the clock module registers. 11.7.2.1 synthesizer control register the synthesizer control register (syncr) is read/write always. lolre ? loss of lock reset enable bit the lolre bit determines how the system handles a loss of lock indication. when operating in normal mode or 1:1 pll mode, the pll must be locked before setting the lolre bit. otherwise reset is immediately asserted. to prevent an immediate reset, the lolre bit must be cleared before writing the mfd[2:0] bits or entering stop mode with the pll disabled. 1 = reset on loss of lock 0 = no reset on loss of lock note: in external clock mode, the lolre bit has no effect. address: 0x00c3_0000 and 0x00c3_0001 bit 15 14 13 12 11 10 9 bit 8 read: lolre mfd2 mfd1 mfd0 locre rfd2 rfd1 rfd0 write: reset:00100001 bit 7654321bit 0 read: locen disclk fwkup 0 stmpd1 stmpd0 00 write: reset:00000000 = writes have no effect and the access terminates without a transfer error exception. figure 11-2. synthesizer control register (syncr) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . clock module memory map and registers mmc2114 MMC2113 mmc2112 ? rev. 1.0 advance information motorola clock module 251 mfd[2:0] ? multiplication factor divider field mfd[2:0] contain the binary value of the divider in the pll feedback loop. see table 11-3 . the mfd[2:0] value is the multiplication factor applied to the reference frequency. when mfd[2:0] are changed or the pll is disabled in stop mode, the pll loses lock. in 1:1 pll mode, mfd[2:0] are ignored, and the multiplication factor is one. note: in external clock mode, the mfd[2:0] bits have no effect. see table 11-6 . locre ? loss of clock reset enable bit the locre bit determines how the system handles a loss of clock condition. when the locen bit is clear, locre has no effect. if the locs flag in synsr indicates a loss of clock condition, setting the locre bit causes an immediate reset. to prevent an immediate reset, the locre bit must be cleared before entering stop mode with the pll disabled. 1 = reset on loss of clock 0 = no reset on loss of clock note: in external clock mode, the locre bit has no effect. table 11-3. system frequency multiplier of the reference frequency (1) in normal pll mode 1. f sys = f ref x (mfd + 2)/2 exp rfd; f ref x (mfd + 2) <= 80 mhz, f sys <= 33 mhz mfd[2:0] 000 (2) (2x) 2. mfd = 000 not valid for f ref < 3 mhz 001 (3x) 010 (4x) (3) 011 (5x) 100 (6x) 101 (7x) 110 (8x) 111 (9x) rfd[2:0] 000 ( 23456789 001 ( 3. default value out of reset 1 3/2 2 5/2 3 7/2 4 9/2 010 ( 1/2 3/4 1 5/4 3/2 7/4 2 9/4 011 ( 1/4 3/8 1/2 5/8 3/4 7/8 1 9/8 100 ( 1/8 3/16 1/4 5/16 3/8 7/16 1/2 9/16 101 ( 1/16 3/32 1/8 5/32 3/16 7/32 1/4 9/32 110 ( 1/32 3/64 1/16 5/64 3/32 7/64 1/8 9/64 111 ( 1/64 3/128 1/32 5/128 3/64 7/128 1/16 9/128 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . advance information mmc2114 MMC2113 mmc2112 ? rev. 1.0 252 clock module motorola clock module rfd[2:0] ? reduced frequency divider field the binary value written to rfd[2:0] is the pll frequency divisor. see table 11-3 . changing rfd[2:0] does not affect the pll or cause a relock delay. changes in clock frequency are synchronized to the next falling edge of the current system clock. to avoid surpassing the allowable system operating frequency, write to rfd[2:0] only when the lock bit is set. note: in external clock mode, the rfd[2:0] bits have no effect. see table 11-6 . locen ? loss of clock enable bit the locen bit enables the loss of clock function. locen does not affect the loss of lock function. 1 = loss of clock function enabled 0 = loss of clock function disabled note: in external clock mode, the locen bit has no effect. disclk ? disable clkout bit the disclk bit determines whether clkout is driven. setting the disclk bit holds clkout low. 1 = clkout disabled 0 = clkout enabled fwkup ? fast wakeup bit the fwkup bit determines when the system clocks are enabled during wakeup from stop mode. 1 = system clocks enabled on wakeup regardless of pll lock status 0 = system clocks enabled only when pll is locked or operating normally note: when fwkup = 0, if the pll or osc is enabled and unintentionally lost in stop mode, the pll wakes up in self-clocked mode or reference clock mode depending on the clock that was lost. in external clock mode, the fwkup bit has no effect on the wakeup sequence. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . clock module memory map and registers mmc2114 MMC2113 mmc2112 ? rev. 1.0 advance information motorola clock module 253 stpmd[1:0] ? stop mode bits stpmd[1:0] control pll and clkout operation in stop mode as shown in table 11-4 . 11.7.2.2 synthesizer status register the synthesizer status register (synsr) is a read-only register that can be read at any time. writing to the synsr has no effect and terminates the cycle normally. table 11-4. stpmd[1:0] operation in stop mode stpmd[1:0] operation during stop mode system clocks pll osc clkout 00 disabled enabled enabled enabled 01 disabled enabled enabled disabled 10 disabled disabled enabled disabled 11 disabled disabled disabled disabled address: 0x00c3_0002 bit 7654321bit 0 read: pllmode pllsel pllref locks lock locs 0 0 write: reset: note 1 note 1 note 1 note 2 note 2 0 0 0 = writes have no effect and the access terminates without a transfer error exception. notes: 1. reset state determined during reset configuration. 2. see the locks and lock bit descriptions. figure 11-3. synthesizer status register (synsr) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . advance information mmc2114 MMC2113 mmc2112 ? rev. 1.0 254 clock module motorola clock module pllmode ? clock mode bit the mode bit is configured at reset and reflects the clock mode as shown in table 11-5 . 1 = pll clock mode 0 = external clock mode pllsel ? pll select bit the pllsel bit is configured at reset and reflects the pll mode as shown in table 11-5 . 1 = normal pll mode 0 = 1:1 pll mode pllref ? pll reference bit the pllref bit is configured at reset and reflects the pll reference source in normal pll mode as shown in table 11-5 . 1 = crystal clock reference 0 = external clock reference locks ? sticky pll lock bit the locks flag is a sticky indication of pll lock status. 1 = no unintentional pll loss of lock since last system reset or mfd change 0 = pll loss of lock since last system reset or mfd change or currently not locked due to exit from stop with fwkup set the lock detect function sets the locks bit when the pll achieves lock after: ? a system reset, or ? a write to syncr that changes the mfd[2:0] bits table 11-5. system clock modes pllmode:pllsel:pllref clock mode 000 external clock mode 100 1:1 pll mode 110 normal pll mode with external clock reference 111 normal pll mode with crystal oscillator reference f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . clock module memory map and registers mmc2114 MMC2113 mmc2112 ? rev. 1.0 advance information motorola clock module 255 when the pll loses lock, locks is cleared. when the pll relocks, locks remains cleared until one of the two listed events occurs. in stop mode, if the pll is intentionally disabled, then the locks bit reflects the value prior to entering stop mode. however, if fwkup is set, then locks is cleared until the pll regains lock. once lock is regained, the locks bit reflects the value prior to entering stop mode. furthermore, reading the locks bit at the same time that the pll loses lock does not return the current loss of lock condition. in external clock mode, locks remains cleared after reset. in normal pll mode and 1:1 pll mode, locks is set after reset. lock ? pll lock flag 1 = pll locked 0 = pll not locked the lock flag is set when the pll is locked. pll lock occurs when the synthesized frequency is within approximately 0.75 percent of the programmed frequency. the pll loses lock when a frequency deviation of greater than approximately 1.5 percent occurs. reading the lock flag at the same time that the pll loses lock or acquires lock does not return the current condition of the pll. the power-on reset circuit uses the lock bit as a condition for releasing reset. if operating in external clock mode, lock remains cleared after reset. locs ? sticky loss of clock flag 1 = loss of clock detected since exiting reset or oscillator not yet recovered from exit from stop mode with fwkup = 1 0 = loss of clock not detected since exiting reset the locs flag is a sticky indication of whether a loss of clock condition has occurred at any time since exiting reset in normal pll and 1:1 pll modes. locs = 0 when the system clocks are operating normally. locs = 1 when system clocks have failed due to a reference failure or pll failure. after entering stop mode with fwkup set and the pll and oscillator intentionally disabled (stpmd[1:0] = 11), the pll exits stop mode in scm while the oscillator starts up. during this time, locs is temporarily set regardless of locen. it is cleared once the oscillator comes up and the pll is attempting to lock. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . advance information mmc2114 MMC2113 mmc2112 ? rev. 1.0 256 clock module motorola clock module if a read of the locs flag and a loss of clock condition occur simultaneously, the flag does not reflect the current loss of clock condition. a loss of clock condition can be detected only if locen = 1 or the oscillator has not yet returned from exit from stop mode with fwkup = 1. note: the locs flag is always 0 in external clock mode. 11.7.2.3 synthesizer test register the synthesizer test register (syntr) is only for factory testing. when not in test mode, syntr is read-only. address: 0x00c3_0003 bit 7654321bit 0 read: 0 0 000000 write: reset:00000000 = writes have no effect and the access terminates without a transfer error exception. figure 11-4. synthesizer test register (syntr) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . clock module memory map and registers mmc2114 MMC2113 mmc2112 ? rev. 1.0 advance information motorola clock module 257 11.7.2.4 synthesizer test register 2 the synthesizer test register 2 (syntr2) is only for factory testing. bits 31 ? 10 bits 31 ? 10 are read-only. writing to bits 31 ? 10 has no effect. rsvd9 ? rsvd0 ? reserved the rsvd bits can be read at any time. writes to these bits update the register values but have no effect on functionality. address: 0x00c3_0004 through 0x00c3_0007 bit 31 30 29 28 27 26 25 bit 24 read: 0 0 000000 write: reset:00000000 bit 23 22 21 20 19 18 17 bit 16 read: 0 0 000000 write: reset:00000000 bit 15 14 13 12 11 10 9 bit 8 read: 0 0 0000 rsvd9 rsvd8 write: reset:00000000 bit 7654321bit 0 read: rsvd7 rsvd6 rsvd5 rsvd4 rsvd3 rsvd2 rsvd1 rsvd0 write: reset:00000000 = writes have no effect and the access terminates without a transfer error exception. figure 11-5. synthesizer test register 2 (syntr2) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . advance information mmc2114 MMC2113 mmc2112 ? rev. 1.0 258 clock module motorola clock module 11.8 functional description this subsection provides a functional description of the clock module. 11.8.1 system clock modes the system clock source is determined during reset (see table 4-7. configuration during reset ). the value of pllen is latched during reset and is of no importance after reset is negated. if pllen is changed during a reset other than power-on reset, the internal clocks may glitch as the clock source is changed between external clock mode and pll clock mode. whenever pllen is changed in reset, an immediate loss of lock condition occurs. table 11-6 shows the clock-out frequency to clock-in frequency relationships for the possible clock modes. caution: xtal must be tied low in external clock mode when reset is asserted. if it is not, clocks could be suspended indefinitely. the external clock is divided by two internally to produce the system clocks. table 11-6. clock-out and clock-in relationships clock mode pll options (1) 1. f ref = input reference frequency f sys = clkout frequency mfd ranges from 0 to 7. rfd ranges from 0 to 7. normal pll clock mode f sys = f ref (mfd + 2)/2 rfd 1:1 pll clock mode f sys = f ref external clock mode f sys = f ref /2 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . clock module functional description mmc2114 MMC2113 mmc2112 ? rev. 1.0 advance information motorola clock module 259 11.8.2 system clocks generation in normal pll clock mode, the default system frequency is two times the reference frequency after reset. the rfd[2:0] and mfd[2:0] bits in syncr select the frequency multiplier. when programming the pll, do not exceed the maximum system clock frequency listed in the electrical specifications. use this procedure to accommodate the frequency overshoot that occurs when the mfd bits are changed: 1. determine the appropriate value for the mfd and rfd fields in syncr. the amount of jitter in the system clocks can be minimized by selecting the maximum mfd factor that can be paired with an rfd factor to provide the required frequency. 2. write a value of rfd (from step 1 ) + 1 to the rfd field of syncr. 3. write the mfd value from step 1 to syncr. 4. monitor the lock flag in synsr. when the pll achieves lock, write the rfd value from step 1 to the rfd field of syncr. this changes the system clocks frequency to the required frequency. note: keep the maximum system clock frequency below the limit given in section 23. preliminary electrical specifications . 11.8.3 pll lock detection the lock detect logic monitors the reference frequency and the pll feedback frequency to determine when frequency lock is achieved. phase lock is inferred by the frequency relationship, but is not guaranteed. the lock flag in synsr reflects the pll lock status. a sticky lock flag, locks, is also provided. the lock detect function uses two counters. one is clocked by the reference and the other is clocked by the pll feedback. when the reference counter has counted n cycles, its count is compared to that of the feedback counter. if the feedback counter has also counted n cycles, the process is repeated for n + k counts. then, if the two counters still match, the lock criteria is relaxed by 1/2 and the system is notified that the pll has achieved frequency lock. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . advance information mmc2114 MMC2113 mmc2112 ? rev. 1.0 260 clock module motorola clock module after lock is detected, the lock circuit continues to monitor the reference and feedback frequencies using the alternate count and compare process. if the counters do not match at any comparison time, then the lock flag is cleared to indicate that the pll has lost lock. at this point, the lock criteria is tightened and the lock detect process is repeated. the alternate count sequences prevent false lock detects due to frequency aliasing while the pll tries to lock. alternating between tight and relaxed lock criteria prevents the lock detect function from randomly toggling between locked and non-locked status due to phase sensitivities. figure 11-6 shows the sequence for detecting locked and non-locked conditions. in external clock mode, the pll is disabled and cannot lock. figure 11-6. lock detect sequence count n reference cycles and compare number of feedback cycles elapsed start with tight lock criteria reference count feedback count loss of lock detected set tight lock criteria and notify system of loss of lock condition count n + k reference cycles and compare number of feedback cycles elapsed lock detected. set relaxed lock condition and notify system of lock condition reference count feedback count reference count = feedback count = n in same count/compare sequence reference count = feedback count = n + k in same count/compare sequence f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . clock module functional description mmc2114 MMC2113 mmc2112 ? rev. 1.0 advance information motorola clock module 261 11.8.3.1 pll loss of lock conditions once the pll acquires lock after reset, the lock and locks flags are set. if the mfd is changed, or if an unexpected loss of lock condition occurs, the lock and locks flags are negated. while the pll is in the non-locked condition, the system clocks continue to be sourced from the pll as the pll attempts to relock. consequently, during the relocking process, the system clocks frequency is not well defined and may exceed the maximum system frequency, violating the system clock timing specifications. however, once the pll has relocked, the lock flag is set. the locks flag remains cleared if the loss of lock is unexpected. the locks flag is set when the loss of lock is caused by changing mfd. if the pll is intentionally disabled during stop mode, then after exit from stop mode, the locks flag reflects the value prior to entering stop mode once lock is regained. 11.8.3.2 pll loss of lock reset if the lolre bit in syncr is set, a loss of lock condition asserts reset. reset reinitializes the lock and locks flags. therefore, software must read the lol bit in reset status register (rsr) to determine if a loss of lock caused the reset. see 5.6.2 reset status register . to exit reset in pll mode, the reference must be present, and the pll must achieve lock. in external clock mode, the pll cannot lock. therefore, a loss of lock condition cannot occur, and the lolre bit has no effect. 11.8.4 loss of clock detection the locen bit in syncr enables the loss of clock detection circuit to monitor the input clocks to the phase and frequency detector (pfd). when either the reference or feedback clock frequency falls below the minimum frequency, the loss of clock circuit sets the sticky locs flag in synsr. note: in external clock mode, the loss of clock circuit is disabled. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . advance information mmc2114 MMC2113 mmc2112 ? rev. 1.0 262 clock module motorola clock module 11.8.4.1 alternate clock selection depending on which clock source fails, the loss-of-clock circuit switches the system clocks source to the remaining operational clock. the alternate clock source generates the system clocks until reset is asserted. as table 11-7 shows, if the reference fails, the pll goes out of lock and into self-clocked mode (scm). the pll remains in scm until the next reset. when the pll is operating in scm, the system frequency depends on the value in the rfd field. the scm system frequency stated in electrical specifications assumes that the rfd has been programmed to binary 000. if the loss-of-clock condition is due to pll failure, the pll reference becomes the system clocks source until the next reset, even if the pll regains and relocks. a special loss-of-clock condition occurs when both the reference and the pll fail. the failures may be simultaneous, or the pll may fail first. in either case, the reference clock failure takes priority and the pll attempts to operate in scm. if successful, the pll remains in scm until the next reset. if the pll cannot operate in scm, the system remains static until the next reset. both the reference and the pll must be functioning properly to exit reset. table 11-7. loss of clock summary clock mode system clock source before failure reference failure alternate clock selected by loc circuit (1) until reset 1. the loc circuit monitors the reference and feedback inputs to the pfd. see figure 11-8 . pll failure alternate clock selected by loc circuit until reset pll pll pll self-clocked mode pll reference external external clock none na f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . clock module functional description mmc2114 MMC2113 mmc2112 ? rev. 1.0 advance information motorola clock module 263 table 11-8. stop mode operation (sheet 1 of 3) mode in locen locre lolre pll osc fwkup expected pll action at stop pll action during stop mode out locks lock locs comments ext xxx x x x ? ? ext 000 lose reference clock stuck ??? nrm 0 0 0 off off 0 lose lock, f.b. clock, reference clock regain nrm ? lk 1 ? lc no regain stuck ??? nrm x 0 0 off off 1 lose lock, f.b. clock, reference clock regain clocks, but don ? t regain lock scm ? > unstable nrm 0 ? > ? lk 0 ? >1 1 ? > ? lc block locs and locks until clock and lock respectively regain; enter scm regardless of locen bit until reference regained no reference clock regain scm ? >0 ? >0 ? >1 ? > block locs and locks until clock and lock respectively regain; enter scm regardless of locen bit no f.b. clock regain stuck ??? nrm 0 0 0 off on 0 lose lock regain nrm ? lk 1 ? lc block locks from being cleared lose reference clock or no lock regain stuck ??? lose reference clock, regain nrm ? lk 1 ? lc block locks from being cleared nrm 0 0 0 off on 1 lose lock no lock regain unstable nrm 0 ? > ? lk 0 ? >1 ? lc block locks until lock regained lose reference clock or no f.b. clock regain stuck ??? lose reference clock, regain unstable nrm 0 ? > ? lk 0 ? >1 ? lc locs not set because locen = 0 nrm 0 0 0 on on 0 ? ? nrm ? lk 1 ? lc lose lock or clock stuck ??? lose lock, regain nrm 0 1 ? lc lose clock and lock, regain nrm 0 1 ? lc locs not set because locen = 0 nrm 0 0 0 on on 1 ? ? nrm ? lk 1 ? lc lose lock unstable nrm 0 0 ? >1 ? lc lose lock, regain nrm 0 1 ? lc lose clock stuck ??? lose clock, regain without lock unstable nrm 0 0 ? >1 ? lc lose clock, regain with lock nrm 0 1 ? lc f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . advance information mmc2114 MMC2113 mmc2112 ? rev. 1.0 264 clock module motorola clock module nrm x x 1 off x x lose lock, f.b. clock, reference clock reset reset ??? reset immediately nrm 0 0 1 on on x ? ? nrm ? lk 1 ? lc lose lock or clock reset ??? reset immediately nrm 1 0 0 off off 0 lose lock, f.b. clock, reference clock regain nrm ? lk 1 ? lc ref not entered during stop; scm entered during stop only during osc startup no regain stuck ??? nrm 1 0 0 off on 0 lose lock, f.b. clock regain nrm ? lk 1 ? lc ref mode not entered during stop no f.b. clock or lock regain stuck ??? lose reference clock scm 0 0 1 wakeup without lock nrm 1 0 0 off on 1 lose lock, f.b. clock regain f.b. clock unstable nrm 0 ? > ? lk 0 ? >1 ? lc ref mode not entered during stop no f.b. clock regain stuck ??? lose reference clock scm 0 0 1 wakeup without lock nrm 1 0 0 on on 0 ? ? nrm ? lk 1 ? lc lose reference clock scm 0 0 1 wakeup without lock lose f.b. clock ref 0 x 1 wakeup without lock lose lock stuck ??? lose lock, regain nrm 0 1 ? lc nrm 1 0 0 on on 1 ? ? nrm ? lk 1 ? lc lose reference clock scm 0 0 1 wakeup without lock lose f.b. clock ref 0 x 1 wakeup without lock lose lock unstable nrm 0 0 ? >1 ? lc nrm 1 0 1 on on x ? ? nrm ? lk 1 ? lc lose lock or clock reset ??? reset immediately nrm 11xoff x x lose lock, f.b. clock, reference clock reset reset ??? reset immediately nrm 1 1 0 on on 0 ? ? nrm ? lk 1 ? lc lose clock reset ??? reset immediately lose lock stuck ??? lose lock, regain nrm 0 1 ? lc table 11-8. stop mode operation (sheet 2 of 3) mode in locen locre lolre pll osc fwkup expected pll action at stop pll action during stop mode out locks lock locs comments f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . clock module functional description mmc2114 MMC2113 mmc2112 ? rev. 1.0 advance information motorola clock module 265 11.8.4.2 loss-of-clock reset when a loss-of-clock condition is recognized, reset is asserted if the locre bit in syncr is set. the locs bit in synsr is cleared after reset. therefore, the loc bit must be read in rsr to determine that a loss of clock condition occurred. locre has no effect in external clock mode. nrm 1 1 0 on on 1 ? ? nrm ? lk 1 ? lc lose clock reset ??? reset immediately lose lock unstable nrm 0 0 ? >1 ? lc lose lock, regain nrm 0 1 ? lc nrm 1 1 1 on on x ? ? nrm ? lk 1 ? lc lose clock or lock reset ??? reset immediately ref 1 0 0 x x x ? ? ref 0 x 1 lose reference clock stuck ??? scm 1 0 0 off x 0 pll disabled regain scm scm 0 0 1 wakeup without lock scm 1 0 0 off x 1 pll disabled regain scm scm 0 0 1 scm 1 0 0 on on 0 ? ? scm 0 0 1 wakeup without lock lose reference clock scm scm 1 0 0 on on 1 ? ? scm 001 lose reference clock scm pll = pll enabled during stop mode. pll = on when stpmd[1:0] = 00 or 01 osc = osc enabled during stop mode. osc = on when stpmd[1:0] = 00, 01, or 10 modes nrm = normal pll crystal clock reference or normal pll external reference or pll 1:1 mode. during pll 1:1 or normal external ref erence mode, the oscillator is never enabled. therefore, during these modes, refer to the osc = on case regardless of stpmd values. ext = external clock mode ref = pll reference mode due to losing pll clock or lock from nrm mode scm = pll self-clocked mode due to losing reference clock from nrm mode reset = immediate reset locks ? lk = expecting previous value of locks before entering stop 0 ? > ? lk = current value is 0 until lock is regained which then will be the previous value before entering stop 0 ? > = current value is 0 until lock is regained but lock is never expected to regain locs ? lc = expecting previous value of locs before entering stop 1 ? > ? lc = current value is 1 until clock is regained which then will be the previous value before entering stop 1 ? > = current value is 1 until clock is regained but clk is never expected to regain table 11-8. stop mode operation (sheet 3 of 3) mode in locen locre lolre pll osc fwkup expected pll action at stop pll action during stop mode out locks lock locs comments f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . advance information mmc2114 MMC2113 mmc2112 ? rev. 1.0 266 clock module motorola clock module to exit reset in pll mode, the reference must be present, and the pll must acquire lock. 11.8.5 clock operation during reset in external clock mode, the system is static and does not recognize reset until a clock is applied to extal. in pll mode, the pll operates in self-clocked mode (scm) during reset until the input reference clock to the pll begins operating within the limits given in the electrical specifications. if a pll failure causes a reset, the system enters reset using the reference clock. then the clock source changes to the pll operating in scm. if scm is not functional, the system becomes static. alternately, if the locen bit in syncr is clear when the pll fails, the system becomes static. if external reset is asserted, the system cannot enter reset unless the pll is capable of operating in scm. 11.8.6 pll operation in pll mode, the pll synthesizes the system clocks. the pll can multiply the reference clock frequency by 2x to 9x, provided that the system clock (clkout) frequency remains within the range listed in electrical specifications. for example, if the reference frequency is 2 mhz, the pll can synthesize frequencies of 4 mhz to 18 mhz. in addition, the rfd can reduce the system frequency by dividing the output of the pll. the rfd is not in the feedback loop of the pll, so changing the rfd divisor does not affect pll operation. figure 11-8 shows the external support circuitry for the crystal oscillator with example component values. actual component values depend on crystal specifications. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . clock module functional description mmc2114 MMC2113 mmc2112 ? rev. 1.0 advance information motorola clock module 267 figure 11-7. pll block diagram figure 11-8. crystal oscillator example stpmd pllen rstout mfd (2 ? 9) locks lock locs to reset module clkout pllsel disclk mdf[2:0] phase and frequency detect loss of clock detect lock detect charge pump filter vco rfd[2:0] scaled pll clock out pll clock out reference clock locen lolre pllmode locre v 66 v 666<1 extal xtal rs rf c1 c2 on-chip 8-mhz crystal configuration c1 = c2 = 16 pf rf = 1 m ? rs = 470 ? f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . advance information mmc2114 MMC2113 mmc2112 ? rev. 1.0 268 clock module motorola clock module 11.8.6.1 phase and frequency detector (pfd) the pfd is a dual-latch phase-frequency detector. it compares both the phase and frequency of the reference and feedback clocks. the reference clock comes from either the crystal oscillator or an external clock source. the feedback clock comes from: clkout in 1:1 pll mode, or vco output divided by two if clkout is disabled in 1:1 pll mode, or vco output divided by the mfd in normal pll mode when the frequency of the feedback clock equals the frequency of the reference clock, the pll is frequency-locked. if the falling edge of the feedback clock lags the falling edge of the reference clock, the pfd pulses the up signal. if the falling edge of the feedback clock leads the falling edge of the reference clock, the pfd pulses the down signal. the width of these pulses relative to the reference clock depends on how much the two clocks lead or lag each other. once phase lock is achieved, the pfd continues to pulse the up and down signals for very short durations during each reference clock cycle. these short pulses continually update the pll and prevent the frequency drift phenomenon known as dead-banding. 11.8.6.2 charge pump/loop filter in 1:1 pll mode, the charge pump uses a fixed current. in normal mode the current magnitude of the charge pump varies with the mfd as shown in table 11-9 . table 11-9. charge pump current and mfd in normal mode operation charge pump current mfd 1x 0 mfd < 2 2x 2 mfd < 6 4x 6 mfd f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . clock module reset mmc2114 MMC2113 mmc2112 ? rev. 1.0 advance information motorola clock module 269 the up and down signals from the pfd control whether the charge pump applies or removes charge, respectively, from the loop filter. the filter is integrated on the chip. 11.8.6.3 voltage control output (vco) the voltage across the loop filter controls the frequency of the vco output. the frequency-to-voltage relationship (vco gain) is positive, and the output frequency is four times the target system frequency. 11.8.6.4 multiplication factor divider (mfd) when the pll is not in 1:1 pll mode, the mfd divides the output of the vco and feeds it back to the pfd. the pfd controls the vco frequency via the charge pump and loop filter such that the reference and feedback clocks have the same frequency and phase. thus, the frequency of the input to the mfd, which is also the output of the vco, is the reference frequency multiplied by the same amount that the mfd divides by. for example, if the mfd divides the vco frequency by six, the pll is frequency locked when the vco frequency is six times the reference frequency. the presence of the mfd in the loop allows the pll to perform frequency multiplication, or synthesis. in 1:1 pll mode, the mfd is bypassed, and the effective multiplication factor is one. 11.9 reset the clock module can assert a reset when a loss of clock or loss of lock occurs as described in 11.8 functional description . reset initializes the clock module registers to a known startup state as described in 11.7 memory map and registers . 11.10 interrupts the clock module does not generate interrupt requests. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . advance information mmc2114 MMC2113 mmc2112 ? rev. 1.0 270 clock module motorola clock module f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . mmc2114 MMC2113 mmc2112 ? rev. 1.0 advance information motorola ports module 271 advance information ? mmc2114, MMC2113, and mmc2112 section 12. ports module 12.1 contents 12.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .272 12.3 signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .273 12.4 memory map and registers . . . . . . . . . . . . . . . . . . . . . . . . . .273 12.4.1 memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .274 12.4.2 register descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . .275 12.4.2.1 port output data registers . . . . . . . . . . . . . . . . . . . . . .275 12.4.2.2 port data direction registers. . . . . . . . . . . . . . . . . . . . .276 12.4.2.3 port pin data/set data registers . . . . . . . . . . . . . . . . .277 12.4.2.4 port clear output data registers . . . . . . . . . . . . . . . . .278 12.4.2.5 port c/d pin assignment register . . . . . . . . . . . . . . . . .279 12.4.2.6 port e pin assignment register. . . . . . . . . . . . . . . . . . .280 12.5 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .281 12.5.1 pin functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .282 12.5.2 port digital i/o timing . . . . . . . . . . . . . . . . . . . . . . . . . . . .283 12.6 interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .283 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . advance information mmc2114 MMC2113 mmc2112 ? rev. 1.0 272 ports module motorola ports module 12.2 introduction many of the pins associated with the external interface may be used for several different functions. their primary function is to provide an external interface to access off-chip resources. when not used for their primary functions, many of the pins may be used as general purpose digital input/output (i/o) pins. in some cases, the pin function is set by the operating mode, and the alternate pin functions are not supported. to facilitate the general purpose digital i/o function, these pins are grouped into 8-bit ports. each port has registers that configure the pins for the desired function, monitor the pins, and control the pins within the ports. figure 12-1. ports module block diagram cse[1:0] / pe[4:3] (1) shs / rcon / pe7 tc[2:0] / pe[2:0] (1) ta / pe6 tea / pe5 d[7:0] / pd[7:0] d[15:8] / pc[7:0] d[23:16] / pb[7:0] d[31:24] / pa[7:0] eb[3:0] / pi[7:4] (1) a[7:0] / ph[7:0] (1) a[15:8] / pg[7:0] (1) r/w / pf7 (1) a[22:16] / pf[6:0] (1) cs[3:0] / pi[3:0] (1) port e port d port c port b port a port i port h port g port f note 1. these pins are found only on the 144-pin package. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . ports module signals mmc2114 MMC2113 mmc2112 ? rev. 1.0 advance information motorola ports module 273 12.3 signals see table 12-3 in 12.5 functional description for signal location and naming convention. 12.4 memory map and registers the ports programming model consists of these registers: the port output data registers (portx) store the data to be driven on the corresponding port pins when the pins are configured for digital output. the port data direction registers (ddrx) control the direction of the port pin drivers when the pins are configured for digital i/o. port pin data/set data registers (portxp/setx): ? reflect the current state of the port pins ? allow for setting individual bits in portx the port clear output data registers (clrx) allow for clearing individual bits in portx. the port pin assignment registers (pcdpar and pepar) control the function of each pin of the c, d, e, i7, and i6 ports. in emulation mode, accesses to the port registers are ignored and the port access goes external so that emulation hardware can satisfy the port access request. the cycle termination is always provided by the port logic, even in emulation mode. all port registers are word-, half-word, and byte-accessible and are grouped to allow coherent access to port data register groups. writing to reserved bits in the port registers has no effect and reading returns 0s. the i/o ports have a base address of 0x00c0_0000. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . advance information mmc2114 MMC2113 mmc2112 ? rev. 1.0 274 ports module motorola ports module 12.4.1 memory map table 12-1. i/o port module memory map address bits 31 ? 24 bits 23 ? 16 bits 15 ? 8bits 7 ? 0 access (1) 0x00c0_0000 porta portb portc portd s/u 0x00c0_0004 porte portf portg porth s/u 0x00c0_0008 porti reserved (2) s/u 0x00c0_000c ddra ddrb ddrc ddrd s/u 0x00c0_0010 ddre ddrf ddrg ddrh s/u 0x00c0_0014 ddri reserved (2) s/u 0x00c0_0018 portap/seta portbp/setb portcp/setc portdp/setd s/u 0x00c0_001c portep/sete portfp/setf portgp/setg porthp/seth s/u 0x00c0_0020 portip/seti reserved (2) s/u 0x00c0_0024 clra clrb clrc clrd s/u 0x00c0_0028 clre clrf clrg clrh s/u 0x00c0_002c clri reserved (2) s/u 0x00c0_0030 pcdpar pepar reserved (2) s/u 0x00c0_0034 ? 0x00c0_003c reserved (2) s/u 1. s/u = cpu supervisor or user mode access. user mode accesses to supervisor only addresses have no effect and result in a cycle termination transfer error. 2. writes have no effect, reads return 0s, and the access terminates without a transfer error exception. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . ports module memory map and registers mmc2114 MMC2113 mmc2112 ? rev. 1.0 advance information motorola ports module 275 12.4.2 register descriptions this subsection provides a description of the i/o port registers. 12.4.2.1 port output data registers the port output data registers (portx) store the data to be driven on the corresponding port x pins when the pins are configured for digital output. reading portx returns the current value in the register, not the port x pin values. the setx and clrx registers also affect the portx register bits. to set bits in portx, write 1s to the corresponding bits in portxp/setx. to clear bits in portx, write 0s to the corresponding bits in clrx. portx are read/write registers when not in emulation mode. reset sets portx. address: 0x00c0_0000 ? porta 0x00c0_0001 ? port b 0x00c0_0002 ? portc 0x00c0_0003 ? portd 0x00c0_0004 ? porte 0x00c0_0005 ? portf 0x00c0_0006 ? portg 0x00c0_0007 ? porth 0x00c0_0008 ? porti 7654321bit 0 read: portx7 portx6 portx5 portx4 portx3 portx2 portx1 portx0 write: reset:11111111 figure 12-2. port output data registers (portx) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . advance information mmc2114 MMC2113 mmc2112 ? rev. 1.0 276 ports module motorola ports module 12.4.2.2 port data direction registers a port data direction registers (ddrx) control the direction of the port x pin drivers when the pins are configured for digital i/o. setting any bit in ddrx configures the corresponding port x pin as an output. clearing any bit in ddrx configures the corresponding pin as an input. when a pin is not configured for digital i/o, its corresponding data direction bit has no effect. ddrx are read/write registers when not in emulation mode. reset clears ddrx. ddrx[7:0] ? port x data direction bits 1 = pin configured as output 0 = pin configured as input address: 0x00c0_000c ? ddra 0x00c0_000d ? ddr b 0x00c0_000e ? ddrc 0x00c0_000f ? ddrd 0x00c0_0010 ? ddre 0x00c0_0011 ? ddrf 0x00c0_0012 ? ddrg 0x00c0_0013 ? ddrh 0x00c0_0014 ? ddri bit 7654321bit 0 read: ddrx7 ddrx6 ddrx5 ddrx4 ddrx3 ddrx2 ddrx1 ddrx0 write: reset:00000000 figure 12-3. port data direction registers (ddrx) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . ports module memory map and registers mmc2114 MMC2113 mmc2112 ? rev. 1.0 advance information motorola ports module 277 12.4.2.3 port pin data/set data registers reading a port pin data/set data register (portxp/setx) returns the current state of the port x pins. writing 1s to portxp/setx sets the corresponding bits in portx. writing 0s has no effect. portxp/setx are read/write registers when not in emulation mode. address: 0x00c0_0018 ? portap/seta 0x00c0_0019 ? portbp/setb 0x00c0_001a ? portcp/setc 0x00c0_001b ? portdp/setd 0x00c0_001c ? portep/sete 0x00c0_001d ? portfp/setf 0x00c0_001e ? portgp/setg 0x00c0_001f ? porthp/seth 0x00c0_0020 ? portip/seti bit 7654321bit 0 read: portxp7 portxp6 portxp5 portxp4 portxp3 portxp2 portxp1 portxp0 write: setx7 setx6 setx5 setx4 setx3 setx2 setx1 setx0 reset:pppppppp p = current pin state figure 12-4. port pin data/set data registers (portxp/setx) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . advance information mmc2114 MMC2113 mmc2112 ? rev. 1.0 278 ports module motorola ports module 12.4.2.4 port clear output data registers writing 0s to a port clear output data register (clrx) clears the corresponding bits in portx. writing 1s has no effect. reading clrx returns 0s. clrx are read/write registers when not in emulation mode. address: 0x00c0_0024 ? clra 0x00c0_0025 ? clrb 0x00c0_0026 ? clrc 0x00c0_0027 ? clrd 0x00c0_0028 ? clre 0x00c0_0029 ? clrf 0x00c0_002a ? clrg 0x00c0_002b ? clrh 0x00c0_002c ? clri bit 7654321bit 0 read: 0 0 000000 write: clrx7 clrx6 clrx5 clrx4 clrx3 clrx2 clrx1 clrx0 reset:00000000 figure 12-5. port clear output data registers (clrx) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . ports module memory map and registers mmc2114 MMC2113 mmc2112 ? rev. 1.0 advance information motorola ports module 279 12.4.2.5 port c/d pin assignment register the port c/d pin assignment register (pcdpar) controls the pin function of ports c, d, i7, and i6. pcdpar is a read/write register when not in emulation mode. pcdpa ? port c, d, i7, and i6 pin assignment bit 1 = port c, d, i7, and i6 pins configured for primary function 0 = port c, d, i7, and i6 pins configured for digital i/o address: 0x00c0_0030 bit 7654321bit 0 read: pcdpa 0000000 write: reset:see note0000000 = writes have no effect and the access terminates without a transfer error exception. note: reset state determined during reset configuration. pcdpa = 1 except in single-chip mode or when an external boot device is selected with a 16-bit port size in master mode. figure 12-6. port c, d, i7, and i6 pin assignment register (pcdpar) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . advance information mmc2114 MMC2113 mmc2112 ? rev. 1.0 280 ports module motorola ports module 12.4.2.6 port e pin assignment register the port e pin assignment register (pepar) controls the pin function of port e. pepar is a read/write register when not in emulation mode. pepa[7:0] ? port e pin assignment bits 1 = port e pins configured for primary function 0 = port e pins configured for digital i/o address: 0x00c0_0031 bit 7654321bit 0 read: pepa7 pepa6 pepa5 pepa4 pepa3 pepa2 pepa1 pepa0 write: reset: see note note: reset state determined during reset configuration as shown in table 12-2 . figure 12-7. port e pin assignment register (pepar) table 12-2. pepar reset values pepar pin master mode single-chip mode emulation mode pepa7 shs 10 1 pepa6 ta 10 1 pepa5 tea 10 1 pepa[4:3] cse[1:0] 0 0 1 pepa[2:0] tc[2:0] 0 0 1 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . ports module functional description mmc2114 MMC2113 mmc2112 ? rev. 1.0 advance information motorola ports module 281 12.5 functional description the initial pin function is determined during reset configuration (see section 4. chip configuration module (ccm) ). the pin assignment registers (pcdpar and pepar) allow the user to select between digital i/o or another pin function after reset. in single-chip mode, all pins are configured as digital i/o by default. every digital i/o pin is individually configurable as an input or an output via a data direction register (ddrx). every port has an output data register (portx) and a pin data register (portxp/setx) to monitor and control the state of its pins. data written to portx is stored and then driven to the corresponding portx pins configured as outputs. reading portx returns the current state of the register regardless of the state of the corresponding pins. reading portxp returns the current state of the corresponding pins, regardless of whether the pins are input or output. every port has a set register (portxp/setx) and a clear register (clrx) for setting or clearing individual bits in portx. in master mode and emulation mode, ports a and b function as the upper external data bus, d[31:16]. when the pcdpa bit is set, ports c and d function as the lower external data bus, d[15:0]. ports e ? i are configured to support external memory and emulation functions. in master mode, the function of eb[3:2] is determined by the pcdpa bit. the function of cs[3:0] is determined by the individual chip select enable (csenx) bits. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . advance information mmc2114 MMC2113 mmc2112 ? rev. 1.0 282 ports module motorola ports module 12.5.1 pin functions table 12-3. ports a ? i supported pin functions pin port master mode single-chip mode emulation mode (1) d[31:24] a d[31:24] (i/o) pa[7:0] (i/o) d[31:24] (i/o) d[23:16] b d[23:16] (i/o) pb[7:0](i/o) d[23:16](i/o) d[15:8] c d[15:8] (i/o) (pcdpa = 1) or pc[7:0] (i/o) (pcdpa = 0) pc[7:0] (i/o) (pcdpa = 0) (2) d[15:8] (i/o) (pcdpa = 1) d[7:0] d d[7:0] (i/o) (pcdpa = 1) or pd[7:0] (i/o) (pcdpa = 0) pd[7:0] (i/o) (pcdpa = 0) (2) d[7:0] (i/o) (pcdpa = 1) shs (3) e shs (o) (pepar7 = 1) or pe7 (i/o) (pepar7 = 0) pe7 (i/o) (pepar7 = 0) (4) shs (o) (pepar7 = 1) ta ta (i) (pepar6 = 1) or pe6 (i/o) (pepar6 = 0) pe6 (i/o) (pepar6 = 0) (4) ta (i) (pepar6 = 1) tea tea (i) (pepar5 = 1) or pe5 (i/o) (pepar5 = 0) pe5 (i/o) (pepar5 = 0) (4) tea (i) (pepar5 = 1) cse[1:0] cse[1:0] (o) (pepar[4:3] = 1) (5) or pe[4:3] (i/o) (pepar[4:3] = 0) pe[4:3] (i/o) (pepar[4:3] = 0) (4) cse[1:0] (o) (pepar[4:3] = 1) tc[2:0] tc[2:0] (o) (pepar[2:0] = 1) or pe[2:0] (i/o) (pepar[2:0] = 0) pe[2:0] (i/o) (pepar[2:0] = 0) (4) tc[2:0] (o) (pepar[2:0] = 1) r/w f r/w (o) pf7 (i/o) r/w (o) a[22:16] a[22:16] (o) pf[6:0] (i/o) a[22:16] (o) a[15:8] g a[15:8] (o) pg[7:0] (i/o) a[15:8] (o) a[7:0] h a[7:0] (o) ph[7:0] (i/o) a[7:0] (o) eb[3:2] i eb[3:2] (o) (pcdpa = 1) or pi[7:6] (i/o) (pcdpa = 0) pi[7:6] (i/o) (pcdpa = 0) (2) eb[3:2] (o) (pcdpa = 1) eb[1:0] eb[1:0] (o) pi[5:4] (i/o) eb[1:0] (o) cs[3:0] cs[3:0] (o) (csenx = 1) or pi[3:0] (i/o) (csenx = 0) pi[3:0] (i/o) (6) cs[3:0] (o) (6) 1. digital i/o pin function provided by port replacement unit. 2. writing pcdpa = 1 has an undefined pin operation for d[31:16] and eb[3:2] in single-chip mode. 3. this pin functions as the reset configuration override enable (rcon ) during reset. 4. writing pepax = 1 has an undefined pin operation for port e pins in single-chip mode. 5. writing pepax = 1 has an undefined pin operation for these port e pins in single-chip and master modes. 6. csenx has no effect on selecting cs[3:0] pin function in single-chip or emulation modes. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . ports module interrupts mmc2114 MMC2113 mmc2112 ? rev. 1.0 advance information motorola ports module 283 12.5.2 port digital i/o timing input data on all pins configured as digital i/o is synchronized to the rising edge of clkout. see figure 12-8 . figure 12-8. digital input timing data written to portx of any pin configured as a digital output is immediately driven to its respective pin. see figure 12-9 . figure 12-9. digital output timing 12.6 interrupts the ports module does not generate interrupt requests. clkout pin data input register pin clkout output data output pin register f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . advance information mmc2114 MMC2113 mmc2112 ? rev. 1.0 284 ports module motorola ports module f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . mmc2114 MMC2113 mmc2112 ? rev. 1.0 advance information motorola edge port module (eport) 285 advance information ? mmc2114, MMC2113, and mmc2112 section 13. edge port module (eport) 13.1 contents 13.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .285 13.3 low-power mode operation . . . . . . . . . . . . . . . . . . . . . . . . . .286 13.3.1 wait and doze modes . . . . . . . . . . . . . . . . . . . . . . . . . . . .286 13.3.2 stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .287 13.4 interrupt/general-purpose i/o pin descriptions . . . . . . . . . . .287 13.5 memory map and registers . . . . . . . . . . . . . . . . . . . . . . . . . .287 13.5.1 memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .287 13.5.2 registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .288 13.5.2.1 eport pin assignment register . . . . . . . . . . . . . . . . .288 13.5.2.2 eport data direction register. . . . . . . . . . . . . . . . . . .290 13.5.2.3 edge port interrupt enable register . . . . . . . . . . . . . . .291 13.5.2.4 edge port data register . . . . . . . . . . . . . . . . . . . . . . . .292 13.5.2.5 edge port pin data register . . . . . . . . . . . . . . . . . . . . .292 13.5.2.6 edge port flag register. . . . . . . . . . . . . . . . . . . . . . . . .293 13.2 introduction the edge port module (eport) has eight external interrupt pins. each pin can be configured individually as a low level-sensitive interrupt pin, an edge-detecting interrupt pin (rising edge, falling edge, or both), or a general-purpose input/output (i/o) pin. see figure 13-1 . f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . advance information mmc2114 MMC2113 mmc2112 ? rev. 1.0 286 edge port module (eport) motorola edge port module (eport) figure 13-1. eport block diagram 13.3 low-power mode operation this subsection describes the operation of the eport module in low-power modes. 13.3.1 wait and doze modes in wait and doze modes, the eport module continues to operate normally and may be configured to exit the low-power modes by generating an interrupt request on either a selected edge or a low level on an external pin. ipbus synchronizer epdr[n] epfr[n] eppar[2n, 2n + 1] epier[n] edge detect d0 stop logic eppdr[n] d1 q d0 d1 q mode epddr[n] to interrupt controller intx pin rising edge of clock f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . edge port module (eport) interrupt/general-purpose i/o pin descriptions mmc2114 MMC2113 mmc2112 ? rev. 1.0 advance information motorola edge port module (eport) 287 13.3.2 stop mode in stop mode, there are no clocks available to perform the edge-detect function. only the level-detect logic is active (if configured) to allow any low level on the external interrupt pin to generate an interrupt (if enabled) to exit stop mode. note: the input pin synchronizer is bypassed for the level-detect logic since no clocks are available. 13.4 interrupt/general-purpose i/o pin descriptions all pins default to general-purpose input pins at reset. the pin value is synchronized to the rising edge of clkout when read from the eport pin data register (eppdr). the values used in the edge/level detect logic are also synchronized to the rising edge of clkout. these pins use schmitt triggered input buffers which have built in hysteresis designed to decrease the probability of generating false edge-triggered interrupts for slow rising and falling input signals. 13.5 memory map and registers this subsection describes the memory map and register structure. 13.5.1 memory map refer to table 13-1 for a description of the eport memory map. the eport has a base address of 0x00c6_0000. table 13-1. edge port module memory map address bits 15 ? 8bits 7 ? 0 access (1) 0x00c6_0000 eport pin assignment register (eppar) s 0x00c6_0002 eport data direction register (epddr) eport interrupt enable register (epier) s 0x00c6_0004 eport data register (epdr) eport pin data register (eppdr) s/u 0x00c6_0006 eport flag register (epfr) reserved (2) s/u 1. s = cpu supervisor mode access only. s/u = cpu supervisor or user mode access. user mode accesses to supervisor only addresses have no effect and result in a cycle termination transfer error. 2. writing to reserved address locations has no effect, and reading returns 0s. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . advance information mmc2114 MMC2113 mmc2112 ? rev. 1.0 288 edge port module (eport) motorola edge port module (eport) 13.5.2 registers the eport programming model consists of these registers: the eport pin assignment register (eppar) controls the function of each pin individually. the eport data direction register (epddr) controls the direction of each one of the pins individually. the eport interrupt enable register (epier) enables interrupt requests for each pin individually. the eport data register (epdr) holds the data to be driven to the pins. the eport pin data register (eppdr) reflects the current state of the pins. the eport flag register (epfr) individually latches eport edge events. 13.5.2.1 eport pin assignment register address: 0x00c6_0000 and 0x00c6_0001 bit 15 14 13 12 11 10 9 bit 8 read: eppa7 eppa6 eppa5 eppa4 write: reset:00000000 bit 7654321bit 0 read: eppa3 eppa2 eppa1 eppa0 write: reset:00000000 figure 13-2. eport pin assignment register (eppar) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . edge port module (eport) memory map and registers mmc2114 MMC2113 mmc2112 ? rev. 1.0 advance information motorola edge port module (eport) 289 eppa[7:0] ? eport pin assignment select fields the read/write eppax fields configure eport pins for level detection and rising and/or falling edge detection as table 13-2 shows. pins configured as level-sensitive are inverted so that a logic 0 on the external pin represents a valid interrupt request. level-sensitive interrupt inputs are not latched. to guarantee that a level-sensitive interrupt request is acknowledged, the interrupt source must keep the signal asserted until acknowledged by software. level sensitivity must be selected to bring the device out of stop mode with an intx interrupt. pins configured as edge-triggered are latched and need not remain asserted for interrupt generation. a pin configured for edge detection is monitored regardless of its configuration as input or output. interrupt requests generated in the eport module can be masked by the interrupt controller module. eppar functionality is independent of the selected pin direction. reset clears the eppax fields. table 13-2. eppax field settings eppax pin configuration 00 pin intx level-sensitive 01 pin intx rising edge triggered 10 pin intx falling edge triggered 11 pin intx both falling edge and rising edge triggered f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . advance information mmc2114 MMC2113 mmc2112 ? rev. 1.0 290 edge port module (eport) motorola edge port module (eport) 13.5.2.2 eport data direction register epdd[7:0] ? edge port data direction bits setting any bit in the epddr configures the corresponding pin as an output. clearing any bit in epddr configures the corresponding pin as an input. pin direction is independent of the level/edge detection configuration. reset clears epdd[7:0]. to use an eport pin as an external interrupt request source, its corresponding bit in epddr must be clear. software can generate interrupt requests by programming the eport data register when the epddr selects output. 1 = corresponding eport pin configured as output 0 = corresponding eport pin configured as input address: 0x00c6_0002 bit 7654321bit 0 read: epdd7 epdd6 epdd5 epdd4 epdd3 epdd2 epdd1 epdd0 write: reset:00000000 figure 13-3. eport data direction register (epddr) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . edge port module (eport) memory map and registers mmc2114 MMC2113 mmc2112 ? rev. 1.0 advance information motorola edge port module (eport) 291 13.5.2.3 edge port interrupt enable register epie[7:0] ? edge port interrupt enable bits the read/write epie[7:0] bits enable eport interrupt requests. if a bit in epier is set, eport generates an interrupt request when: the corresponding bit in the eport flag register (epfr) is set or later becomes set, or the corresponding pin level is low and the pin is configured for level-sensitive operation clearing a bit in epier negates any interrupt request from the corresponding eport pin. reset clears epie[7:0]. 1 = interrupt requests from corresponding eport pin enabled 0 = interrupt requests from corresponding eport pin disabled address: 0x00c6_0003 bit 7654321bit 0 read: epie7 epie6 epie5 epie4 epie3 epie2 epie1 epie0 write: reset:00000000 figure 13-4. eport port interrupt enable register (epier) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . advance information mmc2114 MMC2113 mmc2112 ? rev. 1.0 292 edge port module (eport) motorola edge port module (eport) 13.5.2.4 edge port data register epd[7:0] ? edge port data bits data written to epdr is stored in an internal register; if any pin of the port is configured as an output, the bit stored for that pin is driven onto the pin. reading edpr returns the data stored in the register. reset sets epd[7:0]. 13.5.2.5 edge port pin data register eppd[7:0] ? edge port pin data bits the read-only eppdr reflects the current state of the eport pins. writing to eppdr has no effect, and the write cycle terminates normally. reset does not affect eppdr. address: 0x00c6_0004 bit 7654321bit 0 read: epd7 epd6 epd5 epd4 epd3 epd2 epd1 epd0 write: reset:11111111 figure 13-5. eport port data register (epdr) address: 0x00c6_0005 bit 7654321bit 0 read: eppd7 eppd6 eppd5 eppd4 eppd3 eppd2 eppd1 eppd0 write: reset:pppppppp = writes have no effect and the access terminates without a transfer error exception. p = current pin state figure 13-6. eport port pin data register (eppdr) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . edge port module (eport) memory map and registers mmc2114 MMC2113 mmc2112 ? rev. 1.0 advance information motorola edge port module (eport) 293 13.5.2.6 edge port flag register epf[7:0] ? edge port flag bits when an eport pin is configured for edge triggering, its corresponding read/write bit in epfr indicates that the selected edge has been detected. reset clears epf[7:0]. 1 = selected edge for intx pin has been detected. 0 = selected edge for intx pin has not been detected. bits in this register are set when the selected edge is detected on the corresponding pin. a bit remains set until cleared by writing a 1 to it. writing 0 has no effect. if a pin is configured as level-sensitive (epparx = 00), pin transitions do not affect this register. address: 0x00c6_0006 bit 7654321bit 0 read: epf7 epf6 epf5 epf4 epf3 epf2 epf1 epf0 write: reset:00000000 figure 13-7. eport port flag register (epfr) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . advance information mmc2114 MMC2113 mmc2112 ? rev. 1.0 294 edge port module (eport) motorola edge port module (eport) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . mmc2114 MMC2113 mmc2112 ? rev. 1.0 advance information motorola watchdog timer module 295 advance information ? mmc2114, MMC2113, and mmc2112 section 14. watchdog timer module 14.1 contents 14.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .295 14.3 modes of operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .296 14.3.1 wait mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .296 14.3.2 doze mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .296 14.3.3 stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .296 14.3.4 debug mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .296 14.4 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .297 14.5 signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .297 14.6 memory map and registers . . . . . . . . . . . . . . . . . . . . . . . . . .298 14.6.1 memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .298 14.6.2 registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .298 14.6.2.1 watchdog control register . . . . . . . . . . . . . . . . . . . . . .299 14.6.2.2 watchdog modulus register . . . . . . . . . . . . . . . . . . . . .301 14.6.2.3 watchdog count register . . . . . . . . . . . . . . . . . . . . . . .302 14.6.2.4 watchdog service register . . . . . . . . . . . . . . . . . . . . . .303 14.2 introduction the watchdog timer is a 16-bit timer used to help software recover from runaway code. the watchdog timer has a free-running down-counter (watchdog counter) that generates a reset on underflow. to prevent a reset, software must periodically restart the countdown by servicing the watchdog. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . advance information mmc2114 MMC2113 mmc2112 ? rev. 1.0 296 watchdog timer module motorola watchdog timer module 14.3 modes of operation this subsection describes the operation of the watchdog timer in low-power modes and debug mode of operation. 14.3.1 wait mode in wait mode with the wait bit set in the watchdog control register (wcr), watchdog timer operation stops. in wait mode with the wait bit clear, the watchdog timer continues to operate normally. 14.3.2 doze mode in doze mode with the doze bit set in wcr, watchdog timer module operation stops. in doze mode with the doze bit clear, the watchdog timer continues to operate normally. 14.3.3 stop mode the watchdog operation stops in stop mode. when stop mode is exited, the watchdog operation continues operation from the state it was in prior to entering stop mode. 14.3.4 debug mode in debug mode with the dbg bit set in wcr, watchdog timer module operation stops. in debug mode with the dbg bit clear, the watchdog timer continues to operate normally. when debug mode is exited, watchdog timer operation continues from the state it was in before entering debug mode, but any updates made in debug mode remain. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . watchdog timer module block diagram mmc2114 MMC2113 mmc2112 ? rev. 1.0 advance information motorola watchdog timer module 297 14.4 block diagram figure 14-1. watchdog timer block diagram 14.5 signals the watchdog timer module has no off-chip signals. 16-bit wmr 16-bit watchdog counter count = 0 system divide by reset clock ipbus 4096 16-bit wcntr 16-bit wsr ipbus load counter en wait doze dbg f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . advance information mmc2114 MMC2113 mmc2112 ? rev. 1.0 298 watchdog timer module motorola watchdog timer module 14.6 memory map and registers this subsection describes the memory map and registers for the watchdog timer. the watchdog timer has a base address of 0x00c7_0000. 14.6.1 memory map refer to table 14-1 for an overview of the watchdog memory map. 14.6.2 registers the watchdog timer programming model consists of these registers: the watchdog control register (wcr) configures watchdog timer operation. see 14.6.2.1 watchdog control register . the watchdog modulus register (wmr) determines the timer modulus reload value. see 14.6.2.2 watchdog modulus register . the watchdog count register (wcntr) provides visibility to the watchdog counter value. see 14.6.2.3 watchdog count register . the watchdog service register (wsr) requires a service sequence to prevent reset. see 14.6.2.4 watchdog service register . table 14-1. watchdog timer module memory map address bits 15 ? 8bits 7 ? 0 access (1) 1. s = cpu supervisor mode access only. s/u = cpu supervisor or user mode access. user mode accesses to supervisor only addresses have no effect and result in a cycle termina- tion transfer error. 0x00c7_0000 watchdog control register (wcr) s 0x00c7_0002 watchdog modulus register (wmr) s 0x00c7_0004 watchdog count register (wcntr) s/u 0x00c7_0006 watchdog service register (wsr) s/u f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . watchdog timer module memory map and registers mmc2114 MMC2113 mmc2112 ? rev. 1.0 advance information motorola watchdog timer module 299 14.6.2.1 watchdog control register the 16-bit read/write watchdog control register (wcr) configures watchdog timer operation. wait ? wait mode bit the read-always, write-once wait bit controls the function of the watchdog timer in wait mode. once written, the wait bit is not affected by further writes except in debug mode. reset sets wait. 1 = watchdog timer stopped in wait mode 0 = watchdog timer not affected in wait mode doze ? doze mode bit the read-always, write-once doze bit controls the function of the watchdog timer in doze mode. once written, the doze bit is not affected by further writes except in debug mode. reset sets doze. 1 = watchdog timer stopped in doze mode 0 = watchdog timer not affected in doze mode address: 0x00c7_0000 and 0x00c7_0001 bit 15 14 13 12 11 10 9 bit 8 read: 00000000 write: reset:00000000 bit 7654321bit 0 read: 0000 wait doze dbg en write: reset:00001111 = writes have no effect and the access terminates without a transfer error exception. figure 14-2. watchdog control register (wcr) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . advance information mmc2114 MMC2113 mmc2112 ? rev. 1.0 300 watchdog timer module motorola watchdog timer module dbg ? debug mode bit the read-always, write-once dbg bit controls the function of the watchdog timer in debug mode. once written, the dbg bit is not affected by further writes except in debug mode. during debug mode, watchdog timer registers can be written and read normally. when debug mode is exited, timer operation continues from the state it was in before entering debug mode, but any updates made in debug mode remain. if a write-once register is written for the first time in debug mode, the register is still writable when debug mode is exited. 1 = watchdog timer stopped in debug mode 0 = watchdog timer not affected in debug mode note: changing the dbg bit from 1 to 0 during debug mode starts the watchdog timer. changing the dbg bit from 0 to 1 during debug mode stops the watchdog timer. en ? watchdog enable bit the read-always, write-once en bit enables the watchdog timer. once written, the en bit is not affected by further writes except in debug mode. when the watchdog timer is disabled, the watchdog counter and prescaler counter are held in a stopped state. 1 = watchdog timer enabled 0 = watchdog timer disabled f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . watchdog timer module memory map and registers mmc2114 MMC2113 mmc2112 ? rev. 1.0 advance information motorola watchdog timer module 301 14.6.2.2 watchdog modulus register wm[15:0] ? watchdog modulus field the read-always, write-once wm[15:0] field contains the modulus that is reloaded into the watchdog counter by a service sequence. once written, the wm[15:0] field is not affected by further writes except in debug mode. writing to wmr immediately loads the new modulus value into the watchdog counter. the new value is also used at the next and all subsequent reloads. reading wmr returns the value in the modulus register. reset initializes the wm[15:0] field to 0xffff. note: the prescaler counter is reset anytime a new value is loaded into the watchdog counter and also during reset. address: 0x00c7_0002 and 0x00c7_0003 bit 15 14 13 12 11 10 9 bit 8 read: wm15 wm14 wm13 wm12 wm11 wm10 wm9 wm8 write: reset:11111111 bit 7654321bit 0 read: wm7 wm6 wm5 wm4 wm3 wm2 wm1 wm0 write: reset:11111111 figure 14-3. watchdog modulus register (wmr) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . advance information mmc2114 MMC2113 mmc2112 ? rev. 1.0 302 watchdog timer module motorola watchdog timer module 14.6.2.3 watchdog count register wc[15:0] ? watchdog count field the read-only wc[15:0] field reflects the current value in the watchdog counter. reading the 16-bit wcntr with two 8-bit reads is not guaranteed to return a coherent value. writing to wcntr has no effect, and write cycles are terminated normally. address: 0x00c7_0004 and 0x00c7_0005 bit 15 14 13 12 11 10 9 bit 8 read: wc15 wc14 wc13 wc12 wc11 wc10 wc9 wc8 write: reset:11111111 bit 7654321bit 0 read: wc7 wc6 wc5 wc4 wc3 wc2 wc1 wc0 write: reset:11111111 = writes have no effect and the access terminates without a transfer error exception. figure 14-4. watchdog count register (wcntr) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . watchdog timer module memory map and registers mmc2114 MMC2113 mmc2112 ? rev. 1.0 advance information motorola watchdog timer module 303 14.6.2.4 watchdog service register when the watchdog timer is enabled, writing 0x5555 and then 0xaaaa to the watchdog service register (wsr) before the watchdog counter times out prevents a reset. if wsr is not serviced before the timeout, the watchdog timer sends a signal to the reset controller module which sets the wdr bit and asserts a system reset. both writes must occur in the order listed before the timeout, but any number of instructions can be executed between the two writes. however, writing any value other than 0x5555 or 0xaaaa to wsr resets the servicing sequence, requiring both values to be written to keep the watchdog timer from causing a reset. address: 0x00c7_0006 and 0x00c7_0007 bit 15 14 13 12 11 10 9 bit 8 read: ws15 ws14 ws13 ws12 ws11 ws10 ws9 ws8 write: reset:00000000 bit 7654321bit 0 read: ws7 ws6 ws5 ws4 ws3 ws2 ws1 ws0 write: reset:00000000 figure 14-5. watchdog service register (wsr) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . advance information mmc2114 MMC2113 mmc2112 ? rev. 1.0 304 watchdog timer module motorola watchdog timer module f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . mmc2114 MMC2113 mmc2112 ? rev. 1.0 advance information motorola programmable interrupt timer modules (pit1 and pit2) 305 advance information ? mmc2114, MMC2113, and mmc2112 section 15. programmable interrupt timer modules (pit1 and pit2) 15.1 contents 15.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .306 15.3 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .306 15.4 modes of operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .307 15.4.1 wait mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .307 15.4.2 doze mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .307 15.4.3 stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .307 15.4.4 debug mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .307 15.5 signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .307 15.6 memory map and registers . . . . . . . . . . . . . . . . . . . . . . . . . .308 15.6.1 memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .308 15.6.2 registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .308 15.6.2.1 pit control and status register . . . . . . . . . . . . . . . . . .309 15.6.2.2 pit modulus register . . . . . . . . . . . . . . . . . . . . . . . . . .312 15.6.2.3 pit count register . . . . . . . . . . . . . . . . . . . . . . . . . . . .313 15.7 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .314 15.7.1 set-and-forget timer operation . . . . . . . . . . . . . . . . . . . .314 15.7.2 free-running timer operation . . . . . . . . . . . . . . . . . . . . .315 15.7.3 timeout specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . .315 15.8 interrupt operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .316 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . advance information mmc2114 MMC2113 mmc2112 ? rev. 1.0 306 programmable interrupt timer modules (pit1 and pit2) motorola programmable interrupt timer modules (pit1 and pit2) 15.2 introduction the programmable interrupt timer (pit) is a 16-bit timer that provides precise interrupts at regular intervals with minimal processor intervention. the timer can either count down from the value written in the modulus latch, or it can be a free-running down-counter. this device has two programmable interrupt timers. pit1 has a base address located at 0x00c8_0000. pit2 base address is 0x00c9_0000. 15.3 block diagram figure 15-1. pit block diagram 16-bit pmr 16-bit pit counter count = 0 system clock ipbus 16-bit pcntr ipbus en ovw pdoze pdbg prescaler pre[3:0] rld pif pie load counter to interrupt controller f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . programmable interrupt timer modules (pit1 and pit2) modes of operation mmc2114 MMC2113 mmc2112 ? rev. 1.0 advance information motorola programmable interrupt timer modules (pit1 and pit2) 307 15.4 modes of operation this subsection describes the three low-power modes and the debug mode. 15.4.1 wait mode in wait mode, the pit module continues to operate normally and can be configured to exit the low-power mode by generating an interrupt request. 15.4.2 doze mode in doze mode with the pdoze bit set in the pit control and status register (pcsr), pit module operation stops. in doze mode with the pdoze bit clear, doze mode does not affect pit operation. when doze mode is exited, pit operation continues from the state it was in before entering doze mode. 15.4.3 stop mode in stop mode, the system clock is absent, and pit module operation stops. 15.4.4 debug mode in debug mode with the pdbg bit set in pcsr, pit module operation stops. in debug mode with the pdbg bit clear, debug mode does not affect pit operation. when debug mode is exited, pit operation continues from the state it was in before entering debug mode, but any updates made in debug mode remain. 15.5 signals the pit module has no off-chip signals. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . advance information mmc2114 MMC2113 mmc2112 ? rev. 1.0 308 programmable interrupt timer modules (pit1 and pit2) motorola programmable interrupt timer modules (pit1 and pit2) 15.6 memory map and registers this subsection describes the memory map and register structure for pit1 and pit2. 15.6.1 memory map refer to table 15-1 for a description of the memory map. this device has two programmable interrupt timers. pit1 has a base address located at 0x00c8_0000. pit2 base address is 0x00c9_0000. 15.6.2 registers the pit programming model consists of these registers: the pit control and status register (pcsr) configures the timer ? s operation. see 15.6.2.1 pit control and status register . the pit modulus register (pmr) determines the timer modulus reload value. see 15.6.2.2 pit modulus register . the pit count register (pcntr) provides visibility to the counter value. see 15.6.2.3 pit count register . table 15-1. programmable interrupt timer modules memory map pit1 address pit2 address bits 15 ? 8bits 7 ? 0 access (1) 0x00c8_0000 0x00c9_0000 pit control and status register (pcsr) s 0x00c8_0002 0x00c9_0002 pit modulus register (pmr) s 0x00c8_0004 0x00c9_0004 pit count register (pcntr) s/u 0x00c8_0006 0x00c9_0006 unimplemented (2) ? 1. s = cpu supervisor mode access only. s/u = cpu supervisor or user mode access. user mode accesses to supervisor only addresses have no effect and result in a cycle termination transfer error. 2. accesses to unimplemented address locations have no effect and result in a cycle termination transfer error. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . programmable interrupt timer modules (pit1 and pit2) memory map and registers mmc2114 MMC2113 mmc2112 ? rev. 1.0 advance information motorola programmable interrupt timer modules (pit1 and pit2) 309 15.6.2.1 pit control and status register pre[3:0] ? prescaler bits the read/write pre[3:0] bits select the system clock divisor to generate the pit clock as table 15-2 shows. to accurately predict the timing of the next count, change the pre[3:0] bits only when the enable bit (en) is clear. changing the pre[3:0] resets the prescaler counter. system reset and the loading of a new value into the counter also reset the prescaler counter. setting the en bit and writing to pre[3:0] can be done in this same write cycle. clearing the en bit stops the prescaler counter. pdoze ? doze mode bit the read/write pdoze bit controls the function of the pit in doze mode. reset clears pdoze. 1 = pit function stopped in doze mode 0 = pit function not affected in doze mode when doze mode is exited, timer operation continues from the state it was in before entering doze mode. address: pit1 ? 0x00c8_0000 and 0x00c8_0001 pit2 ? 0x00c9_0000 and 0x00c9_0001 bit 15 14 13 12 11 10 9 bit 8 read: 0000 pre3 pre2 pre1 pre0 write: reset:00000000 bit 7654321bit 0 read: 0 pdoze pdbg ovw pie pif rld en write: reset:00000000 = writes have no effect and the access terminates without a transfer error exception. figure 15-2. pit control and status register (pcsr) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . advance information mmc2114 MMC2113 mmc2112 ? rev. 1.0 310 programmable interrupt timer modules (pit1 and pit2) motorola programmable interrupt timer modules (pit1 and pit2) pdbg ? debug mode bit the read/write pdbg bit controls the function of the pit in debug mode. reset clears pdbg. 1 = pit function stopped in debug mode 0 = pit function not affected in debug mode during debug mode, register read and write accesses function normally. when debug mode is exited, timer operation continues from the state it was in before entering debug mode, but any updates made in debug mode remain. note: changing the pdbg bit from 1 to 0 during debug mode starts the pit timer. likewise, changing the pdbg bit from 0 to 1 during debug mode stops the pit timer. table 15-2. prescaler select encoding pre[3:0] system clock divisor 0000 1 0001 2 0010 4 0011 8 0100 16 0101 32 0110 64 0111 128 1000 256 1001 512 1010 1,024 1011 2,048 1100 4,096 1101 8,192 1110 16,384 1111 32,768 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . programmable interrupt timer modules (pit1 and pit2) memory map and registers mmc2114 MMC2113 mmc2112 ? rev. 1.0 advance information motorola programmable interrupt timer modules (pit1 and pit2) 311 ovw ? overwrite bit the read/write ovw bit enables writing to pmr to immediately overwrite the value in the pit counter. 1 = writing pmr immediately replaces value in pit counter. 0 = value in pmr replaces value in pit counter when count reaches 0x0000. pie ? pit interrupt enable bit the read/write pie bit enables the pif flag to generate interrupt requests. 1 = pif interrupt requests enabled 0 = pif interrupt requests disabled pif ? pit interrupt flag the read/write pif flag is set when the pit counter reaches 0x0000. clear pif by writing a 1 to it or by writing to pmr. writing 0 has no effect. reset clears pif. 1 = pit count has reached 0x0000. 0 = pit count has not reached 0x0000. rld ? reload bit the read/write rld bit enables loading the value of pmr into the pit counter when the count reaches 0x0000. 1 = counter reloaded from pmr on count of 0x0000 0 = counter rolls over to 0xffff on count of 0x0000 en ? pit enable bit the read/write en bit enables pit operation. when the pit is disabled, the counter and prescaler are held in a stopped state. 1 = pit enabled 0 = pit disabled f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . advance information mmc2114 MMC2113 mmc2112 ? rev. 1.0 312 programmable interrupt timer modules (pit1 and pit2) motorola programmable interrupt timer modules (pit1 and pit2) 15.6.2.2 pit modulus register the 16-bit read/write pit modulus register (pmr) contains the timer modulus value for loading into the pit counter when the count reaches 0x0000 and the rld bit is set. when the ovw bit is set, pmr is transparent, and the value written to pmr is immediately loaded into the pit counter. the prescaler counter is reset anytime a new value is loaded into the pit counter and also during reset. reading the pmr returns the value written in the modulus latch. reset initializes pmr to 0xffff. address: pit1 ? 0x00c8_0002 and 0x00c8_0003 pit2 ? 0x00c9_0002 and 0x00c9_0003 bit 15 14 13 12 11 10 9 bit 8 read: pm15 pm14 pm13 pm12 pm11 pm10 pm9 pm8 write: reset:11111111 bit 7654321bit 0 read: pm7pm6pm5pm4pm3pm2pm1pm0 write: reset:11111111 figure 15-3. pit modulus register (pmr) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . programmable interrupt timer modules (pit1 and pit2) memory map and registers mmc2114 MMC2113 mmc2112 ? rev. 1.0 advance information motorola programmable interrupt timer modules (pit1 and pit2) 313 15.6.2.3 pit count register the 16-bit, read-only pit control register (pcntr) contains the counter value. reading the 16-bit counter with two 8-bit reads is not guaranteed to be coherent. writing to pcntr has no effect, and write cycles are terminated normally. address: pit1 ? 0x00c8_0004 and 0x00c8_0005 pit2 ? 0x00c9_0004 and 0x00c9_0005 bit 15 14 13 12 11 10 9 bit 8 read: pc15 pc14 pc13 pc12 pc11 pc10 pc9 pc8 write: reset:11111111 bit 7654321bit 0 read: pc7 pc6 pc5 pc4 pc3 pc2 pc1 pc0 write: reset:11111111 = writes have no effect and the access terminates without a transfer error exception. figure 15-4. pit count register (pcntr) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . advance information mmc2114 MMC2113 mmc2112 ? rev. 1.0 314 programmable interrupt timer modules (pit1 and pit2) motorola programmable interrupt timer modules (pit1 and pit2) 15.7 functional description this subsection describes the pit functional operation. 15.7.1 set-and-forget timer operation this mode of operation is selected when the rld bit in the pcsr register is set. when the pit counter reaches a count of 0x0000, the pif flag is set in pcsr. the value in the modulus latch is loaded into the counter, and the counter begins decrementing toward 0x0000. if the pie bit is set in pcsr, the pif flag issues an interrupt request to the cpu. when the ovw bit is set in pcsr, the counter can be directly initialized by writing to pmr without having to wait for the count to reach 0x0000. figure 15-5. counter reloading from the modulus latch 0x0002 0x0001 0x0000 0x0005 0x0005 pit clock counter modulus pif f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . programmable interrupt timer modules (pit1 and pit2) functional description mmc2114 MMC2113 mmc2112 ? rev. 1.0 advance information motorola programmable interrupt timer modules (pit1 and pit2) 315 15.7.2 free-running timer operation this mode of operation is selected when the rld bit in pcsr is clear. in this mode, the counter rolls over from 0x0000 to 0xffff without reloading from the modulus latch and continues to decrement. when the counter reaches a count of 0x0000, the pif flag is set in pcsr. if the pie bit is set in pcsr, the pif flag issues an interrupt request to the cpu. when the ovw bit is set in pcsr, the counter can be directly initialized by writing to pmr without having to wait for the count to reach 0x0000. figure 15-6. counter in free-running mode 15.7.3 timeout specifications the 16-bit pit counter and prescaler supports different timeout periods. the prescaler divides the system clock as selected by the pre[3:0] bits in pcsr. the pm[15:0] bits in pmr select the timeout period. timeout period = pre[3:0] (pm[15:0] + 1) clocks 0x0002 0x0001 0x0000 0xffff 0x0005 pit clock counter modulus pif f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . advance information mmc2114 MMC2113 mmc2112 ? rev. 1.0 316 programmable interrupt timer modules (pit1 and pit2) motorola programmable interrupt timer modules (pit1 and pit2) 15.8 interrupt operation table 15-3 lists the interrupt requests generated by the pit. the pif flag is set when the pit counter reaches 0x0000. the pie bit enables the pif flag to generate interrupt requests. clear pif by writing a 1 to it or by writing to the pmr. table 15-3. pit interrupt requests interrupt request flag enable bit timeout pif pie f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . mmc2114 MMC2113 mmc2112 ? rev. 1.0 advance information motorola timer modules (tim1 and tim2) 317 advance information ? mmc2114, MMC2113, and mmc2112 section 16. timer modules (tim1 and tim2) 16.1 contents 16.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .319 16.3 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .319 16.4 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .320 16.5 modes of operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .321 16.5.1 supervisor and user modes. . . . . . . . . . . . . . . . . . . . . . . .321 16.5.2 run mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .321 16.5.3 stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .321 16.5.4 wait, doze, and debug modes . . . . . . . . . . . . . . . . . . . . .321 16.5.5 test mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .322 16.6 signal description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .322 16.6.1 icoc[2:0] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .322 16.6.2 icoc3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 322 16.7 memory map and registers . . . . . . . . . . . . . . . . . . . . . . . . . .323 16.7.1 timer input capture/output compare select register . . .324 16.7.2 timer compare force register . . . . . . . . . . . . . . . . . . . . .325 16.7.3 timer output compare 3 mask register . . . . . . . . . . . . . .326 16.7.4 timer output compare 3 data register. . . . . . . . . . . . . . .327 16.7.5 timer counter registers . . . . . . . . . . . . . . . . . . . . . . . . . .328 16.7.6 timer system control register 1 . . . . . . . . . . . . . . . . . . . .329 16.7.7 timer toggle-on-overflow register . . . . . . . . . . . . . . . . .330 16.7.8 timer control register 1 . . . . . . . . . . . . . . . . . . . . . . . . . .331 16.7.9 timer control register 2 . . . . . . . . . . . . . . . . . . . . . . . . . .332 16.7.10 timer interrupt enable register . . . . . . . . . . . . . . . . . . . . .333 16.7.11 timer system control register 2 . . . . . . . . . . . . . . . . . . . .334 16.7.12 timer flag register 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . .336 16.7.13 timer flag register 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . .337 16.7.14 timer channel registers . . . . . . . . . . . . . . . . . . . . . . . . . .338 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . advance information mmc2114 MMC2113 mmc2112 ? rev. 1.0 318 timer modules (tim1 and tim2) motorola timer modules (tim1 and tim2) 16.7.15 pulse accumulator control register . . . . . . . . . . . . . . . . . 339 16.7.16 pulse accumulator flag register . . . . . . . . . . . . . . . . . . . .341 16.7.17 pulse accumulator counter registers . . . . . . . . . . . . . . . .342 16.7.18 timer port data register . . . . . . . . . . . . . . . . . . . . . . . . . .343 16.7.19 timer port data direction register . . . . . . . . . . . . . . . . . .344 16.7.20 timer test register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .345 16.8 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .345 16.8.1 prescaler . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .345 16.8.2 input capture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .345 16.8.3 output compare . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .346 16.8.4 pulse accumulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .347 16.8.4.1 event counter mode . . . . . . . . . . . . . . . . . . . . . . . . . . .347 16.8.4.2 gated time accumulation mode . . . . . . . . . . . . . . . . . .348 16.8.5 general-purpose i/o ports. . . . . . . . . . . . . . . . . . . . . . . . .349 16.9 reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 351 16.10 interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .351 16.10.1 timer channel interrupts (cxf) . . . . . . . . . . . . . . . . . . . . .351 16.10.2 pulse accumulator overflow (paovf). . . . . . . . . . . . . . . .352 16.10.3 pulse accumulator input (paif) . . . . . . . . . . . . . . . . . . . . .352 16.10.4 timer overflow (tof) . . . . . . . . . . . . . . . . . . . . . . . . . . . .352 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . timer modules (tim1 and tim2) introduction mmc2114 MMC2113 mmc2112 ? rev. 1.0 advance information motorola timer modules (tim1 and tim2) 319 16.2 introduction the mmc2114, MMC2113 and mmc2112 have two 4-channel timer modules (tim1 and tim2). each consists of a 16-bit programmable counter driven by a 7-stage programmable prescaler. each of the four timer channels can be configured for input capture or output compare. additionally, one of the channels, channel 3, can be configured as a pulse accumulator. a timer overflow function allows software to extend the timing capability of the system beyond the 16-bit range of the counter. the input capture and output compare functions allow simultaneous input waveform measurements and output waveform generation. the input capture function can capture the time of a selected transition edge. the output compare function can generate output waveforms and timer software delays. the 16-bit pulse accumulator can operate as a simple event counter or a gated time accumulator. the pulse accumulator shares timer channel 3 when in event mode. 16.3 features features of the timer include: four 16-bit input capture/output compare channels 16-bit architecture programmable prescaler pulse widths variable from microseconds to seconds single 16-bit pulse accumulator toggle-on-overflow feature for pulse-width modulator (pwm) generation f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . advance information mmc2114 MMC2113 mmc2112 ? rev. 1.0 320 timer modules (tim1 and tim2) motorola timer modules (tim1 and tim2) 16.4 block diagram figure 16-1. timer block diagram prescaler channel 0 pt0 16-bit counter system logic pr[2:0] divide-by-64 module clock timc0h:timc0l edge detect timpacnth:timpacntl paovf pedge paovi pamod pae 16-bit comparator timcnth:timcntl 16-bit latch channel 1 timc1h:timc1l 16-bit comparator 16-bit latch 16-bit counter interrupt logic tof toi c0f c1f edge detect pt1 logic edge detect cxf channel 2 channel3 timc3h:timc3l 16-bit comparator 16-bit latch c3f pt3 logic edge detect ios0 ios1 ios3 om:ol0 tov0 om:ol1 tov1 om:ol3 tov3 edg1a edg1b edg3a edg3b edg0a edg0b tcre channel 3 output compare paif clear counter paif pai interrupt logic cxi interrupt request interrupt request paovf ch. 3 compare ch.3 capture ch. 1 capture mux clk[1:0] paclk paclk/256 paclk/65536 paclk paclk/256 paclk/65536 te clock ch. 1 compare ch. 0 compare ch. 0 capture pa input mux icoc0 pin icoc1 pin icoc3 pin f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . timer modules (tim1 and tim2) modes of operation mmc2114 MMC2113 mmc2112 ? rev. 1.0 advance information motorola timer modules (tim1 and tim2) 321 16.5 modes of operation this subsection describes the supervisor and user modes, the five low-power options, and test mode. 16.5.1 supervisor and user modes the so bit in the chip-select control register determines whether the processor is operating in user mode or supervisor mode. accessing supervisor address locations while not in supervisor mode causes the timer to assert a transfer error. see figure 21-2. chip select control register 0 (cscr0) . 16.5.2 run mode clearing the timen bit in the timer system control register 1 (timscr1) or the pae bit in the pulse accumulator control register (timpactl) reduces power consumption in run mode. timer registers are still accessible, but all timer functions are disabled. see figure 16-8. timer system control register (timscr1) and figure 16-19. pulse accumulator control register (timpactl) . 16.5.3 stop mode if the central processor unit (cpu) enters stop mode, timer operation stops. upon exiting stop mode, the timer resumes operation unless stop mode was exited by reset. 16.5.4 wait, doze, and debug modes the timer is unaffected by these low-power modes. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . advance information mmc2114 MMC2113 mmc2112 ? rev. 1.0 322 timer modules (tim1 and tim2) motorola timer modules (tim1 and tim2) 16.5.5 test mode a high signal on the test pin puts the processor in test mode or special mode. the timer behaves as in user mode, except that timer test registers are accessible. 16.6 signal description table 16-1 provides an overview of the signal properties. 16.6.1 icoc[2:0] the icoc[2:0] pins are for channel 2 ? 0 input capture and output compare functions. these pins are available for general-purpose input/output (i/o) when not configured for timer functions. 16.6.2 icoc3 the icoc3 pin is for channel 3 input capture and output compare functions or for the pulse accumulator input. this pin is available for general-purpose i/o when not configured for timer functions. table 16-1. signal properties pin name (1) 1. x is timer designation 1 or 2 timport register bit function reset state pullup icocx0 portt0 timer x channel 0 ic/oc pin pin state active icocx1 portt1 timer x channel 1 ic/oc pin pin state active icocx2 portt2 timer x channel 2 ic/oc pin pin state active icocx3 portt3 timer x channel 3 ic/oc or pa pin pin state active f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . timer modules (tim1 and tim2) memory map and registers mmc2114 MMC2113 mmc2112 ? rev. 1.0 advance information motorola timer modules (tim1 and tim2) 323 16.7 memory map and registers see table 16-2 for a memory map of the two timer modules. timer 1 has a base address of 0x00ce_0000. timer 2 has a base address of 0x00cf_0000. note: reading reserved or unimplemented locations returns 0s. writing to reserved or unimplemented locations has no effect. table 16-2. timer modules memory map address bits 7 ? 0 access (1) tim1 tim2 0x00ce_0000 0x00cf_0000 timer ic/oc select register (timios) s 0x00ce_0001 0x00cf_0001 timer compare force register (timcforc) s 0x00ce_0002 0x00cf_0002 timer output compare 3 mask register (timoc3m) s 0x00ce_0003 0x00cf_0003 timer output compare 3 data register (timoc3d) s 0x00ce_0004 0x00cf_0004 timer counter register high (timcnth) s 0x00ce_0005 0x00cf_0005 timer counter register low (timcntl) s 0x00ce_0006 0x00cf_0006 timer system control register 1 (timscr1) s 0x00ce_0007 0x00cf_0007 reserved (2) 2 0x00ce_0008 0x00cf_0008 timer toggle-on-overflow register (tmtov) s 0x00ce_0009 0x00cf_0009 timer control register 1 (timctl1) s 0x00ce_000a 0x00cf_000a reserved (2) 2 0x00ce_000b 0x00cf_000b timer control register 2 (timctl2) s 0x00ce_000c 0x00cf_000c timer interrupt enable register (timie) s 0x00ce_000d 0x00cf_000d timer system control register 2 (timscr2) s 0x00ce_000e 0x00cf_000e timer flag register 1 (timflg1) s 0x00ce_000f 0x00cf_000f timer flag register 2 (timflg2) s 0x00ce_0010 0x00cf_0010 timer channel 0 register high (timc0h) s 0x00ce_0011 0x00cf_0011 timer channel 0 register low (timc0l) s 0x00ce_0012 0x00cf_0012 timer channel 1 register high (timc1h) s 0x00ce_0013 0x00cf_0013 timer channel 1 register low (timc1l) s 0x00ce_0014 0x00cf_0014 timer channel 2 register high (timc2h) s 0x00ce_0015 0x00cf_0015 timer channel 2 register low (timc2l) s 0x00ce_0016 0x00cf_0016 timer channel 3 register high (timc3h) s f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . advance information mmc2114 MMC2113 mmc2112 ? rev. 1.0 324 timer modules (tim1 and tim2) motorola timer modules (tim1 and tim2) 16.7.1 timer input capture/output compare select register read: anytime; always read $00 write: anytime ios[3:0] ? i/o select bits the ios[3:0] bits enable input capture or output compare operation for the corresponding timer channels. 1 = output compare enabled 0 = input capture enabled 0x00ce_0017 0x00cf_0017 timer channel 3 register low (timc3l) s 0x00ce_0018 0x00cf_0018 pulse accumulator control register (timpactl) s 0x00ce_0019 0x00cf_0019 pulse accumulator flag register (timpaflg) s 0x00ce_001a 0x00cf_001a pulse accumulator counter register high (timpacnth) s 0x00ce_001b 0x00cf_001b pulse accumulator counter register low (timpacntl) s 0x00ce_001c 0x00cf_001c reserved (2) 2 0x00ce_001d 0x00cf_001d timer port data register (timport) s 0x00ce_001e 0x00cf_001e timer port data direction register (timddr) s 0x00ce_001f 0x00cf_001f timer test register (timtst) s 1. s = cpu supervisor mode access only. 2. writes have no effect, reads return 0s, and the access terminates without a transfer error exception. table 16-2. timer modules memory map (continued) address bits 7 ? 0 access (1) tim1 tim2 address: tim1 ? 0x00ce_0000 tim2 ? 0x00cf_0000 bit 7654321bit 0 read: 0000 ios3 ios2 ios1 ios0 write: reset:00000000 = writes have no effect and the access terminates without a transfer error exception. figure 16-2. timer input capture/output compare select register (timios) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . timer modules (tim1 and tim2) memory map and registers mmc2114 MMC2113 mmc2112 ? rev. 1.0 advance information motorola timer modules (tim1 and tim2) 325 16.7.2 timer compare force register read: anytime write: anytime foc[3:0] ? force output compare bits setting an foc bit causes an immediate output compare on the corresponding channel. forcing an output compare does not set the output compare flag. 1 = force output compare 0 = no effect note: a successful channel 3 output compare overrides any channel 2:0 compares. for each oc3m bit that is set, the output compare action reflects the corresponding oc3d bit. address: tim1 ? 0x00ce_0001 tim2 ? 0x00cf_0001 bit 7654321bit 0 read: 00000000 write: foc3 foc2 foc1 foc0 reset:00000000 = writes have no effect and the access terminates without a transfer error exception. figure 16-3. timer compare force register (timcforc) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . advance information mmc2114 MMC2113 mmc2112 ? rev. 1.0 326 timer modules (tim1 and tim2) motorola timer modules (tim1 and tim2) 16.7.3 timer output compare 3 mask register read: anytime write: anytime oc3m[3:0] ? output compare 3 mask bits setting an oc3m bit configures the corresponding timport pin to be an output. oc3mx makes the timer port pin an output regardless of the data direction bit when the pin is configured for output compare (iosx = 1). the oc3mx bits do not change the state of the timddr bits. 1 = corresponding timport pin configured as output 0 = no effect address: tim1 ? 0x00ce_0002 tim2 ? 0x00cf_0002 bit 7654321bit 0 read: 0000 oc3m3 oc3m2 oc3m1 oc3m0 write: reset:00000000 = writes have no effect and the access terminates without a transfer error exception. figure 16-4. timer output compare 3 mask register (timoc3m) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . timer modules (tim1 and tim2) memory map and registers mmc2114 MMC2113 mmc2112 ? rev. 1.0 advance information motorola timer modules (tim1 and tim2) 327 16.7.4 timer output compare 3 data register read: anytime write: anytime oc3d[3:0] ? output compare 3 data bits when a successful channel 3 output compare occurs, these bits transfer to the timer port data register if the corresponding oc3mx bits are set. note: a successful channel 3 output compare overrides any channel 2:0 compares. for each oc3m bit that is set, the output compare action reflects the corresponding oc3d bit. address: tim1 ? 0x00ce_0003 tim2 ? 0x00cf_0003 bit 7654321bit 0 read: 0000 oc3d3 oc3d2 oc3d1 oc3d0 write: reset:00000000 = writes have no effect and the access terminates without a transfer error exception. figure 16-5. timer output compare 3 data register (timoc3d) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . advance information mmc2114 MMC2113 mmc2112 ? rev. 1.0 328 timer modules (tim1 and tim2) motorola timer modules (tim1 and tim2) 16.7.5 timer counter registers read: anytime write: only in test (special) mode; has no effect in normal modes to ensure coherent reading of the timer counter, such that a timer rollover does not occur between two back-to-back 8-bit reads, it is recommended that only half-word (16-bit) accesses be used. a write to timcnt may have an extra cycle on the first count because the write is not synchronized with the prescaler clock. the write occurs at least one cycle before the synchronization of the prescaler clock. address: tim1 ? 0x00ce_0004 tim2 ? 0x00cf_0004 bit 7654321bit 0 read: bit 15 14 13 12 11 10 9 bit 8 write: reset:00000000 = writes have no effect and the access terminates without a transfer error exception. figure 16-6. timer counter register high (timcnth) address: tim1 ? 0x00ce_0005 tim2 ? 0x00cf_0005 bit 7654321bit 0 read: bit 7 654321bit 0 write: reset:00000000 = writes have no effect and the access terminates without a transfer error exception. figure 16-7. timer counter register low (timcntl) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . timer modules (tim1 and tim2) memory map and registers mmc2114 MMC2113 mmc2112 ? rev. 1.0 advance information motorola timer modules (tim1 and tim2) 329 16.7.6 timer system control register 1 read: anytime write: anytime timen ? timer enable bit timen enables the timer. when the timer is disabled, only the registers are accessible. clearing timen reduces power consumption. 1 = timer enabled 0 = timer and timer counter disabled tffca ? timer fast flag clear all bit tffca enables fast clearing of the main timer interrupt flag registers (timflg1 and timflg2) and the pa flag register (timpaflg). tffca eliminates the software overhead of a separate clear sequence. when tffca is set: an input capture read or a write to an output compare channel clears the corresponding channel flag, cxf. any access of the timer count registers (timcnth/l) clears the tof flag. any access of the pa counter registers (timpacnt) clears both the paovf and paif flags in timpaflg. writing logic 1s to the flags clears them only when tffca is clear. 1 = fast flag clearing 0 = normal flag clearing address: tim1 ? 0x00ce_0006 tim2 ? 0x00cf_0006 bit 7654321bit 0 read: timen 00 tffca 0000 write: reset:00000000 = writes have no effect and the access terminates without a transfer error exception. figure 16-8. timer system control register (timscr1) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . advance information mmc2114 MMC2113 mmc2112 ? rev. 1.0 330 timer modules (tim1 and tim2) motorola timer modules (tim1 and tim2) figure 16-9. fast clear flag logic 16.7.7 timer toggle-on-overflow register read: anytime write: anytime tov[3:0] ? toggle-on-overflow bits tov[3:0] toggles the output compare pin on overflow. this feature only takes effect when in output compare mode. when set, it takes precedence over forced output compare but not channel 3 override events. 1 = toggle output compare pin on overflow feature enabled 0 = toggle output compare pin on overflow feature disabled clear write timcx registers read timcx registers tffca data bit x write timflg1 register cxf cxf flag address: tim1 ? 0x00ce_0008 tim2 ? 0x00cf_0008 bit 7654321bit 0 read: 0000 tov3 tov2 tov1 tov0 write: reset:00000000 = writes have no effect and the access terminates without a transfer error exception. figure 16-10. timer toggle-on-overflow register (timtov) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . timer modules (tim1 and tim2) memory map and registers mmc2114 MMC2113 mmc2112 ? rev. 1.0 advance information motorola timer modules (tim1 and tim2) 331 16.7.8 timer control register 1 read: anytime write: anytime omx/olx ? output mode/output level bits these bit pairs select the output action to be taken as a result of a successful output compare. when either omx or olx is set and the iosx bit is set, the pin is an output regardless of the state of the corresponding ddr bit. channel 3 shares a pin with the pulse accumulator input pin. to use the pai input, clear both the om3 and ol3 bits and clear the oc3m3 bit in the output compare 3 mask register. address: tim1 ? 0x00ce_0009 tim2 ? 0x00cf_0009 bit 7654321bit 0 read: om3 ol3 om2 ol2 om1 ol1 om0 ol0 write: reset:00000000 figure 16-11. timer control register 1 (timctl1) table 16-3. output compare action selection omx:olx action on output compare 00 timer disconnected from output pin logic 01 toggle ocx output line 10 clear ocx output line 11 set ocx line f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . advance information mmc2114 MMC2113 mmc2112 ? rev. 1.0 332 timer modules (tim1 and tim2) motorola timer modules (tim1 and tim2) 16.7.9 timer control register 2 read: anytime write: anytime edgx[b:a] ? input capture edge control bits these eight bit pairs configure the input capture edge detector circuits. address: tim1 ? 0x00ce_000b tim2 ? 0x00cf_000b bit 7654321bit 0 read: edg3b edg3a edg2b edg2a edg1b edg1a edg0b edg10 write: reset:00000000 figure 16-12. timer control register 2 (timctl2) table 16-4. input capture edge selection edgx[b:a] edge selection 00 input capture disabled 01 input capture on rising edges only 10 input capture on falling edges only 11 input capture on any edge (rising or falling) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . timer modules (tim1 and tim2) memory map and registers mmc2114 MMC2113 mmc2112 ? rev. 1.0 advance information motorola timer modules (tim1 and tim2) 333 16.7.10 timer interrupt enable register read: anytime write: anytime c[3:0]i ? channel interrupt enable bits c[3:0]i enable the c[3:0]f flags in timer flag register 1 to generate interrupt requests. 1 = corresponding channel interrupt requests enabled 0 = corresponding channel interrupt requests disabled address: tim1 ? 0x00ce_000c tim2 ? 0x00cf_000c bit 7654321bit 0 read: 0000 c3i c2i c1i c0i write: reset:00000000 = writes have no effect and the access terminates without a transfer error exception. figure 16-13. timer interrupt enable register (timie) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . advance information mmc2114 MMC2113 mmc2112 ? rev. 1.0 334 timer modules (tim1 and tim2) motorola timer modules (tim1 and tim2) 16.7.11 timer system control register 2 read: anytime write: anytime toi ? timer overflow interrupt enable bit toi enables timer overflow interrupt requests. 1 = overflow interrupt requests enabled 0 = overflow interrupt requests disabled pupt ? timer pullup enable bit pupt enables pullup resistors on the timer ports when the ports are configured as inputs. 1 = pullup resistors enabled 0 = pullup resistors disabled rdpt ? timer drive reduction bit rdpt reduces the output driver size. 1 = output drive reduction enabled 0 = output drive reduction disabled tcre ? timer counter reset enable bit tcre enables a counter reset after a channel 3 compare. 1 = counter reset enabled 0 = counter reset disabled note: when the timer channel 3 registers contain $0000 and tcre is set, the timer counter registers remain at $0000 all the time. address: tim1 ? 0x00ce_000d tim2 ? 0x00cf_000d bit 7654321bit 0 read: toi 0 pupt rdpt tcre pr2 pr1 pr0 write: reset:00000000 = writes have no effect and the access terminates without a transfer error exception. figure 16-14. timer system control register 2 (timscr2) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . timer modules (tim1 and tim2) memory map and registers mmc2114 MMC2113 mmc2112 ? rev. 1.0 advance information motorola timer modules (tim1 and tim2) 335 when the timer channel 3 registers contain $ffff and tcre is set, tof never gets set even though the timer counter registers go from $ffff to $0000. pr[2:0] ? prescaler bits these bits select the prescaler divisor for the timer counter. note: the newly selected prescaled clock does not take effect until the next synchronized edge of the prescaled clock when the clock count transitions to $0000.) table 16-5. prescaler selection pr[2:0] prescaler divisor 000 1 001 2 010 4 011 8 100 16 101 32 110 64 111 128 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . advance information mmc2114 MMC2113 mmc2112 ? rev. 1.0 336 timer modules (tim1 and tim2) motorola timer modules (tim1 and tim2) 16.7.12 timer flag register 1 read: anytime write: anytime; writing 1 clears flag; writing 0 has no effect c[3:0]f ? channel flags a channel flag is set when an input capture or output compare event occurs. clear a channel flag by writing a 1 to the flag. note: when the fast flag clear all bit, tffca, is set, an input capture read or an output compare write clears the corresponding channel flag. tffca is in timer system control register 1 (timscr1). when a channel flag is set, it does not inhibit subsequent output compares or input captures. address: tim1 ? 0x00ce_000e tim2 ? 0x00cf_000e bit 7654321bit 0 read: 0000 c3f c2f c1f c0f write: reset:00000000 = writes have no effect and the access terminates without a transfer error exception. figure 16-15. timer flag register 1 (timflg1) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . timer modules (tim1 and tim2) memory map and registers mmc2114 MMC2113 mmc2112 ? rev. 1.0 advance information motorola timer modules (tim1 and tim2) 337 16.7.13 timer flag register 2 read: anytime write: anytime; writing 1 clears flag; writing 0 has no effect tof ? timer overflow flag tof is set when the timer counter rolls over from $ffff to $0000. if the toi bit in timscr2 is also set, tof generates an interrupt request. clear tof by writing a 1 to it. 1 = timer overflow 0 = no timer overflow note: when the timer channel 3 registers contain $ffff and tcre is set, tof never gets set even though the timer counter registers go from $ffff to $0000. when the fast flag clear all bit, tffca, is set, any access to the timer counter registers clears timer flag register 2. the tffca bit is in timer system control register 1 (timscr1). when tof is set, it does not inhibit subsequent overflow events. address: tim1 ? 0x00ce_000f tim2 ? 0x00cf_000f bit 7654321bit 0 read: tof 0000000 write: reset:00000000 = writes have no effect and the access terminates without a transfer error exception. figure 16-16. timer flag register 2 (timflg2) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . advance information mmc2114 MMC2113 mmc2112 ? rev. 1.0 338 timer modules (tim1 and tim2) motorola timer modules (tim1 and tim2) 16.7.14 timer channel registers read: anytime write: output compare channel, anytime; input capture channel, no effect when a channel is configured for input capture (iosx = 0), the timer channel registers latch the value of the free-running counter when a defined transition occurs on the corresponding input capture pin. when a channel is configured for output compare (iosx = 1), the timer channel registers contain the output compare value. to ensure coherent reading of the timer counter, such that a timer rollover does not occur between back-to-back 8-bit reads, it is recommended that only half-word (16-bit) accesses be used. address: timc0h ? 0x00ce_0010/0x00cf_0010 timc1h ? 0x00ce_0012/0x00cf_0012 timc2h ? 0x00ce_0014/0x00cf_0014 timc3h ? 0x00ce_0016/0x00cf_0016 bit 7654321bit 0 read: bit 15 14 13 12 11 10 9 bit 8 write: reset:00000000 figure 16-17. timer channel [0:3] register high (timcxh) address: timc0l ? 0x00ce_0011/0x00cf_0011 timc1l ? 0x00ce_0013/0x00cf_0013 timc2l ? 0x00ce_0015/0x00cf_0015 timc3l ? 0x00ce_0017/0x00cf_0017 bit 7654321bit 0 read: bit 7654321bit 0 write: reset:00000000 figure 16-18. timer channel [0:3] register low (timcxl) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . timer modules (tim1 and tim2) memory map and registers mmc2114 MMC2113 mmc2112 ? rev. 1.0 advance information motorola timer modules (tim1 and tim2) 339 16.7.15 pulse accumulator control register read: anytime write: anytime pae ? pulse accumulator enable bit pae enables the pulse accumulator. 1 = pulse accumulator enabled 0 = pulse accumulator disabled note: the pulse accumulator can operate in event mode even when the timer enable bit, timen, is clear. pamod ? pulse accumulator mode bit pamod selects event counter mode or gated time accumulation mode. 1 = gated time accumulation mode 0 = event counter mode pedge ? pulse accumulator edge bit pedge selects falling or rising edges on the pai pin to increment the counter. in event counter mode (pamod = 0): 1 = rising pai edge increments counter 0 = falling pai edge increments counter address: tim1 ? 0x00ce_0018 tim2 ? 0x00cf_0018 bit 7654321bit 0 read: 0 pae pamod pedge clk1 clk0 paovi pai write: reset:00000000 = writes have no effect and the access terminates without a transfer error exception. figure 16-19. pulse accumulator control register (timpactl) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . advance information mmc2114 MMC2113 mmc2112 ? rev. 1.0 340 timer modules (tim1 and tim2) motorola timer modules (tim1 and tim2) in gated time accumulation mode (pamod = 1): 1 = low pai input enables divide-by-64 clock to pulse accumulator and trailing rising edge on pai sets paif flag. 0 = high pai input enables divide-by-64 clock to pulse accumulator and trailing falling edge on pai sets paif flag. note: the timer prescaler generates the divide-by-64 clock. if the timer is not active, there is no divide-by-64 clock. to operate in gated time accumulation mode: 1. apply logic 0 to reset pin. 2. initialize registers for pulse accumulator mode test. 3. apply appropriate level to pai pin. 4. enable timer. clk[1:0] ? clock select bits clk[1:0] select the timer counter input clock as shown in table 16-6 . paovi ? pulse accumulator overflow interrupt enable bit paovi enables the paovf flag to generate interrupt requests. 1 = paovf interrupt requests enabled 0 = paovf interrupt requests disabled pai ? pulse accumulator input interrupt enable bit pai enables the paif flag to generate interrupt requests. 1 = paif interrupt requests enabled 0 = paif interrupt requests disabled table 16-6. clock selection clk[1:0] timer counter clock (1) 1. changing the clkx bits causes an immediate change in the timer counter clock input. 00 timer prescaler clock (2) 2. when pae = 0, the timer prescaler clock is always the timer counter clock. 01 paclk 10 paclk/256 11 paclk/65536 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . timer modules (tim1 and tim2) memory map and registers mmc2114 MMC2113 mmc2112 ? rev. 1.0 advance information motorola timer modules (tim1 and tim2) 341 16.7.16 pulse accumulator flag register read: anytime write: anytime; writing 1 clears the flag; writing 0 has no effect paovf ? pulse accumulator overflow flag paovf is set when the 16-bit pulse accumulator rolls over from $ffff to $0000. if the paovi bit in timpactl is also set, paovf generates an interrupt request. clear paovf by writing a 1 to it. 1 = pulse accumulator overflow 0 = no pulse accumulator overflow paif ? pulse accumulator input flag paif is set when the selected edge is detected at the pai pin. in event counter mode, the event edge sets paif. in gated time accumulation mode, the trailing edge of the gate signal at the pai pin sets paif. if the pai bit in timpactl is also set, paif generates an interrupt request. clear paif by writing a 1 to it. 1 = active pai input 0 = no active pai input note: when the fast flag clear all enable bit, tffca, is set, any access to the pulse accumulator counter registers clears all the flags in timpaflg. address: tim1 ? 0x00ce_0019 tim2 ? 0x00cf_0019 bit 7654321bit 0 read: 000000 paovf paif write: reset:00000000 = writes have no effect and the access terminates without a transfer error exception. figure 16-20. pulse accumulator flag register (timpaflg) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . advance information mmc2114 MMC2113 mmc2112 ? rev. 1.0 342 timer modules (tim1 and tim2) motorola timer modules (tim1 and tim2) 16.7.17 pulse accumulator counter registers read: anytime write: anytime these registers contain the number of active input edges on the pai pin since the last reset. note: reading the pulse accumulator counter registers immediately after an active edge on the pai pin may miss the last count since the input first has to be synchronized with the bus clock. to ensure coherent reading of the pa counter, such that the counter does not increment between back-to-back 8-bit reads, it is recommended that only half-word (16-bit) accesses be used. address: tim1 ? 0x00ce_001a tim2 ? 0x00cf_001a bit 7654321bit 0 read: bit 15 14 13 12 11 10 9 bit 8 write: reset:00000000 figure 16-21. pulse accumulator counter register high (timpacnth) address: tim1 ? 0x00ce_001b tim2 ? 0x00cf_001b bit 7654321bit 0 read: bit 7654321bit 0 write: reset:00000000 figure 16-22. pulse accumulator counter register low (timpacntl) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . timer modules (tim1 and tim2) memory map and registers mmc2114 MMC2113 mmc2112 ? rev. 1.0 advance information motorola timer modules (tim1 and tim2) 343 16.7.18 timer port data register read: anytime; read pin state when corresponding timddr bit is 0; read pin driver state when corresponding timddr bit is 1 write: anytime portt[3:0] ? timer port input capture/output compare data bits data written to timport is buffered and drives the pins only when they are configured as general-purpose outputs. reading an input (ddr bit = 0) reads the pin state; reading an output (ddr bit = 1) reads the latch. writing to a pin configured as a timer output does not change the pin state. address: tim1 ? 0x00ce_001d tim2 ? 0x00cf_001d bit 7654321bit 0 read: 0000 portt3 portt2 portt1 portt0 write: reset:00000000 = writes have no effect and the access terminates without a transfer error exception. figure 16-23. timer port data register (timport) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . advance information mmc2114 MMC2113 mmc2112 ? rev. 1.0 344 timer modules (tim1 and tim2) motorola timer modules (tim1 and tim2) 16.7.19 timer port data direction register read: anytime write: anytime ddrt[3:0] ? timport data direction bits these bits control the port logic of timport. reset clears the timer port data direction register, configuring all timer port pins as inputs. 1 = corresponding pin configured as output 0 = corresponding pin configured as input address: tim1 ? 0x00ce_001e tim2 ? 0x00cf_001e bit 7654321bit 0 read: 0000 ddrt3 ddrt2 ddrt1 ddrt0 write: reset:00000000 timer function: ic/oc3 ic/oc2 ic/oc1 ic/oc0 pulse accumulator function: pai = writes have no effect and the access terminates without a transfer error exception. figure 16-24. timer port data direction register (timddr) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . timer modules (tim1 and tim2) functional description mmc2114 MMC2113 mmc2112 ? rev. 1.0 advance information motorola timer modules (tim1 and tim2) 345 16.7.20 timer test register the timer test register (timtst) is only for factory testing. when not in test mode, timtst is read-only. 16.8 functional description the timer module is a 16-bit, 4-channel timer with input capture and output compare functions and a pulse accumulator. 16.8.1 prescaler the prescaler divides the module clock by 1, 2, 4, 8, 16, 32, 64, or 128. the pr[2:0] bits in timscr2 select the prescaler divisor. 16.8.2 input capture clearing an i/o select bit, iosx, configures channel x as an input capture channel. the input capture function captures the time at which an external event occurs. when an active edge occurs on the pin of an input capture channel, the timer transfers the value in the timer counter into the timer channel registers, timcxh and timcxl. the minimum pulse width for the input capture input is greater than two module clocks. address: tim1 ? 0x00ce_001f tim2 ? 0x00cf_001f bit 7654321bit 0 read: 00000000 write: reset:00000000 = writes have no effect and the access terminates without a transfer error exception. figure 16-25. timer test register (timtst) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . advance information mmc2114 MMC2113 mmc2112 ? rev. 1.0 346 timer modules (tim1 and tim2) motorola timer modules (tim1 and tim2) the input capture function does not force data direction. the timer port data direction register controls the data direction of an input capture pin. pin conditions such as rising or falling edges can trigger an input capture only on a pin configured as an input. an input capture on channel x sets the cxf flag. the cxi bit enables the cxf flag to generate interrupt requests. 16.8.3 output compare setting an i/o select bit, iosx, configures channel x as an output compare channel. the output compare function can generate a periodic pulse with a programmable polarity, duration, and frequency. when the timer counter reaches the value in the channel registers of an output compare channel, the timer can set, clear, or toggle the channel pin. an output compare on channel x sets the cxf flag. the cxi bit enables the cxf flag to generate interrupt requests. the output mode and level bits, omx and olx, select, set, clear, or toggle on output compare. clearing both omx and olx disconnects the pin from the output logic. setting a force output compare bit, focx, causes an output compare on channel x. a forced output compare does not set the channel flag. a successful output compare on channel 3 overrides output compares on all other output compare channels. a channel 3 output compare can cause bits in the output compare 3 data register to transfer to the timer port data register, depending on the output compare 3 mask register. the output compare 3 mask register masks the bits in the output compare 3 data register. the timer counter reset enable bit, tcre, enables channel 3 output compares to reset the timer counter. a channel 3 output compare can reset the timer counter even if the oc3/pai pin is being used as the pulse accumulator input. an output compare overrides the data direction bit of the output compare pin but does not change the state of the data direction bit. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . timer modules (tim1 and tim2) functional description mmc2114 MMC2113 mmc2112 ? rev. 1.0 advance information motorola timer modules (tim1 and tim2) 347 writing to the timer port bit of an output compare pin does not affect the pin state. the value written is stored in an internal latch. when the pin becomes available for general-purpose output, the last value written to the bit appears at the pin. 16.8.4 pulse accumulator the pulse accumulator (pa) is a 16-bit counter that can operate in two modes: 1. event counter mode ? counts edges of selected polarity on the pulse accumulator input pin, pai 2. gated time accumulation mode ? counts pulses from a divide-by-64 clock the pa mode bit, pamod, selects the mode of operation. the minimum pulse width for the pai input is greater than two module clocks. 16.8.4.1 event counter mode clearing the pamod bit configures the pa for event counter operation. an active edge on the pai pin increments the pa. the pa edge bit, pedge, selects falling edges or rising edges to increment the pa. an active edge on the pai pin sets the pa input flag, paif. the pa input interrupt enable bit, pai, enables the paif flag to generate interrupt requests. note: the pai input and timer channel 3 use the same pin. to use the pai input, disconnect it from the output logic by clearing the channel 3 output mode and output level bits, om3 and ol3. also clear the channel 3 output compare 3 mask bit, oc3m3. the pa counter registers, timpacnth/l, reflect the number of active input edges on the pai pin since the last reset. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . advance information mmc2114 MMC2113 mmc2112 ? rev. 1.0 348 timer modules (tim1 and tim2) motorola timer modules (tim1 and tim2) the pa overflow flag, paovf, is set when the pa rolls over from $ffff to $0000. the pa overflow interrupt enable bit, paovi, enables the paovf flag to generate interrupt requests. note: the pa can operate in event counter mode even when the timer enable bit, timen, is clear. 16.8.4.2 gated time accumulation mode setting the pamod bit configures the pa for gated time accumulation operation. an active level on the pai pin enables a divide-by-64 clock to drive the pa. the pa edge bit, pedge, selects low levels or high levels to enable the divide-by-64 clock. the trailing edge of the active level at the pai pin sets the pa input flag, paif. the pa input interrupt enable bit, pai, enables the paif flag to generate interrupt requests. note: the pai input and timer channel 3 use the same pin. to use the pai input, disconnect it from the output logic by clearing the channel 3 output mode and output level bits, om3 and ol3. also clear the channel 3 output compare mask bit, oc3m3. the pa counter registers, timpacnth/l reflect the number of pulses from the divide-by-64 clock since the last reset. note: the timer prescaler generates the divide-by-64 clock. if the timer is not active, there is no divide-by-64 clock. figure 16-26. channel 3 output compare/pulse accumulator logic pad om3 ol3 channel 3 output compare pulse accumulator oc3m3 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . timer modules (tim1 and tim2) functional description mmc2114 MMC2113 mmc2112 ? rev. 1.0 advance information motorola timer modules (tim1 and tim2) 349 16.8.5 general-purpose i/o ports an i/o pin used by the timer defaults to general-purpose i/o unless an internal function which uses that pin is enabled. the timer pins can be configured for either an input capture function or an output compare function. the iosx bits in the timer ic/oc select register configure the timer port pins as either input capture or output compare pins. the timer port data direction register controls the data direction of an input capture pin. external pin conditions trigger input captures on input capture pins configured as inputs. to configure a pin for input capture: 1. clear the pin ? s ios bit in timios. 2. clear the pin ? s ddr bit in timddr. 3. write to timctl2 to select the input edge to detect. timddr does not affect the data direction of an output compare pin. the output compare function overrides the data direction register but does not affect the state of the data direction register. to configure a pin for output compare: 1. set the pin ? s ios bit in timios. 2. write the output compare value to timcxh/l. 3. clear the pin ? s ddr bit in timddr. 4. write to the omx/olx bits in timctl1 to select the output action. table 16-7 shows how various timer settings affect pin functionality. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . advance information mmc2114 MMC2113 mmc2112 ? rev. 1.0 350 timer modules (tim1 and tim2) motorola timer modules (tim1 and tim2) table 16-7. timer settings and pin functions timen ddr (1) timios edgx [b:a] omx/ olx (2) oc3mx (3) pin data direction pin driven by pin function comments 00 x (4) x x x in ext. digital input timer disabled by timen = 0 0 1 x x x x out data reg. digital output timer disabled by timen = 0 100 (ic) 0 (ic disabled) x 0 in ext. digital input input capture disabled by edgx setting 1 1 0 0 x 0 out data reg. digital output input capture disabled by edgx setting 1 0 0 <> 0 x 0 in ext. ic and digital input normal settings for input capture 1 1 0 <> 0 x 0 out data reg. digital output input capture of data driven to output pin by cpu 1 0 0 <> 0 x 1 in ext. ic and digital input oc3m setting has no effect because ios = 0 1 1 0 <> 0 x 1 out data reg. digital output oc3m setting has no effect because ios = 0; input capture of data driven to output pin by cpu 101 (oc) x (3) 0 (5) 0 in ext. digital input output compare takes place but does not affect the pin because of the omx/olx setting 1 1 1 x 0 0 out data reg. digital output output compare takes place but does not affect the pin because of the omx/olx setting 1 0 1 x <> 0 0 out oc action output compare pin readable only if ddr = 0 (5) 1 1 1 x <> 0 0 out oc action output compare pin driven by oc action (5) 10 1 x x 1 out oc action/ oc3dx output compare (ch 3) pin readable only if ddr = 0 (6) 11 1 x x 1 out oc action/ oc3dx output compare/ oc3dx (ch 3) pin driven by channel oc action and oc3dx via channel 3 oc (6) 1. when ddr set the pin as input (0), reading the data register will return the state of the pin. when ddr set the pin as outpu t (1), reading the data register will return the content of the data latch. pin conditions such as rising or falling edges can trigger an input capture on a pin configured as an input. 2. omx/olx bit pairs select the output action to be taken as a result of a successful output compare. when either omx or olx is set and the iosx bit is set, the pin is an output regardless of the state of the corresponding ddr bit. 3. setting an oc3m bit configures the corresponding timport pin to be output. oc3mx makes the timer port pin an output regardle ss of the data direction bit when the pin is configured for output compare (iosx = 1). the oc3mx bits do not change the state of the timddr bi ts. 4. x = don ? t care 5. an output compare overrides the data direction bit of the output compare pin but does not change the state of the data direc tion bit. enabling output compare disables data register drive of the pin. 6. a successful output compare on channel 3 causes an output value determined by oc3dx value to temporarily override the output compare pin state of any other output compare channel.the next oc action for the specific channel will still be output to the pin. a channel 3 ou tput compare can cause bits in the output compare 3 data register to transfer to the timer port data register, depending on the output compare 3 mask register. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . timer modules (tim1 and tim2) reset mmc2114 MMC2113 mmc2112 ? rev. 1.0 advance information motorola timer modules (tim1 and tim2) 351 16.9 reset reset initializes the timer registers to a known startup state as described in 16.7 memory map and registers . 16.10 interrupts table 16-8 lists the interrupt requests generated by the timer. 16.10.1 timer channel interrupts (cxf) a channel flag is set when an input capture or output compare event occurs. clear a channel flag by writing a 1 to the flag. note: when the fast flag clear all bit, tffca, is set, an input capture read or an output compare write clears the corresponding channel flag. tffca is in timer system control register 1 (timscr1). when a channel flag is set, it does not inhibit subsequent output compares or input captures table 16-8. timer interrupt requests interrupt request flag enable bit channel 3 ic/oc c3f c3i channel 2 ic/oc c2f c2i channel 1 ic/oc c1f c1i channel 0 ic/oc c0f c0i pa overflow paovf paovi pa input paif pai timer overflow tof toi f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . advance information mmc2114 MMC2113 mmc2112 ? rev. 1.0 352 timer modules (tim1 and tim2) motorola timer modules (tim1 and tim2) 16.10.2 pulse accumulator overflow (paovf) paovf is set when the 16-bit pulse accumulator rolls over from $ffff to $0000. if the paovi bit in timpactl is also set, paovf generates an interrupt request. clear paovf by writing a 1 to this flag. note: when the fast flag clear all enable bit, tffca, is set, any access to the pulse accumulator counter registers clears all the flags in timpaflg. 16.10.3 pulse accumulator input (paif) paif is set when the selected edge is detected at the pai pin. in event counter mode, the event edge sets paif. in gated time accumulation mode, the trailing edge of the gate signal at the pai pin sets paif. if the pai bit in timpactl is also set, paif generates an interrupt request. clear paif by writing a 1 to this flag. note: when the fast flag clear all enable bit, tffca, is set, any access to the pulse accumulator counter registers clears all the flags in timpaflg. 16.10.4 timer overflow (tof) tof is set when the timer counter rolls over from $ffff to $0000. if the toi bit in timscr2 is also set, tof generates an interrupt request. clear tof by writing a 1 to this flag. note: when the timer channel 3 registers contain $ffff and tcre is set, tof never gets set even though the timer counter registers go from $ffff to $0000. when the fast flag clear all bit, tffca, is set, any access to the timer counter registers clears timer flag register 2. the tffca bit is in timer system control register 1 (timscr1). when tof is set, it does not inhibit future overflow events. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . mmc2114 MMC2113 mmc2112 ? rev. 1.0 advance information motorola serial communications interface modules (sci1 and sci2) 353 advance information ? mmc2114, MMC2113, and mmc2112 section 17. serial communications interface modules (sci1 and sci2) 17.1 contents 17.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .354 17.3 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .355 17.4 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .356 17.5 modes of operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .357 17.5.1 doze mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .357 17.5.2 stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .357 17.6 signal description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .358 17.6.1 rxd . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 358 17.6.2 txd . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .358 17.7 memory map and registers . . . . . . . . . . . . . . . . . . . . . . . . . .358 17.7.1 sci baud rate registers . . . . . . . . . . . . . . . . . . . . . . . . . .360 17.7.2 sci control register 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . .361 17.7.3 sci control register 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . .364 17.7.4 sci status register 1. . . . . . . . . . . . . . . . . . . . . . . . . . . . .366 17.7.5 sci status register 2. . . . . . . . . . . . . . . . . . . . . . . . . . . . .369 17.7.6 sci data registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .370 17.7.7 sci pullup and reduced drive register . . . . . . . . . . . . . .371 17.7.8 sci port data register . . . . . . . . . . . . . . . . . . . . . . . . . . . .372 17.7.9 sci data direction register . . . . . . . . . . . . . . . . . . . . . . . .373 17.8 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .374 17.9 data format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .374 17.10 baud rate generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .375 17.11 transmitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .376 17.11.1 frame length . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .377 17.11.2 transmitting a frame . . . . . . . . . . . . . . . . . . . . . . . . . . . . .378 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . advance information mmc2114 MMC2113 mmc2112 ? rev. 1.0 354 serial communications interface modules (sci1 and sci2) motorola serial communications interface modules (sci1 and sci2) 17.11.3 break frames. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .380 17.11.4 idle frames . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .380 17.12 receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .381 17.12.1 frame length . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .381 17.12.2 receiving a frame . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .381 17.12.3 data sampling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .382 17.12.4 framing errors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .387 17.12.5 baud rate tolerance . . . . . . . . . . . . . . . . . . . . . . . . . . . . .387 17.12.5.1 slow data tolerance . . . . . . . . . . . . . . . . . . . . . . . . . . .388 17.12.5.2 fast data tolerance . . . . . . . . . . . . . . . . . . . . . . . . . . .389 17.12.6 receiver wakeup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .390 17.12.6.1 idle input line wakeup (wake = 0) . . . . . . . . . . . . . . .390 17.12.6.2 address mark wakeup (wake = 1). . . . . . . . . . . . . . . .391 17.13 single-wire operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .392 17.14 loop operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .393 17.15 i/o ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .394 17.16 reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .395 17.17 interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .395 17.17.1 transmit data register empty . . . . . . . . . . . . . . . . . . . . . .395 17.17.2 transmission complete . . . . . . . . . . . . . . . . . . . . . . . . . . .395 17.17.3 receive data register full. . . . . . . . . . . . . . . . . . . . . . . . . 396 17.17.4 idle receiver input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .396 17.17.5 overrun . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .396 17.2 introduction the serial communications interface (sci) allows asynchronous serial communications with peripheral devices and other microcontroller units (mcu). the mmc2114, MMC2113, and mmc2112 have two identical sci modules, each with its own control registers and input/output (i/o) pins. in the text that follows, sci register names are denoted generically. thus, sciport refers interchangeably to sci1port and sci2port, the port data registers for sci1 and sci2, respectively. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . serial communications interface modules (sci1 and sci2) features mmc2114 MMC2113 mmc2112 ? rev. 1.0 advance information motorola serial communications interface modules (sci1 and sci2) 355 17.3 features features of each sci module include: full-duplex operation standard mark/space non-return-to-zero (nrz) format 13-bit baud rate selection programmable 8-bit or 9-bit data format separately enabled transmitter and receiver separate receiver and transmitter central processor unit (cpu) interrupt requests programmable transmitter output polarity two receiver wakeup methods: ? idle line wakeup ? address mark wakeup interrupt-driven operation with eight flags: ? transmitter empty ? transmission complete ? receiver full ? idle receiver input ? receiver overrun ? noise error ? framing error ? parity error receiver framing error detection hardware parity checking 1/16 bit-time noise detection general-purpose, i/o capability f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . advance information mmc2114 MMC2113 mmc2112 ? rev. 1.0 356 serial communications interface modules (sci1 and sci2) motorola serial communications interface modules (sci1 and sci2) 17.4 block diagram figure 17-1. sci block diagram sci data receive shift register sci data register transmit shift register register baud rate generator scbr[12:0] rxd txd receive and wakeup data format control control pf fe nf rdrf idle tie or tcie raf clock idle ilie rie rdrf/or tdre tc interrupt interrupt interrupt interrupt pin request request request request sbk loops te rsrc transmit control loops rwu re rsrc pe ilt pt wake m pin 16 tc tdre ipbus ipbus t8 r8 system f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . serial communications interface modules (sci1 and sci2) modes of operation mmc2114 MMC2113 mmc2112 ? rev. 1.0 advance information motorola serial communications interface modules (sci1 and sci2) 357 17.5 modes of operation sci operation is identical in run, special, and emulation modes. the sci has two low-power modes, doze and stop. note: run mode is the normal mode of operation and the wait instruction does not affect sci operation. 17.5.1 doze mode when the scidoz bit in the sci pullup and reduced drive (scipurd) register is set, the doze instruction stops the sci clock and puts the sci in a low-power state. the doze instruction does not affect sci register states. any transmission or reception in progress stops at doze mode entry and resumes when an internal or external interrupt request brings the cpu out of doze mode. exiting doze mode by reset aborts any transmission or reception in progress and resets the sci. see 17.7.7 sci pullup and reduced drive register . when the scidoz bit is clear, execution of the doze instruction has no effect on the sci. normal module operation continues, allowing any sci interrupt to bring the cpu out of doze mode. 17.5.2 stop mode the stop instruction stops the sci clock and puts the sci in a low-power state. the stop instruction does not affect sci register states. any transmission or reception in progress halts at stop mode entry and resumes when an external interrupt request brings the cpu out of stop mode. exiting stop mode by reset aborts any transmission or reception in progress and resets the sci. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . advance information mmc2114 MMC2113 mmc2112 ? rev. 1.0 358 serial communications interface modules (sci1 and sci2) motorola serial communications interface modules (sci1 and sci2) 17.6 signal description table 17-1 gives an overview of the signals which are described here. 17.6.1 rxd rxd is the sci receiver pin. rxd is available for general-purpose i/o when it is not configured for receiver operation. 17.6.2 txd txd is the sci transmitter pin. txd is available for general-purpose i/o when it is not configured for transmitter operation. 17.7 memory map and registers table 17-1 shows the sci memory map. note: reading unimplemented addresses (0x00cc_000b through 0x00cc_000f) returns 0s. writing to unimplemented addresses has no effect. accessing unimplemented addresses does not generate an error response. table 17-1. signal properties name function port reset state default pullup state rxd receive data pin sciport0 0 disabled txd transmit data pin sciport1 0 disabled f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . serial communications interface modules (sci1 and sci2) memory map and registers mmc2114 MMC2113 mmc2112 ? rev. 1.0 advance information motorola serial communications interface modules (sci1 and sci2) 359 table 17-2. serial communications interface module memory map (1) address bits 7 ? 0 access (2) sci1 sci2 0x00cc_0000 0x00cd_0000 sci baud register high (scibdh) s/u 0x00cc_0001 0x00cd_0001 sci baud register low (scibdl) s/u 0x00cc_0002 0x00cd_0002 sci control register 1 (scicr1) s/u 0x00cc_0003 0x00cd_0003 sci control register 2 (scicr2) s/u 0x00cc_0004 0x00cd_0004 sci status register 1 (scisr1) s/u 0x00cc_0005 0x00cd_0005 sci status register 2 (scisr2) s/u 0x00cc_0006 0x00cd_0006 sci data register high (scidrh) s/u 0x00cc_0007 0x00cd_0007 sci data register low (scidrl) s/u 0x00cc_0008 0x00cd_0008 sci pullup and reduced drive register (scipurd) s/u 0x00cc_0009 0x00cd_0009 sci port data register (sciport) s/u 0x00cc_000a 0x00cd_000a sci data direction register (sciddr) s/u 0x00cc_000b to 0x00cc_000f 0x00cd_000b to 0x00cd_000f reserved (3) s/u 1. each module is assigned 64 kbytes of address space, all of which may not be decoded. accesses outside of the specified module memory map generate a bus error exception. 2. s/u = cpu supervisor or user mode access. user mode accesses to supervisor only addresses have no effect and result in a cycle termination transfer error. 3. within the specified module memory map, accessing reserved addresses does not generate a bus error exception. reads of reserved addresses return 0s and writes have no effect. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . advance information mmc2114 MMC2113 mmc2112 ? rev. 1.0 360 serial communications interface modules (sci1 and sci2) motorola serial communications interface modules (sci1 and sci2) 17.7.1 sci baud rate registers read: anytime write: anytime sbr[12:8], sbr[7:0] ? sci baud rate bits these read/write bits control the sci baud rate: where: 1 sbr[12:0] 8191 note: the baud rate generator is disabled until the te bit or the re bit in scicr2 is set for the first time after reset. the baud rate generator is disabled when sbr[12:0] = 0. writing to scibdh has no effect without also writing to scibdl. writing to scibdh puts the data in a temporary location until data is written to scibdl. address: sci1 ? 0x00cc_0000 sci2 ? 0x00cd_0000 bit 7654321bit 0 read: 0 0 0 sbr12 sbr11 sbr10 sbr9 sbr8 write: reset:00000000 = writes have no effect and the access terminates without a transfer error exception. figure 17-2. sci baud rate register high (scibdh) address: sci1 ? 0x00cc_0001 sci2 ? 0x00cd_0001 bit 7654321bit 0 read: sbr7 sbr6 sbr5 sbr4 sbr3 sbr2 sbr1 sbr0 write: reset:00000100 figure 17-3. sci baud rate register low (scibdl) sci baud rate = f sys 16 x sbr[12:0] f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . serial communications interface modules (sci1 and sci2) memory map and registers mmc2114 MMC2113 mmc2112 ? rev. 1.0 advance information motorola serial communications interface modules (sci1 and sci2) 361 17.7.2 sci control register 1 read: anytime write: anytime loops ? loop select bit this read/write control bit switches the sci between normal mode and loop mode. reset clears loops. 1 = loop mode sci operation 0 = normal mode sci operation the sci operates normally (loops = 0, rsrc = x) when the output of its transmitter is connected to the txd pin, and the input of its receiver is connected to the rxd pin. in loop mode (loops =1, rsrc = 0), the input to the sci receiver is internally disconnected from the rxd pin logic and instead connected to the output of the sci transmitter. the behavior of txd is governed by the ddrsc1 bit in sciddr. if ddrsc1 = 1, the txd pin is driven with the output of the sci transmitter. if ddrsc1 = 0, the txd pin idles high. see 17.14 loop operation for additional information. for either loop mode or single-wire mode to function, both the sci receiver and transmitter must be enabled by setting the re and te bits in scixcr2. note: the rxd pin becomes general-purpose i/o when loops = 1, regardless of the state of the rsrc bit. ddrsc0 in sciddr is the data direction bit for the rxd pin. table 17-3 shows how the loops, rsrc, and ddrsc0 bits affect sci operation and the configuration of the rxd and txd pins. address: sci1 ? 0x00cc_0002 sci2 ? 0x00cd_0002 bit 7654321bit 0 read: loops woms rsrc m wake ilt pe pt write: reset:00000000 figure 17-4. sci control register 1 (scicr1) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . advance information mmc2114 MMC2113 mmc2112 ? rev. 1.0 362 serial communications interface modules (sci1 and sci2) motorola serial communications interface modules (sci1 and sci2) woms ? wired-or mode select bit this read/write bit configures the txd and rxd pins for open-drain operation. this allows all of the txd pins to be tied together in a multiple-transmitter system. woms also affects the txd and rxd pins when they are general-purpose outputs. external pullup resistors are necessary on open-drain outputs. reset clears woms. 1 = txd and rxd pins open-drain when outputs 0 = txd and rxd pins cmos drive when outputs rsrc ? receiver source bit this read/write bit selects the internal feedback path to the receiver input when loops = 1. reset clears rsrc. 1 = receiver input tied to txd pin when loops = 1 0 = receiver input tied to transmitter output when loops = 1 m ? data format mode bit this read/write bit selects 11-bit or 10-bit frames. reset clears m. 1 = frames have 1 start bit, 9 data bits, and 1 stop bit. 0 = frames have 1 start bit, 8 data bits, and 1 stop bit. table 17-3. sci normal, loop, and single-wire mode pin configurations loops rsrc sci mode receiver input rxd pin function ddrsc0 transmitter output txd pin function 0 x normal tied to rxd input buffer receive pin x tied to txd output driver transmit pin 1 0 loop tied to transmitter output general- purpose i/o 0 tied to receiver input only none (idles high) 1 tied to receiver input and txd output driver transmit pin 1 single-wire tied to txd 0 no connection receive pin 1 tied to txd output driver transmit pin f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . serial communications interface modules (sci1 and sci2) memory map and registers mmc2114 MMC2113 mmc2112 ? rev. 1.0 advance information motorola serial communications interface modules (sci1 and sci2) 363 wake ? wakeup bit this read/write bit selects the condition that wakes up the sci receiver when it has been placed in a standby state by setting the rwu bit in scicr2. when wake is set, a logic 1 (address mark) in the most significant bit position of a received data character wakes the receiver. an idle condition on the rxd pin does so when wake = 0. reset clears wake. 1 = address mark receiver wakeup 0 = idle line receiver wakeup ilt ? idle line type bit this read/write bit determines when the receiver starts counting logic 1s as idle character bits. the counting begins either after the start bit or after the stop bit. if the count begins after the start bit, then a string of logic 1s preceding the stop bit may cause false recognition of an idle character. beginning the count after the stop bit avoids false idle character recognition, but requires properly synchronized transmissions. reset clears ilt. 1 = idle frame bit count begins after stop bit. 0 = idle frame bit count begins after start bit. pe ? parity enable bit this read/write bit enables the parity function. when enabled, the parity function inserts a parity bit in the most significant bit position of an sci data word. reset clears pe. 1 = parity function enabled 0 = parity function disabled pt ? parity type bit this read/write bit selects even parity or odd parity. with even parity, an even number of 1s clears the parity bit and an odd number of 1s sets the parity bit. with odd parity, an odd number of 1s clears the parity bit and an even number of 1s sets the parity bit. reset clears pt. 1 = odd parity when pe = 1 0 = even parity when pe = 1 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . advance information mmc2114 MMC2113 mmc2112 ? rev. 1.0 364 serial communications interface modules (sci1 and sci2) motorola serial communications interface modules (sci1 and sci2) 17.7.3 sci control register 2 read: anytime write: anytime tie ? transmitter interrupt enable bit this read/write bit allows the tdre flag to generate interrupt requests. reset clears tie. 1 = tdre interrupt requests enabled 0 = tdre interrupt requests disabled tcie ? transmission complete interrupt enable bit this read/write bit allows the tc flag to generate interrupt requests. reset clears tcie. 1 = tc interrupt requests enabled 0 = tc interrupt requests disabled rie ? receiver interrupt enable bit this read/write bit allows the rdrf and or flags to generate interrupt requests. reset clears rie. 1 = rdrf and or interrupt requests enabled 0 = rdrf and or interrupt requests disabled ilie ? idle line interrupt enable bit this read/write bit allows the idle flag to generate interrupt requests. reset clears ilie. 1 = idle interrupt requests enabled 0 = idle interrupt requests disabled address: sci1 ? 0x00cc_0003 sci2 ? 0x00cd_0003 bit 7654321bit 0 read: tie tcie rie ilie te re rwu sbk write: reset:00000000 figure 17-5. sci control register 2 (scicr2) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . serial communications interface modules (sci1 and sci2) memory map and registers mmc2114 MMC2113 mmc2112 ? rev. 1.0 advance information motorola serial communications interface modules (sci1 and sci2) 365 te ? transmitter enable bit this read/write bit enables the transmitter and configures the txd pin as the transmitter output. toggling te queues an idle frame. reset clears te. 1 = transmitter enabled 0 = transmitter disabled re ? receiver enable bit this read/write bit enables the receiver. reset clears re. 1 = receiver enabled 0 = receiver disabled note: when loops = 0 and te = re = 1, the rxd pin is an input and the txd pin is an output regardless of the state of the ddrsc1 (txd) and ddrsc0 (rxd) bits. rwu ? receiver wakeup bit this read/write bit puts the receiver in a standby state that inhibits receiver interrupt requests. the wake bit determines whether an idle input or an address mark wakes up the receiver and clears rwu. reset clears rwu. 1 = receiver asleep when re = 1 0 = receiver awake when re = 1 sbk ? send break bit setting this read/write bit causes the sci to send break frames of 10 (m = 0) or 11 (m =1) logic 0s. to send one break frame, set sbk and then clear it before the break frame is finished transmitting. as long as sbk is set, the transmitter continues to send break frames. 1 = transmitter sends break frames. 0 = transmitter does not send break frames. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . advance information mmc2114 MMC2113 mmc2112 ? rev. 1.0 366 serial communications interface modules (sci1 and sci2) motorola serial communications interface modules (sci1 and sci2) 17.7.4 sci status register 1 read: anytime write: has no meaning or effect tdre ? transmit data register empty flag the tdre flag is set when the transmit shift register receives a word from the sci data register. it signals that the scidrh and scidrl are empty and can receive new data to transmit. if the tie bit in the scicr2 is also set, tdre generates an interrupt request. clear tdre by reading scisr1 and then writing to scidrl. reset sets tdre. 1 = transmit data register empty 0 = transmit data register not empty tc ? transmit complete flag the tc flag is set when tdre = 1 and no data, preamble, or break frame is being transmitted. it signals that no transmission is in progress. if the tcie bit is set in scicr2, tc generates an interrupt request. when tc is set, the txd pin is idle (logic 1). tc is cleared automatically when a data, preamble, or break frame is queued. clear tc by reading scisr1 with tc set and then writing to scidrl. tc cannot be cleared while a transmission is in progress. reset sets tc. 1 = no transmission in progress 0 = transmission in progress address: sci1 ? 0x00cc_0004 sci2 ? 0x00cd_0004 bit 7654321bit 0 read: tdre tc rdrf idle or nf fe pf write: reset:11000000 = writes have no effect and the access terminates without a transfer error exception. figure 17-6. sci status register 1 (scisr1) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . serial communications interface modules (sci1 and sci2) memory map and registers mmc2114 MMC2113 mmc2112 ? rev. 1.0 advance information motorola serial communications interface modules (sci1 and sci2) 367 rdrf ? receive data register full flag the rdrf flag is set when the data in the receive shift register is transferred to scidrh and scidrl. it signals that the received data is available to the mcu. if the rie bit is set in scicr2, rdrf generates an interrupt request. clear rdrf by reading the scisr1 and then reading scidrl. reset clears rdrf. 1 = received data available in scidrh and scidrl 0 = received data not available in scidrh and scidrl idle ? idle line flag the idle flag is set when 10 (if m = 0) or 11 (if m = 1) consecutive logic 1s appear on the receiver input. if the ilie bit in scicr2 is set, idle generates an interrupt request. once idle is cleared, a valid frame must again set the rdrf flag before an idle condition can set the idle flag. clear idle by reading scisr1 and then reading scidrl. reset clears idle. 1 = receiver idle 0 = receiver active or idle since reset or idle since idle flag last cleared note: when rwu of scicr2 =1, an idle line condition does not set the idle flag. or ? overrun flag the or flag is set if data is not read from scidrl before the receive shift register receives the stop bit of the next frame. this is a receiver overrun condition. if the rie bit in scicr2 is set, or generates an interrupt request. the data in the shift register is lost, but the data already in the scidrh and scidrl is not affected. clear or by reading scisr1 and then reading scidrl. reset clears or. 1 = overrun 0 = no overrun f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . advance information mmc2114 MMC2113 mmc2112 ? rev. 1.0 368 serial communications interface modules (sci1 and sci2) motorola serial communications interface modules (sci1 and sci2) nf ? noise flag the nf flag is set when the sci detects noise on the receiver input. nf is set during the same cycle as the rdrf flag but does not get set in the case of an overrun. clear nf by reading scisr1 and then reading scidrl. reset clears nf. 1 = noise 0 = no noise fe ? framing error flag the fe flag is set when a logic 0 is accepted as the stop bit. fe is set during the same cycle as the rdrf flag but does not get set in the case of an overrun. fe inhibits further data reception until it is cleared. clear fe by reading scisr1 and then reading scidrl. reset clears fe. 1 = framing error 0 = no framing error pf ? parity error flag the pf flag is set when pe = 1 and the parity of the received data does not match its parity bit. clear pf by reading scisr1 and then reading scidrl. reset clears pf. 1 = parity error 0 = no parity error f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . serial communications interface modules (sci1 and sci2) memory map and registers mmc2114 MMC2113 mmc2112 ? rev. 1.0 advance information motorola serial communications interface modules (sci1 and sci2) 369 17.7.5 sci status register 2 read: anytime write: has no meaning or effect raf ? receiver active flag the raf flag is set when the receiver detects a logic 0 during the rt1 time period of the start bit search. when the receiver detects an idle character, it clears raf. reset clears raf. 1 = reception in progress 0 = no reception in progress address: sci1 ? 0x00cc_0005 sci2 ? 0x00cd_0005 bit 7654321bit 0 read: 0000000raf write: reset:00000000 = writes have no effect and the access terminates without a transfer error exception. figure 17-7. sci status register 2 (scisr2) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . advance information mmc2114 MMC2113 mmc2112 ? rev. 1.0 370 serial communications interface modules (sci1 and sci2) motorola serial communications interface modules (sci1 and sci2) 17.7.6 sci data registers read: anytime write: anytime; writing to r8 has no effect r8 ? receive bit 8 the r8 bit is the ninth received data bit when using the 9-bit data format (m = 1). reset clears r8. t8 ? transmit bit 8 the t8 bit is the ninth transmitted data bit when using the 9-bit data format (m = 1). reset clears t8. r[7:0] ? receive bits [7:0] the r[7:0] bits are receive bits [7:0] when using the 9-bit or 8-bit data format. reset clears r[7:0]. address: sci1 ? 0x00cc_0006 sci2 ? 0x00cd_0006 bit 7654321bit 0 read: r8 t8 000000 write: reset:00000000 = writes have no effect and the access terminates without a transfer error exception. figure 17-8. sci data register high (scidrh) address: sci1 ? 0x00cc_0007 sci2 ? 0x00cd_0007 bit 7654321bit 0 read: r7 r6 r5 r4 r3 r2 r1 r0 write: t7 t6 t5 t4 t3 t2 t1 t0 reset:00000000 figure 17-9. sci data register low (scidrl) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . serial communications interface modules (sci1 and sci2) memory map and registers mmc2114 MMC2113 mmc2112 ? rev. 1.0 advance information motorola serial communications interface modules (sci1 and sci2) 371 t[7:0] ? transmit bits [7:0] the t[7:0] bits are transmit bits [7:0] when using the 9-bit or 8-bit data format. reset clears t[7:0]. note: if the value of t8 is the same as in the previous transmission, t8 does not have to be rewritten. the same value is transmitted until t8 is rewritten. when using the 8-bit data format, only scidrl needs to be accessed. when using 8-bit write instructions to transmit 9-bit data, write first to scidrh, then to scidrl. 17.7.7 sci pullup and reduced drive register write: anytime scisdoz ? sci stop in doze mode bit the scisdoz bit disables the sci in doze mode. 1 = sci disabled in doze mode 0 = sci enabled in doze mode rsvd[5:1] ? reserved writing to these read/write bits updates their values but has no effect on functionality. rdpsci ? reduced drive bit this read/write bit controls the drive capability of txd and rxd. 1 = reduced txd and rxd pin drive 0 = full txd and rxd pin drive address: sci1 ? 0x00cc_0008 sci2 ? 0x00cd_0008 bit 7654321bit 0 read: scisdoz 0 rsvd5 rdpsci 00 rsvd1 pupsci write: reset:00000000 = writes have no effect and the access terminates without a transfer error exception. figure 17-10. sci pullup and reduced drive register (scipurd) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . advance information mmc2114 MMC2113 mmc2112 ? rev. 1.0 372 serial communications interface modules (sci1 and sci2) motorola serial communications interface modules (sci1 and sci2) pupsci ? pullup enable bit this read/write bit enables the pullups on pins txd and rxd. if a pin is programmed as an output, the pullup is disabled. 1 = txd and rxd pullups enabled 0 = txd and rxd pullups disabled 17.7.8 sci port data register read: anytime; when ddrscx = 0, its pin is configured as an input, and reading portscx returns the pin level; when ddrscx = 1, its pin is configured as an output, and reading portscx returns the pin driver output level. write: anytime; data stored in internal latch drives pin only if ddrsc bit = 1 rsvd[7:2] ? reserved writing to these read/write bits updates their values but has no effect on functionality. portsc[1:0] ? sciport data bits these are the read/write data bits of the sci port. note: writes to sciport do not change the pin state when the pin is configured for sci input. to ensure correct reading of the sci pin values from sciport, always wait at least one cycle after writing to sciddr before reading sciport. address: sci1 ? 0x00cc_0009 sci2 ? 0x00cd_0009 bit 7654321bit 0 read: rsvd7 rsvd6 rsvd5 rsvd4 rsvd3 rsvd2 portsc1 portsc0 write: reset:00000000 pin function: txd rxd figure 17-11. sci port data register (sciport) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . serial communications interface modules (sci1 and sci2) memory map and registers mmc2114 MMC2113 mmc2112 ? rev. 1.0 advance information motorola serial communications interface modules (sci1 and sci2) 373 17.7.9 sci data direction register read: anytime write: anytime rsvd[7:2] ? reserved writing to these read/write bits updates their values but has no effect on functionality. ddrsc[1:0] ? sciport data direction bits these bits control the data direction of the sciport pins. reset clears ddrsc[1:0]. 1 = corresponding pin configured as output 0 = corresponding pin configured as input note: when loops = 0 and te = re = 1, the rxd pin is an input and the txd pin is an output regardless of the state of the ddrsc1 (txd) and ddrsc0 (rxd) bits. address: sci1 ? 0x00cc_000a sci2 ? 0x00cd_000a bit 7654321bit 0 read: rsvd7 rsvd6 rsvd5 rsvd4 rsvd3 rsvd2 ddrsc1 ddrsc0 write: reset:00000000 figure 17-12. sci data direction register (sciddr) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . advance information mmc2114 MMC2113 mmc2112 ? rev. 1.0 374 serial communications interface modules (sci1 and sci2) motorola serial communications interface modules (sci1 and sci2) 17.8 functional description the sci allows full-duplex, asynchronous, non-return-to-zero (nrz) serial communication between the mcu and remote devices, including other mcus. the sci transmitter and receiver operate independently, although they use the same baud rate generator. the cpu monitors the status of the sci, writes the data to be transmitted, and processes received data. 17.9 data format the sci uses the standard nrz mark/space data format shown in figure 17-13 . each frame has a start bit, eight or nine data bits, and one or two stop bits. clearing the m bit in sccr1 configures the sci for 10-bit frames. setting the m bit configures the sci for 11-bit frames. when the sci is configured for 9-bit data, the ninth data bit is the t8 bit in sci data register high (scidrh). it remains unchanged after transmission and can be used repeatedly without rewriting it. a frame with nine data bits has a total of 11 bits. figure 17-13. sci data formats 10-bit frame start bit 0 bit 1 bit 2 bit 3 bit 4 bit 5 bit 6 bit 7 bit stop bit next start bit m = 0 in scicr1 start bit 0 bit 1 bit 2 bit 3 bit 4 bit 5 bit 6 bit 7 bit stop bit next start bit 11-bit frame m = 1 in scicr1 bit 8 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . serial communications interface modules (sci1 and sci2) baud rate generation mmc2114 MMC2113 mmc2112 ? rev. 1.0 advance information motorola serial communications interface modules (sci1 and sci2) 375 17.10 baud rate generation a 13-bit modulus counter in the baud rate generator derives the baud rate for both the receiver and the transmitter. the value from 0 to 8191 written to scibdh and scibdl determines the system clock divisor. the baud rate clock is synchronized with the bus clock and drives the receiver. the baud rate clock divided by 16 drives the transmitter. the receiver acquisition rate is 16 samples per bit time. baud rate generation is subject to two sources of error: 1. integer division of the module clock may not give the exact target frequency. 2. synchronization with the bus clock can cause phase shift. table 17-4. example baud rates (system clock = 33 mhz) sbr[12:0] receiver clock (hz) transmitter clock (hz) target baud rate percent error 0x0012 1,833,333.3 114,583.3 115,200 0.54 0x0024 916,666.7 57,291.7 57,600 0.54 0x0036 611,111.1 38,194.4 38,400 0.54 0x003d 540,983.6 33,811.4 33,600 0.63 0x0048 458,333.3 28,645.8 28,800 0.54 0x006b 308,411.2 19,275.7 19,200 0.39 0x0008f 230,769.2 14,423.1 14,400 0.16 0x00d7 153,488.4 95,93.0 9,600 0.07 0x01ae 76,744.2 4,796.5 4,800 0.07 0x035b 38,416.8 2,401.0 2,400 0.04 0x06b7 19,197.2 1,199.8 1,200 0.01 0x0d6d 9,601.4 600.1 600 0.01 0x1adb 4,800.0 300.0 300 0 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . advance information mmc2114 MMC2113 mmc2112 ? rev. 1.0 376 serial communications interface modules (sci1 and sci2) motorola serial communications interface modules (sci1 and sci2) 17.11 transmitter figure 17-14. transmitter block diagram pe pt h876543210l 11-bit transmit shift register stop start tdre tie tcie sbk tc msb sci data register load from scidr shift enable preamble (all 1s) break (all 0s) transmitter control m ipbus sbr[12:0] 16 txd tdre tc system loop loops clock te to control receiver woms pin force pin direction pin buffer and control baud divider parity generation interrupt request interrupt request f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . serial communications interface modules (sci1 and sci2) transmitter mmc2114 MMC2113 mmc2112 ? rev. 1.0 advance information motorola serial communications interface modules (sci1 and sci2) 377 17.11.1 frame length the transmitter can generate either 10-bit or 11-bit frames. in scicr1, the m bit selects frame length, and the pe bit enables the parity function. one data bit may be an address mark or an extra stop bit. all frames begin with a start bit and end with one or two stop bits. when transmitting 9-bit data, bit t8 in sci data register high (scidrh) is the ninth bit (bit 8). table 17-5. example 10-bit and 11-bit frames m bit frame length start bit data bits parity bit address mark (1) 1. when implementing a multidrop network using the sci, the address mark bit is used to designate subsequent data frames as a network address and not device data. stop bit(s) 0 10 bits 1 8 no no 1 1 7 no no 2 17no yes 1 17yes no 1 111 bits 1 9 no no 1 1 8 no no 2 18no yes 1 18yes no 1 17no yes 2 17yes no 2 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . advance information mmc2114 MMC2113 mmc2112 ? rev. 1.0 378 serial communications interface modules (sci1 and sci2) motorola serial communications interface modules (sci1 and sci2) 17.11.2 transmitting a frame to begin an sci transmission: 1. configure the sci: a. write a baud rate value to scibdh and scibdl. b. write to scicr1 to: i. enable or disable loop mode and select the receiver feedback path ii. select open-drain or wired-or sci outputs iii. select 10-bit or 11-bit frames iv. select the receiver wakeup condition: address mark or idle line v. select idle line type vi. enable or disable the parity function and select odd or even parity c. write to scicr2 to: i. enable or disable tdre, tc, rdrf, and idle interrupt requests ii. enable the transmitter and queue a break frame iii. enable or disable the receiver iv. put the receiver in standby if required 2. transmit a byte: a. clear the tdre flag by reading scisr1 and, if sending 9-bit data, write the ninth data bit to scdrh. b. write the byte to be transmitted (or low-order 8 bits if sending 9-bit data) to scidrl. 3. repeat step 2 for each subsequent transmission. writing the te bit from 0 to 1 loads the transmit shift register with a preamble of 10 (if m = 0) or 11 (if m = 1) logic 1s. when the preamble shifts out, the sci transfers the data from scidrh and scidrl to the transmit shift register. the transmit shift register prefaces the data with a 0 start bit and appends the data with a 1 stop bit and begins shifting out the frame. the sci sets the tdre flag every time it transfers data from scidrh and scidrl to the transmit shift register. tdre indicates that scidrh f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . serial communications interface modules (sci1 and sci2) transmitter mmc2114 MMC2113 mmc2112 ? rev. 1.0 advance information motorola serial communications interface modules (sci1 and sci2) 379 and scidrl can accept new data. if the tie bit is set, tdre generates an interrupt request. note: scidrh and scidrl transfer data to the transmit shift register and sets tdre 9/16ths of a bit time after the previous frame ? s stop bit starts to shift out. hardware supports odd or even parity. when parity is enabled, the most significant data bit is the parity bit. when the transmit shift register is not transmitting a frame, the txd pin goes to the idle condition, logic 1. clearing the te bit while the transmitter is idle will return control of the txd pin to the sci data direction (sciddr) and sci port (sciport) registers. if the te bit is cleared while a transmission is in progress (while tc = 0), the frame in the transmit shift register continues to shift out. then the txd pin reverts to being a general-purpose i/o pin even if there is data pending in the sci data register. to avoid accidentally cutting off a message, always wait until tdre is set after the last frame before clearing te. to separate messages with preambles with minimum idle line time, use this sequence between messages: 1. write the last byte of the first message to scidrh and scidrl. 2. wait until the tdre flag is set, indicating the transfer of the last frame to the transmit shift register. 3. queue a preamble by clearing and then setting the te bit. 4. write the first byte of the second message to scidrh and scidrl. when the sci relinquishes the txd pin, the sciport and sciddr registers control the txd pin. to force txd high when turning off the transmitter, set bit 1 of the sci port register (sciport) and bit 1 of the sci data direction register (sciddr). the txd pin goes high as soon as the sci relinquishes control of it. see 17.7.8 sci port data register and 17.7.9 sci data direction register . f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . advance information mmc2114 MMC2113 mmc2112 ? rev. 1.0 380 serial communications interface modules (sci1 and sci2) motorola serial communications interface modules (sci1 and sci2) 17.11.3 break frames setting the sbk bit in scicr2 loads the transmit shift register with a break frame. a break frame contains all logic 0s and has no start, stop, or parity bit. break frame length depends on the m bit in the scicr1 register. as long as sbk is set, the sci continuously loads break frames into the transmit shift register. after sbk is clear, the transmit shift register finishes transmitting the last break frame and then transmits at least one logic 1. the automatic logic 1 at the end of a break frame guarantees the recognition of the next start bit. the sci recognizes a break frame when a start bit is followed by eight or nine 0 data bits and a 0 where the stop bit should be. receiving a break frame has these effects on sci registers: sets the fe flag sets the rdrf flag clears the scidrh and scidrl may set the or flag, nf flag, pe flag, or the raf flag 17.11.4 idle frames an idle frame contains all logic 1s and has no start, stop, or parity bit. idle frame length depends on the m bit in the scicr1 register. the preamble is a synchronizing idle frame that begins the first transmission after writing the te bit from 0 to 1. if the te bit is cleared during a transmission, the txd pin becomes idle after completion of the transmission in progress. clearing and then setting the te bit during a transmission queues an idle frame to be sent after the frame currently being transmitted. note: when queueing an idle frame, return the te bit to logic 1 before the stop bit of the current frame shifts out to the txd pin. setting te after the stop bit appears on txd causes data previously written to scidrh and scidrl to be lost. toggle te to queue an idle frame, while the tdre flag is set, immediately before writing new data to scidrh and scidrl. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . serial communications interface modules (sci1 and sci2) receiver mmc2114 MMC2113 mmc2112 ? rev. 1.0 advance information motorola serial communications interface modules (sci1 and sci2) 381 17.12 receiver figure 17-15. sci receiver block diagram 17.12.1 frame length the receiver can handle either 8-bit or 9-bit data. the state of the m bit in scicr1 selects frame length. when receiving 9-bit data, bit r8 in scidrh is the ninth bit (bit 8). 17.12.2 receiving a frame when the sci receives a frame, the receive shift register shifts the frame in from the rxd pin. all 1s m wake ilt pe pt re h876543210l 11-bit receive shift register stop start data wakeup parity checking msb sci data register r8 rie ilie rdrf or nf fe pe ipbus rxd system idle rdrf/or sbr[12:0] baud divider loop loops rsrc from txd or transmitter clock idle raf recovery control logic rwu interrupt request interrupt request f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . advance information mmc2114 MMC2113 mmc2112 ? rev. 1.0 382 serial communications interface modules (sci1 and sci2) motorola serial communications interface modules (sci1 and sci2) after an entire frame shifts into the receive shift register, the data portion of the frame transfers to scidrh and scidrl. the rdrf flag is set, indicating that the received data can be read. if the rie bit is also set, rdrf generates an interrupt request. 17.12.3 data sampling the receiver samples the rxd pin at the rt clock rate. the rt clock is an internal signal with a frequency 16 times the baud rate. to adjust for baud rate mismatch, the rt clock resynchronizes: after every start bit after the receiver detects a data bit change from logic 1 to logic 0 (after the majority of data bit samples at rt8, rt9, and rt10 returns a valid logic 1 and the majority of the next rt8, rt9, and rt10 samples returns a valid logic 0) to locate the start bit, data recovery logic does an asynchronous search for a 0 preceded by three 1s. when the falling edge of a possible start bit occurs, the rt clock begins to count to 16. figure 17-16. receiver data sampling reset rt clock rt1 rt1 rt1 rt1 rt1 rt1 rt1 rt1 rt1 rt2 rt3 rt4 rt5 rt8 rt7 rt6 rt11 rt10 rt9 rt15 rt14 rt13 rt12 rt16 rt1 rt2 rt3 rt4 samples rt clock rt clock count start bit rxd start bit qualification start bit data sampling 11 1 1 1 1 110000 0 00 lsb verification f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . serial communications interface modules (sci1 and sci2) receiver mmc2114 MMC2113 mmc2112 ? rev. 1.0 advance information motorola serial communications interface modules (sci1 and sci2) 383 to verify the start bit and to detect noise, data recovery logic takes samples at rt3, rt5, and rt7. if start bit verification is not successful, the rt clock is reset and a new search for a start bit begins. to determine the value of a data bit and to detect noise, recovery logic takes samples at rt8, rt9, and rt10. note: the rt8, rt9, and rt10 data samples do not affect start bit verification. if any or all of the rt8, rt9, and rt10 samples are logic 1s following a successful start bit verification, the nf flag is set and the receiver interprets the bit as a start bit (logic 0). table 17-6. start bit verification rt3, rt5, and rt7 samples start bit verification noise flag 000 yes 0 001 yes 1 010 yes 1 011 no 0 100 yes 1 101 no 0 110 no 0 111 no 0 table 17-7. data bit recovery rt8, rt9, and rt10 samples data bit determination noise flag 000 0 0 001 0 1 010 0 1 011 1 1 100 0 1 101 1 1 110 1 1 111 1 0 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . advance information mmc2114 MMC2113 mmc2112 ? rev. 1.0 384 serial communications interface modules (sci1 and sci2) motorola serial communications interface modules (sci1 and sci2) the rt8, rt9, and rt10 samples also verify stop bits. in figure 17-17 , the verification samples rt3 and rt5 determine that the first low detected was noise and not the beginning of a start bit. the rt clock is reset and the start bit search begins again. the nf flag is not set because the noise occurred before the start bit was verified. figure 17-17. start bit search example 1 table 17-8. stop bit recovery rt8, rt9, and rt10 samples framing error flag noise flag 000 1 0 001 1 1 010 1 1 011 0 1 100 1 1 101 0 1 110 0 1 111 0 0 reset rt clock rt1 rt1 rt1 rt1 rt2 rt3 rt4 rt5 rt1 rt1 rt2 rt3 rt4 rt7 rt6 rt5 rt10 rt9 rt8 rt14 rt13 rt12 rt11 rt15 rt16 rt1 rt2 rt3 samples rt clock rt clock count start bit rxd 11 0 1 111000 00 lsb 0 0 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . serial communications interface modules (sci1 and sci2) receiver mmc2114 MMC2113 mmc2112 ? rev. 1.0 advance information motorola serial communications interface modules (sci1 and sci2) 385 in figure 17-18 , noise is perceived as the beginning of a start bit although the rt3 sample is high. the rt3 sample sets the noise flag. although the perceived bit time is misaligned, the rt8, rt9, and rt10 data samples are within the bit time, and data recovery is successful. figure 17-18. start bit search example 2 in figure 17-19 a large burst of noise is perceived as the beginning of a start bit, although the rt5 sample is high. the rt5 sample sets the noise flag. although this is a worst-case misalignment of perceived bit time, the data samples rt8, rt9, and rt10 are within the bit time and data recovery is successful. figure 17-19. start bit search example 3 reset rt clock rt1 rt1 rt1 rt1 rt1 rt1 rt2 rt3 rt4 rt5 rt6 rt7 rt8 rt11 rt10 rt9 rt14 rt13 rt12 rt2 rt1 rt16 rt15 rt3 rt4 rt5 rt6 rt7 samples rt clock rt clock count actual start bit rxd 11 1 1 11000 0 lsb 0 0 perceived start bit reset rt clock rt1 rt1 rt1 rt1 rt2 rt3 rt4 rt5 rt6 rt7 rt8 rt9 rt10 rt13 rt12 rt11 rt16 rt15 rt14 rt4 rt3 rt2 rt1 rt5 rt6 rt7 rt8 rt9 samples rt clock rt clock count actual start bit rxd 10 1 11000 0 lsb 0 perceived start bit f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . advance information mmc2114 MMC2113 mmc2112 ? rev. 1.0 386 serial communications interface modules (sci1 and sci2) motorola serial communications interface modules (sci1 and sci2) figure 17-20 shows the effect of noise early in the start bit time. although this noise does not affect proper synchronization with the start bit time, it does set the noise flag. figure 17-20. start bit search example 4 figure 17-21 shows a burst of noise near the beginning of the start bit that resets the rt clock. the sample after the reset is low but is not preceded by three high samples that would qualify as a falling edge. depending on the timing of the start bit search and on the data, the frame may be missed entirely or it may set the framing error flag. figure 17-21. start bit search example 5 reset rt clock rt1 rt1 rt1 rt1 rt1 rt1 rt1 rt1 rt1 rt1 rt2 rt3 rt4 rt7 rt6 rt5 rt10 rt9 rt8 rt14 rt13 rt12 rt11 rt15 rt16 rt1 rt2 rt3 samples rt clock rt clock count perceived and actual start bit rxd 11 1 1100 1 lsb 1 1 1 1 reset rt clock rt1 rt1 rt1 rt1 rt1 rt1 rt1 rt1 rt1 rt1 rt2 rt3 rt4 rt7 rt6 rt5 rt1 rt1 rt1 rt1 rt1 rt1 rt1 rt1 rt1 rt1 rt1 rt1 samples rt clock rt clock count start bit rxd 11 1 1101 0 lsb 1 1 1 1 1 00 0 00 0 0 0 no start bit found f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . serial communications interface modules (sci1 and sci2) receiver mmc2114 MMC2113 mmc2112 ? rev. 1.0 advance information motorola serial communications interface modules (sci1 and sci2) 387 in figure 17-22 a noise burst makes the majority of data samples rt8, rt9, and rt10 high. this sets the noise flag but does not reset the rt clock. in start bits only, the rt8, rt9, and rt10 data samples are ignored. figure 17-22. start bit search example 6 17.12.4 framing errors if the data recovery logic does not detect a 1 where the stop bit should be in an incoming frame, it sets the fe flag in scisr1. a break frame also sets the fe flag because a break frame has no stop bit. the fe flag is set at the same time that the rdrf flag is set. 17.12.5 baud rate tolerance a transmitting device may be operating at a baud rate below or above the receiver baud rate. accumulated bit time misalignment can cause one of the rt8, rt9, and rt10 stop bit data samples to fall outside the stop bit. a noise error occurs if the samples are not all the same value. if more than one of the samples is outside the stop bit, a framing error occurs. in most applications, the baud rate tolerance is much more than the degree of misalignment that is likely to occur. as the receiver samples an incoming frame, it resynchronizes the rt clock on any valid falling edge within the frame. resynchronization within frames corrects misalignments between transmitter bit times and receiver bit times. reset rt clock rt1 rt1 rt1 rt1 rt1 rt1 rt1 rt1 rt1 rt1 rt2 rt3 rt4 rt7 rt6 rt5 rt10 rt9 rt8 rt14 rt13 rt12 rt11 rt15 rt16 rt1 rt2 rt3 samples rt clock rt clock count start bit rxd 11 1 1100 0 lsb 1 1 1 1 0 11 0 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . advance information mmc2114 MMC2113 mmc2112 ? rev. 1.0 388 serial communications interface modules (sci1 and sci2) motorola serial communications interface modules (sci1 and sci2) 17.12.5.1 slow data tolerance figure 17-23 shows how much a slow received frame can be misaligned without causing a noise error or a framing error. the slow stop bit begins at rt8 instead of rt1 but arrives in time for the stop bit data samples at rt8, rt9, and rt10. figure 17-23. slow data for 8-bit data, sampling of the stop bit takes the receiver: 9bittimes 16 rt cycles + 10 rt cycles = 154 rt cycles. with the misaligned data shown in figure 17-23 , the receiver counts 154 rt cycles at the point when the count of the transmitting device is: 9bittimes 16 rt cycles + 3 rt cycles = 147 rt cycles. the maximum percent difference between the receiver count and the transmitter count for slow 8-bit data with no errors is: for 9-bit data, sampling of the stop bit takes the receiver: 10 bit times 16 rt cycles + 10 rt cycles = 170 rt cycles. with the misaligned data shown in figure 17-23 , the receiver counts 170 rt cycles at the point when the count of the transmitting device is: 10 bit times 16 rt cycles + 3 rt cycles = 163 rt cycles. the maximum percent difference between the receiver count and the transmitter count for slow 9-bit data with no errors is: msb stop rt1 rt2 rt3 rt4 rt5 rt6 rt7 rt8 rt9 rt10 rt11 rt12 rt13 rt14 rt15 rt16 data samples receiver rt clock 154 147 ? 154 ------------------------- - 100 4.54% = 170 163 ? 170 ------------------------- - 100 4.12% = f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . serial communications interface modules (sci1 and sci2) receiver mmc2114 MMC2113 mmc2112 ? rev. 1.0 advance information motorola serial communications interface modules (sci1 and sci2) 389 17.12.5.2 fast data tolerance figure 17-24 shows how much a fast received frame can be misaligned without causing a noise error or a framing error. the fast stop bit ends at rt10 instead of rt16 but is still sampled at rt8, rt9, and rt10. figure 17-24. fast data for 8-bit data, sampling of the stop bit takes the receiver: 9bittimes 16 rt cycles + 10 rt cycles = 154 rt cycles. with the misaligned data shown in figure 17-24 , the receiver counts 154 rt cycles at the point when the count of the transmitting device is: 10 bit times 16 rt cycles = 160 rt cycles. the maximum percent difference between the receiver count and the transmitter count for fast 8-bit data with no errors is: for 9-bit data, sampling of the stop bit takes the receiver: 10 bit times 16 rt cycles + 10 rt cycles = 170 rt cycles. with the misaligned data shown in figure 17-24 , the receiver counts 170 rt cycles at the point when the count of the transmitting device is: 11 bit times 16 rt cycles = 176 rt cycles. the maximum percent difference between the receiver count and the transmitter count for fast 9-bit data with no errors is: idle or next frame stop rt1 rt2 rt3 rt4 rt5 rt6 rt7 rt8 rt9 rt10 rt11 rt12 rt13 rt14 rt15 rt16 data samples receiver rt clock 154 160 ? 154 ------------------------- - 100 3.90% = 170 176 ? 170 ------------------------- - 100 3.53% = f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . advance information mmc2114 MMC2113 mmc2112 ? rev. 1.0 390 serial communications interface modules (sci1 and sci2) motorola serial communications interface modules (sci1 and sci2) 17.12.6 receiver wakeup so that the sci can ignore transmissions intended only for other devices in multiple-receiver systems, the receiver can be put into a standby state. setting the rwu bit in scicr2 puts the receiver into a standby state during which receiver interrupts are disabled. the transmitting device can address messages to selected receivers by including addressing information in the initial frame or frames of each message. the wake bit in scicr1 determines how the sci is brought out of the standby state to process an incoming message. the wake bit enables either idle line wakeup or address mark wakeup. 17.12.6.1 idle input line wakeup (wake = 0) when wake = 0, an idle condition on the rxd pin clears the rwu bit and wakes up the receiver. the initial frame or frames of every message contain addressing information. all receivers evaluate the addressing information, and receivers for which the message is addressed process the frames that follow. any receiver for which a message is not addressed can set its rwu bit and return to the standby state. the rwu bit remains set and the receiver remains on standby until another idle frame appears on the rxd pin. idle line wakeup requires that messages be separated by at least one idle frame and that no message contains idle frames. the idle frame that wakes up the receiver does not set the idle flag or the rdrf flag. the ilt bit in scicr1 determines whether the receiver begins counting logic 1s as idle frame bits after the start bit or after the stop bit. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . serial communications interface modules (sci1 and sci2) receiver mmc2114 MMC2113 mmc2112 ? rev. 1.0 advance information motorola serial communications interface modules (sci1 and sci2) 391 17.12.6.2 address mark wakeup (wake = 1) when wake = 1, an address mark clears the rwu bit and wakes up the receiver. an address mark is a 1 in the most significant data bit position. the receiver interprets the data as address data. when using address mark wakeup, the msb of all non-address data must be 0. user code must compare the address data to the receiver ? s address and, if the addresses match, the receiver processes the frames that follow. if the addresses do not match, user code must put the receiver back to sleep by setting the rwu bit. the rwu bit remains set and the receiver remains on standby until another address frame appears on the rxd pin. the address mark clears the rwu bit before the stop bit is received and sets the rdrf flag. address mark wakeup allows messages to contain idle frames but requires that the most significant byte (msb) be reserved for address data. note: with the wake bit clear, setting the rwu bit after the rxd pin has been idle can cause the receiver to wake up immediately. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . advance information mmc2114 MMC2113 mmc2112 ? rev. 1.0 392 serial communications interface modules (sci1 and sci2) motorola serial communications interface modules (sci1 and sci2) 17.13 single-wire operation normally, the sci uses the txd pin for transmitting and the rxd pin for receiving (loops = 0, rsrc = x). in single-wire mode, the rxd pin is disconnected from the sci and is available as a general-purpose i/o pin. the sci uses the txd pin for both receiving and transmitting. in single-wire mode (loops = 1, rxrc = 1), setting the data direction bit for the txd pin configures txd as the output for transmitted data. clearing the data direction bit configures txd as the input for received data. figure 17-25. single-wire operation (loops = 1, rsrc = 1) enable single-wire operation by setting the loops bit and the rsrc bit in scicr1. setting the loops bit disables the path from the rxd pin to the receiver. setting the rsrc bit connects the receiver input to the output of the txd pin driver. both the transmitter and receiver must be enabled (te = 1 and re = 1). the woms bit in the scicr1 register configures the txd pin for full cmos drive or for open-drain drive. woms controls the txd pin in both normal operation and in single-wire operation. when woms is set, the ddr bit for the txd pin does not have to be cleared for transmitter to receive data. txd sciddr txd sciddr general-purpose i/o general-purpose i/o nc transmitter woms txd receiver transmitter receiver rxd txd rxd bit = 1 bit = 0 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . serial communications interface modules (sci1 and sci2) loop operation mmc2114 MMC2113 mmc2112 ? rev. 1.0 advance information motorola serial communications interface modules (sci1 and sci2) 393 17.14 loop operation in loop mode (loops = 1, rsrc = 0), the transmitter output goes to the receiver input. the rxd pin is disconnected from the sci and is available as a general-purpose i/o pin. setting the ddr bit for the txd pin connects the transmitter output to the txd pin. clearing the data direction bit disconnects the transmitter output from the txd pin. figure 17-26. loop operation (loops = 1, rsrc = 0) enable loop operation by setting the loops bit and clearing the rsrc bit in scicr1. setting the loops bit disables the path from the rxd pin to the receiver. clearing the rsrc bit connects the transmitter output to the receiver input. both the transmitter and receiver must be enabled (te = 1 and re = 1). the woms bit in scicr1 configures the txd pin for full cmos drive or for open-drain drive. woms controls the txd pin during both normal operation and loop operation. txd woms txd sciddr txd sciddr general-purpose i/o general-purpose i/o h transmitter receiver transmitter receiver woms rxd rxd txd bit = 1 bit = 0 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . advance information mmc2114 MMC2113 mmc2112 ? rev. 1.0 394 serial communications interface modules (sci1 and sci2) motorola serial communications interface modules (sci1 and sci2) 17.15 i/o ports the sciport register is associated with two pins: the txd pin is connected to sciport1. the rxd pin is connected to sciport0. the sci data direction register (sciddr) configures the pins as inputs or outputs (see 17.7.9 sci data direction register ). the sci pullup and reduced drive register (scipurd) controls pin drive capability and enables or disables pullups (see 17.7.7 sci pullup and reduced drive register ). the woms bit in sci control register 1 (scicr1) configures output ports as full cmos drive outputs or as open-drain outputs (see 17.7.2 sci control register 1 ). table 17-9. sci port control summary pullup enable control reduced drive control wired-or mode control register bit reset state register bit reset state register bit reset state scipurd pupsci 0 scipurd rdpsci 0 scicr1 woms cmos drive f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . serial communications interface modules (sci1 and sci2) reset mmc2114 MMC2113 mmc2112 ? rev. 1.0 advance information motorola serial communications interface modules (sci1 and sci2) 395 17.16 reset reset initializes the sci registers to a known startup state as described in 17.7 memory map and registers . 17.17 interrupts table 17-10 lists the five interrupt requests associated with each sci module. 17.17.1 transmit data register empty the tdre flag is set when the transmit shift register receives a byte from the sci data register. it signals that scidrh and scidrl are empty and can receive new data to transmit. if the tie bit in scicr2 is also set, tdre generates an interrupt request. clear tdre by reading scisr1 and then writing to scidrl. reset sets tdre. 17.17.2 transmission complete the tc flag is set when tdre = 1 and no data, preamble, or break frame is being transmitted. it signals that no transmission is in progress. if the tcie bit is set in scicr2, tc generates an interrupt request. when tc is set, the txd pin is idle (logic 1). tc is cleared automatically when a data, preamble, or break frame is queued. clear tc by reading scisr1 with tc set and then writing to the scidrl register. tc cannot be cleared while a transmission is in progress. table 17-10. sci interrupt request sources source flag enable bit transmitter tdre tie tc tcie receiver rdrf rie or rie idle ilie f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . advance information mmc2114 MMC2113 mmc2112 ? rev. 1.0 396 serial communications interface modules (sci1 and sci2) motorola serial communications interface modules (sci1 and sci2) 17.17.3 receive data register full the rdrf flag is set when the data in the receive shift register transfers to scidrh and scidrl. it signals that the received data is available to be read. if the rie bit is set in scicr2, rdrf generates an interrupt request. clear rdrf by reading scisr1 and then reading scidrl. 17.17.4 idle receiver input the idle flag is set when 10 (if m = 0) or 11 (if m = 1) consecutive logic 1s appear on the receiver input. this signals an idle condition on the receiver input. if the ilie bit in scicr2 is set, idle generates an interrupt request. once idle is cleared, a valid frame must again set the rdrf flag before an idle condition can set the idle flag. clear idle by reading scisr1 with idle set and then reading scidrl. 17.17.5 overrun the or flag is set if data is not read from scidrl before the receive shift register receives the stop bit of the next frame. this signals a receiver overrun condition. if the rie bit in scicr2 is set, or generates an interrupt request. the data in the shift register is lost, but the data already in scidrh and scidrl is not affected. clear or by reading scisr1 and then reading scidrl. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . mmc2114 MMC2113 mmc2112 ? rev. 1.0 advance information motorola serial peripheral interface module (spi) 397 advance information ? mmc2114, MMC2113, and mmc2112 section 18. serial peripheral interface module (spi) 18.1 contents 18.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .398 18.3 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .398 18.4 modes of operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .399 18.5 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .399 18.6 signal description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .400 18.6.1 miso (master in/slave out) . . . . . . . . . . . . . . . . . . . . . . . .400 18.6.2 mosi (master out/slave in) . . . . . . . . . . . . . . . . . . . . . . . .400 18.6.3 sck (serial clock) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .401 18.6.4 ss (slave select) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .401 18.7 memory map and registers . . . . . . . . . . . . . . . . . . . . . . . . . .401 18.7.1 spi control register 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 402 18.7.2 spi control register 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 405 18.7.3 spi baud rate register . . . . . . . . . . . . . . . . . . . . . . . . . . .406 18.7.4 spi status register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .408 18.7.5 spi data register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .409 18.7.6 spi pullup and reduced drive register . . . . . . . . . . . . . .410 18.7.7 spi port data register . . . . . . . . . . . . . . . . . . . . . . . . . . . .411 18.7.8 spi port data direction register . . . . . . . . . . . . . . . . . . . .412 18.8 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .413 18.8.1 master mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .414 18.8.2 slave mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .415 18.8.3 transmission formats . . . . . . . . . . . . . . . . . . . . . . . . . . . .416 18.8.3.1 transfer format when cpha = 1 . . . . . . . . . . . . . . . . .416 18.8.3.2 transfer format when cpha = 0 . . . . . . . . . . . . . . . . .417 18.8.4 spi baud rate generation. . . . . . . . . . . . . . . . . . . . . . . . .420 18.8.5 slave-select output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .420 18.8.6 bidirectional mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .421 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . advance information mmc2114 MMC2113 mmc2112 ? rev. 1.0 398 serial peripheral interface module (spi) motorola serial peripheral interface module (spi) 18.8.7 error conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .422 18.8.7.1 write collision error . . . . . . . . . . . . . . . . . . . . . . . . . . . .422 18.8.7.2 mode fault error . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .422 18.8.8 low-power mode options . . . . . . . . . . . . . . . . . . . . . . . . .423 18.8.8.1 run mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .423 18.8.8.2 doze mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .423 18.8.8.3 stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .424 18.9 reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 424 18.10 interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .424 18.10.1 mode fault (modf) flag . . . . . . . . . . . . . . . . . . . . . . . . . .424 18.10.2 spi interrupt flag (spif) . . . . . . . . . . . . . . . . . . . . . . . . . .424 18.2 introduction the serial peripheral interface (spi) module allows full-duplex, synchronous, serial communication between the microcontroller unit (mcu) and peripheral devices. software can poll the spi status flags or spi operation can be interrupt driven. 18.3 features features include: master mode and slave mode wired-or mode slave-select output mode fault error flag with central processor unit (cpu) interrupt capability double-buffered operation serial clock with programmable polarity and phase control of spi operation during doze mode reduced drive control for lower power consumption f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . serial peripheral interface module (spi) modes of operation mmc2114 MMC2113 mmc2112 ? rev. 1.0 advance information motorola serial peripheral interface module (spi) 399 18.4 modes of operation the spi functions in these three modes: 1. run mode ? run mode is the normal mode of operation. 2. doze mode ? doze mode is a configurable low-power mode. 3. stop mode ? the spi is inactive in stop mode. 18.5 block diagram figure 18-1. spi block diagram mstr swom ssoe lsbfe spisdoz spc0 spif wcol modf 256 128 64 32 16 8 4 2 divider baud rate select baud rate generator shift register shift spiport miso mosi sck ss control clock control pin control spi control spr[2:0] sppr[6:4] mstr cpol cpha mstr spi data register spie spe rdpsp pupsp ddrsp[7:0] ip interface spi interrupt request spi clock msb lsb f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . advance information mmc2114 MMC2113 mmc2112 ? rev. 1.0 400 serial peripheral interface module (spi) motorola serial peripheral interface module (spi) 18.6 signal description an overview of the signals is provided in table 18-1 . 18.6.1 miso (master in/slave out) miso is one of the two spi data pins. in master mode, miso is the data input. in slave mode, miso is the data output and is three-stated until a master drives the ss input pin low. in bidirectional mode, a slave miso pin is the siso pin (slave in/slave out). in a multiple-master system, all miso pins are tied together. 18.6.2 mosi (master out/slave in) mosi is one of the two spi data pins. in master mode, mosi is the data output. in slave mode, mosi is the data input. in bidirectional mode, a master mosi pin is the momi pin (master out/master in). in a multiple-master system, all mosi pins are tied together. table 18-1. signal properties name port function (1) 1. the spi ports (miso, mosi, sck, and ss ) are general-purpose i/o ports when the spi is disabled (spe = 0). reset state miso spiport0 master data in/slave data out 0 mosi spiport1 master data out/slave data in 0 sck spiport2 serial clock 0 ss spiport3 slave select 0 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . serial peripheral interface module (spi) memory map and registers mmc2114 MMC2113 mmc2112 ? rev. 1.0 advance information motorola serial peripheral interface module (spi) 401 18.6.3 sck (serial clock) the sck pin is the serial clock pin for synchronizing transmissions between master and slave devices. in master mode, sck is an output. in slave mode, sck is an input. in a multiple-master system, all sck pins are tied together. 18.6.4 ss (slave select) in master mode, the ss pin can be: a mode-fault input a general-purpose input a general-purpose output a slave-select output in slave mode, the ss pin is always a slave-select input. 18.7 memory map and registers table 18-2 shows the spi memory map. note: reading reserved addresses (0x00cb_004 and 0x00cb_0009 through 0x00cb_000b) and unimplemented addresses (0x00cb_000c through 0x00cb_000f) returns 0s. writing to unimplemented addresses has no effect. accessing unimplemented addresses does not generate an error response. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . advance information mmc2114 MMC2113 mmc2112 ? rev. 1.0 402 serial peripheral interface module (spi) motorola serial peripheral interface module (spi) 18.7.1 spi control register 1 read: anytime write: anytime spie ? spi interrupt enable bit the spie bit enables the spif and modf flags to generate interrupt requests. reset clears spie. 1 = spif and modf interrupt requests enabled 0 = spif and modf interrupt requests disabled table 18-2. spi memory map address bits 7 ? 0 access (1) 1. s/u = cpu supervisor or user mode access. user mode accesses to supervisor only ad- dresses have no effect and result in a cycle termination transfer error. 0x00cb_0000 spi control register 1 (spicr1) s/u 0x00cb_0001 spi control register 2 (spicr2) s/u 0x00cb_0002 spi baud rate register (spibr) s/u 0x00cb_0003 spi status register (spisr) s/u 0x00cb_0005 spi data register (spidr) s/u 0x00cb_0006 spi pullup and reduced drive register (spipurd) s/u 0x00cb_0007 spi port data register (spiport) s/u 0x00cb_0008 spi port data direction register (spiddr) s/u address: 0x00cb_0000 %lw%lw read: spie spe swom mstr cpol cpha ssoe lsbfe write: reset:00000100 figure 18-2. spi control register 1 (spicr1) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . serial peripheral interface module (spi) memory map and registers mmc2114 MMC2113 mmc2112 ? rev. 1.0 advance information motorola serial peripheral interface module (spi) 403 spe ? spi system enable bit the spe bit enables the spi and dedicates spi port pins [3:0] to spi functions. when spe is clear, the spi system is initialized but in a low-power disabled state. reset clears spe. 1 = spi enabled 0 = spi disabled swom ? spi wired-or mode bit the swom bit configures the output buffers of spi port pins [3:0] as open-drain outputs. swom controls spi port pins [3:0] whether they are spi outputs or general-purpose outputs. reset clears swom. 1 = output buffers of spi port pins [3:0] open-drain 0 = output buffers of spi port pins [3:0] cmos drive mstr ? master bit the mstr bit selects spi master mode or spi slave mode operation. reset clears mstr. 1 = master mode 0 = slave mode cpol ? clock polarity bit the cpol bit selects an inverted or non-inverted spi clock. to transmit data between spi modules, the spi modules must have identical cpol values. reset clears cpol. 1 = active-low clock; sck idles high 0 = active-high clock; sck idles low cpha ? clock phase bit the cpha bit delays the first edge of the sck clock. reset sets cpha. 1 = first sck edge at start of transmission 0 = first sck edge 1/2 cycle after start of transmission f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . advance information mmc2114 MMC2113 mmc2112 ? rev. 1.0 404 serial peripheral interface module (spi) motorola serial peripheral interface module (spi) ssoe ? slave select output enable bit the ssoe bit and the ddrsp3 bit configure the ss pin as a general-purpose input or a slave-select output. reset clears ssoe. note: setting the ssoe bit disables the mode fault detect function. lsbfe ? lsb-first enable bit the lsbfe enables data to be transmitted lsb first. reset clears lsbfe. 1 = data transmitted lsb first. 0 = data transmitted msb first note: in spidr, the msb is always bit 7 regardless of the lsbfe bit. table 18-3. ss pin i/o configurations ddrsp3 ssoe master mode slave mode 0 0 mode-fault input slave-select input 0 1 general-purpose input slave-select input 1 0 general-purpose output slave-select input 1 1 slave-select output slave-select input f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . serial peripheral interface module (spi) memory map and registers mmc2114 MMC2113 mmc2112 ? rev. 1.0 advance information motorola serial peripheral interface module (spi) 405 18.7.2 spi control register 2 read: anytime write: anytime; writing to unimplemented bits has no effect spisdoz ? spi stop in doze bit the spidoz bit stops the spi clocks when the cpu is in doze mode. reset clears spisdoz. 1 = spi inactive in doze mode 0 = spi active in doze mode spc0 ? serial pin control bit 0 the spc0 bit enables the bidirectional pin configurations shown in table 18-4 . reset clears spc0. address: 0x00cb_0001 bit 7654321bit 0 read: 000000 spisdoz spc0 write: reset:00000100 = writes have no effect and the access terminates without a transfer error exception. figure 18-3. spi control register 2 (spicr2) table 18-4. bidirectional pin configurations pin mode spc0 mstr miso pin (1) mosi pin (2) sck pin (3) ss pin (4) a normal 0 0 slave data output slave data input sck input slave-select input b 1 master data input master data output sck output modf/gp input (ddrsp3 = 0) or gp output (ddrsp3 = 1) c bidirectional 1 0 slave data i/o gp (5) i/o sck input slave-select input d 1 gp i/o master data i/o sck output modf/gp input (ddrsp3 = 0) or gp output (ddrsp3 = 1) 1. slave output is enabled if spiddr bit 0 = 1, ss = 0, and mstr = 0 (a, c). 2. master output is enabled if spiddr bit 1 = 1 and mstr = 1 (b, d). 3. sck output is enabled if spiddr bit 2 = 1 and mstr = 1 (b, d). 4. ss output is enabled if spiddr bit 3 = 1, spicr1 bit 1 (ssoe) = 1, and mstr = 1 (b, d). modf input is enabled if spi ddr bit 3 = 0 and ssoe = 0. gp input is enabled if spi ddr bit 3 = 0 and ssoe = 1. 5. gp = general-purpose f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . advance information mmc2114 MMC2113 mmc2112 ? rev. 1.0 406 serial peripheral interface module (spi) motorola serial peripheral interface module (spi) 18.7.3 spi baud rate register read: anytime write: anytime; writing to unimplemented bits has no effect sppr[6:4] ? spi baud rate preselection bits the sppr[6:4] and spr[2:0] bits select the spi clock divisor as shown in table 18-5 . reset clears sppr[6:4] and spr[2:0], selecting an spi clock divisor of 2. spr[2:0] ? spi baud rate bits the sppr[6:4] and spr[2:0] bits select the spi clock divisor as shown in table 18-5 . reset clears sppr[6:4] and spr[2:0], selecting an spi clock divisor of 2. note: writing to spibr during a transmission may cause spurious results. address: 0x00cb_0002 bit 7654321bit 0 read: 0 sppr6 sppr5 sppr4 0 spr2 spr1 spr0 write: reset:00000000 = writes have no effect and the access terminates without a transfer error exception. figure 18-4. spi baud rate register (spibr) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . serial peripheral interface module (spi) memory map and registers mmc2114 MMC2113 mmc2112 ? rev. 1.0 advance information motorola serial peripheral interface module (spi) 407 table 18-5. spi baud rate selection (33-mhz module clock) sppr[6:4] spr[2:0] spi clock divisor baud rate sppr[6:4] spr[2:0] spi clock divisor baud rate 000 000 2 16.5 mhz 100 000 10 3.3 mhz 000 001 4 8.25 mhz 100 001 20 1.65 mhz 000 010 8 4.125 mhz 100 010 40 825 mhz 000 011 16 2.06 mhz 100 011 80 412.5 khz 000 100 32 1.03 mhz 100 100 160 206.25 khz 000 101 64 515.62 khz 100 101 320 103.13 khz 000 110 128 257.81 khz 100 110 640 51.56 khz 000 111 256 128.9 khz 100 111 1280 25.78 khz 001 000 4 8.25 mhz 101 000 12 2.75 mhz 001 001 8 4.12 mhz 101 001 24 1.375 mhz 001 010 16 2.06 mhz 101 010 48 687.5 khz 001 011 32 1.03 mhz 101 011 96 343.75 khz 001 100 64 515.62 khz 101 100 192 171.88 khz 001 101 128 257.81 khz 101 101 384 85.94 khz 001 110 256 128.9 khz 101 110 768 42.97 khz 001 111 512 64.45 khz 101 111 1536 21.48 khz 010 000 6 5.5 mhz 110 000 14 2.36 mhz 010 001 12 2.75 mhz 110 001 28 1.18 mhz 010 010 24 1.375 mhz 110 010 56 589.29 khz 010 011 48 687.5 khz 110 011 112 296.64 khz 010 100 96 343.75 khz 110 100 224 147.32 khz 010 101 192 171.88 khz 110 101 448 73.66 khz 010 110 384 85.94 khz 110 110 896 36.83 khz 010 111 768 42.97 khz 110 111 1792 18.42 khz 011 000 8 4.13 mhz 111 000 16 2.06 mhz 011 001 16 2.06 mhz 111 001 32 1.03 mhz 011 010 32 1.03 mhz 111 010 64 515.63 khz 011 011 64 515.63 khz 111 011 128 257.81 khz 011 100 128 257.81 khz 111 100 256 128.91 khz 011 101 256 128.91 khz 111 101 512 64.45 khz 011 110 512 64.45 khz 111 110 1024 32.23 khz 011 111 1024 32.23 khz 111 111 2048 16.11 khz f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . advance information mmc2114 MMC2113 mmc2112 ? rev. 1.0 408 serial peripheral interface module (spi) motorola serial peripheral interface module (spi) 18.7.4 spi status register read: anytime write: has no meaning or effect spif ? spi interrupt flag the spif flag is set after the eighth sck cycle in a transmission when received data transfers from the shift register to spidr. if the spie bit is also set, spif generates an interrupt request. once spif is set, no new data can be transferred into spidr until spif is cleared. clear spif by reading spisr with spif set and then accessing spidr. reset clears spif. 1 = new data available in spidr 0 = no new data available in spidr wcol ? write collision flag the wcol flag is set when software writes to spidr during a transmission. clear wcol by reading spisr with wcol set and then accessing spidr. reset clears wcol. 1 = write collision 0 = no write collision modf ? mode fault flag the modf flag is set when the ss pin of a master spi is driven low and the ss pin is configured as a mode-fault input. if the spie bit is also set, modf generates an interrupt request. a mode fault clears the spe, mstr, and ddrsp[2:0] bits. clear modf by reading spisr with modf set and then writing to spicr1. reset clears modf. 1 = mode fault 0 = no mode fault address: 0x00cb_0003 bit 7654321bit 0 read: spif wcol 0 modf 0000 write: reset:00000000 = writes have no effect and the access terminates without a transfer error exception. figure 18-5. spi status register (spisr) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . serial peripheral interface module (spi) memory map and registers mmc2114 MMC2113 mmc2112 ? rev. 1.0 advance information motorola serial peripheral interface module (spi) 409 18.7.5 spi data register read: anytime; normally read only after spif is set write: anytime; see wcol spidr is both the input and output register for spi data. writing to spidr while a transmission is in progress sets the wcol flag and disables the attempted write. read spidr after the spif flag is set and before the end of the next transmission. if the spif flag is not serviced before a new byte enters the shift register, the new byte and any successive bytes are lost. the byte already in the spidr remains there until spif is serviced. address: 0x00cb_0005 bit 7654321bit 0 read: bit 7654321bit 0 write: reset:00000000 figure 18-6. spi data register (spidr) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . advance information mmc2114 MMC2113 mmc2112 ? rev. 1.0 410 serial peripheral interface module (spi) motorola serial peripheral interface module (spi) 18.7.6 spi pullup and reduced drive register read: anytime write: anytime; writing to unimplemented bits has no effect rsvd5 and rsvd1 ? reserved writing to these read/write bits updates their values but has no effect on functionality. rdpsp ? spi port reduced drive control bit 1 = reduced drive capability on spiport bits [7:4] 0 = full drive enabled on spiport bits [7:4] pupsp ? spi port pullup enable bit 1 = pullup devices enabled for spiport bits [3:0] 0 = pullup devices disabled for spiport bits [3:0] address: 0x00cb_0006 bit 7654321bit 0 read: 0 0 rsvd5 rdpsp 00 rsvd1 pupsp write: reset:00000000 = writes have no effect and the access terminates without a transfer error exception. figure 18-7. spi pullup and reduced drive register (spipurd) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . serial peripheral interface module (spi) memory map and registers mmc2114 MMC2113 mmc2112 ? rev. 1.0 advance information motorola serial peripheral interface module (spi) 411 18.7.7 spi port data register read: anytime write: anytime rsvd[7:4] ? reserved writing to these read/write bits updates their values but has no effect on functionality. portsp[3:0] ? spi port data bits data written to spiport drives pins only when they are configured as general-purpose outputs. reading an input (ddrsp bit clear) returns the pin level; reading an output (ddrsp bit set) returns the pin driver input level. writing to any of the portsp[3:0] pins does not change the pin state when the pin is configured for spi output. spiport i/o function depends upon the state of the spe bit in spicr1 and the state the ddrsp bits in spiddr. address: 0x00cb_0007 bit 7654321bit 0 read: rsvd7 rsvd6 rsvd5 rsvd4 portsp3 portsp2 portsp1 portsp0 write: reset:000000 0 0 pin function: ss sck mosi/ momi miso/ siso figure 18-8. spi port data register (spiport) table 18-6. spi port summary pullup enable control reduced drive control wired-or mode control register bit reset state register bit reset state register bit reset state spipurd pupsp 0 spipurd rdpsp[1:0] full drive spicr1 swom normal f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . advance information mmc2114 MMC2113 mmc2112 ? rev. 1.0 412 serial peripheral interface module (spi) motorola serial peripheral interface module (spi) 18.7.8 spi port data direction register read: anytime write: anytime rsvd[7:4] ? reserved writing to these read/write bits updates their values but has no effect on functionality. ddrsp[3:0] ? data direction bits the ddrsp[3:0] bits control the data direction of spiport pins. reset clears ddrsp[3:0]. 1 = corresponding pin configured as output 0 = corresponding pin configured as input in slave mode, ddrsp3 has no meaning or effect. in master mode, the ddrsp3 and the ssoe bits determine whether spi port pin 3 is a mode-fault input, a general-purpose input, a general-purpose output, or a slave-select output. note: when the spi is enabled (spe = 1), the miso, mosi, and sck pins: are inputs if their spi functions are input functions regardless of the state of their ddrsp bits. are outputs if their spi functions are output functions only if their ddrsp bit s are set. address: 0x00cb_0008 bit 7654321bit 0 read: rsvd7 rsvd6 rsvd5 rsvd4 ddrsp3 ddrsp2 ddrsp1 ddrsp0 write: reset:000000 0 0 pin function: ss sck mosi/ momi miso/ siso figure 18-9. spi port data direction register (spiddr) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . serial peripheral interface module (spi) functional description mmc2114 MMC2113 mmc2112 ? rev. 1.0 advance information motorola serial peripheral interface module (spi) 413 18.8 functional description the spi module allows full-duplex, synchronous, serial communication between the mcu and peripheral devices. software can poll the spi status flags or spi operation can be interrupt driven. setting the spe bit in spicr1 enables the spi and dedicates four spi port pins to spi functions: slave select (ss ) serial clock (sck) master out/slave in (mosi) master in/slave out (miso) when the spe bit is clear, the ss , sck, mosi, and miso pins are general-purpose i/o pins controlled by spiddr. the 8-bit shift register in a master spi is linked by the mosi and miso pins to the 8-bit shift register in the slave. the linked shift registers form a distributed 16-bit register. in an spi transmission, the sck clock from the master shifts the data in the 16-bit register eight bit positions, and the master and slave exchange data. data written to the master spidr register is the output data to the slave. after the exchange, data read from the master spidr is the input data from the slave. figure 18-10. full-duplex operation shift register shift register baud rate generator master spi slave spi v dd mosi mosi miso miso sck sck ss ss spidr spidr f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . advance information mmc2114 MMC2113 mmc2112 ? rev. 1.0 414 serial peripheral interface module (spi) motorola serial peripheral interface module (spi) 18.8.1 master mode setting the mstr bit in spicr1 puts the spi in master mode. only a master spi can initiate a transmission. writing to the master spidr begins a transmission. if the shift register is empty, the byte transfers to the shift register and begins shifting out on the mosi pin under the control of the master sck clock. the sck clock starts one-half sck cycle after writing to spidr. the spr[2:0] and sppr[6:4] bits in spibr control the baud rate generator and determine the speed of the shift register. the sck pin is the spi clock output. through the sck pin, the baud rate generator of the master controls the shift register of the slave. the mstr bit in spicr1 and the spc0 bit in spicr2 control the function of the data pins, mosi and miso. the ss pin is normally an input that remains in the inactive high state. setting the ddrsp3 bit in spiddr configures ss as an output. the ddrsp3 bit and the ssoe bit in spicr1 can configure ss for general-purpose i/o, mode fault detection, or slave selection. see table 18-3 . the ss output goes low during each transmission and is high when the spi is in the idle state. driving the master ss input low sets the modf flag in spisr, indicating a mode fault. more than one master may be trying to drive the mosi and sck lines simultaneously. a mode fault clears the data direction bits of the miso, mosi (or momi), and sck pins to make them inputs. a mode fault also clears the spe and mstr bits in spicr1. if the spie bit is also set, the modf flag generates an interrupt request. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . serial peripheral interface module (spi) functional description mmc2114 MMC2113 mmc2112 ? rev. 1.0 advance information motorola serial peripheral interface module (spi) 415 18.8.2 slave mode clearing the mstr bit in spicr1 puts the spi in slave mode. the sck pin is the spi clock input from the master, and the ss pin is the slave-select input. for a transmission to occur, the ss pin must be driven low and remain low until the transmission is complete. the mstr bit and the spc0 bit in spicr2 control the function of the data pins, mosi and miso. the ss input also controls the miso pin. if ss is low, the msb in the shift register shifts out on the miso pin. if ss is high, the miso pin is in a high impedance state, and the slave ignores the sck input. note: when using peripherals with full-duplex capability, do not simultaneously enable two receivers that drive the same miso output line. as long as only one slave drives the master input line, it is possible for several slaves to receive the same transmission simultaneously. if the cpha bit in spicr1 is clear, odd-numbered edges on the sck input latch the data on the mosi pin. even-numbered edges shift the data into the lsb position of the spi shift register and shift the msb out to the miso pin. if the cpha bit is set, even-numbered edges on the sck input latch the data on the mosi pin. odd-numbered edges shift the data into the lsb position of the spi shift register and shift the msb out to the miso pin. the transmission is complete after the eighth shift. the received data transfers to spidr, setting the spif flag in spisr. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . advance information mmc2114 MMC2113 mmc2112 ? rev. 1.0 416 serial peripheral interface module (spi) motorola serial peripheral interface module (spi) 18.8.3 transmission formats the cpha and cpol bits in spicr1 select one of four combinations of serial clock phase and polarity. clock phase and polarity must be identical for the master spi device and the communicating slave device. 18.8.3.1 transfer format when cpha = 1 some peripherals require the first sck edge to occur before the slave msb becomes available at its miso pin. when the cpha bit is set, the master spi waits for a synchronization delay of one-half sck clock cycle. then it issues the first sck edge at the beginning of the transmission. the first edge causes the slave to transmit its msb to the miso pin of the master. the second edge and the following even-numbered edges latch the data. the third edge and the following odd-numbered edges shift the latched slave data into the master shift register and shift master data out on the master mosi pin. after the 16th and final sck edge: data that was in the master spidr register is in the slave spidr. data that was in the slave spidr register is in the master spidr. the sck clock stops and the spif flag in spisr is set, indicating that the transmission is complete. if the spie bit in spcr1 is set, spif generates an interrupt request. figure 18-11 shows the timing of a transmission with the cpha bit set. the ss pin of the master must be either high or configured as a general-purpose output not affecting the spi. when cpha = 1, the slave ss line can remain low between bytes. this format is good for systems with a single master and a single slave driving the miso data line. writing to spidr while a transmission is in progress sets the wcol flag to indicate a write collision and inhibits the write. wcol does not generate an interrupt request; the spif interrupt request comes at the end of the transfer that was in progress at the time of the error. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . serial peripheral interface module (spi) functional description mmc2114 MMC2113 mmc2112 ? rev. 1.0 advance information motorola serial peripheral interface module (spi) 417 figure 18-11. spi clock format 1 (cpha = 1) 18.8.3.2 transfer format when cpha = 0 in some peripherals, the slave msb is available at its miso pin as soon as the slave is selected. when the cpha bit is clear, the master spi delays its first sck edge for half a sck cycle after the transmission starts. the first edge and all following odd-numbered edges latch the slave data. even-numbered sck edges shift slave data into the master shift register and shift master data out on the master mosi pin. t l begin transmission end transmission sck (cpol = 0) sample input change output ss pin output sck (cpol = 1) msb first (lsbfe = 0): lsb first (lsbfe = 1): msb lsb lsb msb bit 5 bit 2 bit 6 bit 1 bit 4 bit 3 bit 3 bit 4 bit 2 bit 5 bit 1 bit 6 change output slave ss pin mosi pin miso pin master only mosi/miso t t if next transfer begins here for t t , t l , t l minimum 1/2 sck t i t l t l = minimum leading time before the first sck edge t t = minimum trailing time after the last sck edge t i = minimum idling time between transmissions (minimum ss high time) t l , t t , and t i are guaranteed for master mode and required for slave mode. legend: f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . advance information mmc2114 MMC2113 mmc2112 ? rev. 1.0 418 serial peripheral interface module (spi) motorola serial peripheral interface module (spi) after the 16th and final sck edge: data that was in the master spidr is in the slave spidr. data that was in the slave spidr is in the master spidr. the sck clock stops and the spif flag in spisr is set, indicating that the transmission is complete. if the spie bit in spcr1 is set, spif generates an interrupt request. figure 18-12 shows the timing of a transmission with the cpha bit clear. the ss pin of the master must be either high or configured as a general-purpose output not affecting the spi. when cpha = 0, the slave ss pin must be negated and reasserted between bytes. figure 18-12. spi clock format 0 (cpha = 0) t l begin transmission end transmission sck (cpol = 0) sample input change output ss pin output sck (cpol = 1) msb first (lsbfe = 0): lsb first (lsbfe = 1): msb lsb lsb msb bit 5 bit 2 bit 6 bit 1 bit 4 bit 3 bit 3 bit 4 bit 2 bit 5 bit 1 bit 6 change output slave ss pin mosi pin miso pin master only mosi/miso t t if next transfer begins here for t t , t l , t l minimum 1/2 sck t i t l t l = minimum leading time before the first sck edge t t = minimum trailing time after the last sck edge t i = minimum idling time between transmissions (minimum ss high time) t l , t t , and t i are guaranteed for master mode and required for slave mode. legend: f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . serial peripheral interface module (spi) functional description mmc2114 MMC2113 mmc2112 ? rev. 1.0 advance information motorola serial peripheral interface module (spi) 419 note: clock skew between the master and slave can cause data to be lost when: cpha = 0, and, the baud rate is the spi clock divided by two, and the master sck frequency is half the slave spi clock frequency, and software writes to the slave spidr just before the synchronized ss signal goes low. the synchronized ss signal is synchronized to the spi clock. figure 18-13 shows an example with the synchronized ss signal almost a full spi clock cycle late. while the synchronized ss of the slave is high, writing is allowed even though the ss pin is already low. the write can change the miso pin while the master is sampling the miso line. the first bit of the transfer may not be stable when the master samples it, so the byte sent to the master may be corrupted. figure 18-13. transmission error due to master/slave clock skew sck (cpol = 0) sample i change o change o ss pin (i) spi clock ss synchronized miso pin spidr write to spi clock mosi/miso mosi pin miso pin sck (cpol = 1) this cycle f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . advance information mmc2114 MMC2113 mmc2112 ? rev. 1.0 420 serial peripheral interface module (spi) motorola serial peripheral interface module (spi) also, if the slave generates a late write, its state machine may not have time to reset, causing it to incorrectly receive a byte from the master. this error is most likely when the sck frequency is half the slave spi clock frequency. at other baud rates, the sck skew is no more than one spi clock, and there is more time between the synchronized ss signal and the first sck edge. for example, with a sck frequency one-fourth the slave spi clock frequency, there are two spi clocks between the fall of ss and the sck edge. as long as another late spidr write does not occur, the following bytes to and from the slave are correctly transmitted. 18.8.4 spi baud rate generation the baud rate generator divides the spi clock to produce the spi baud clock. the sppr[6:4] and spr[2:0] bits in spibr select the spi clock divisor: spi clock divisor = (sppr + 1) 2(spr+1) where: sppr = the value written to bits sppr[6:4] spr = the value written to bits spr[2:0] the baud rate generator is active only when the spi is in master mode and transmitting. otherwise, the divider is inactive to reduce i dd current. 18.8.5 slave-select output the slave-select output feature automatically drives the ss pin low during transmission to select external devices and drives it high during idle to deselect external devices. when ss output is selected, the ss output pin is connected to the ss input pin of the external device. in master mode only, setting the ssoe bit in spicr1 and the ddrsp[3] bit in spiddr configures the ss pin as a slave-select output. setting the ssoe bit disables the mode fault feature. note: be careful when using the slave-select output feature in a multimaster system. the mode fault feature is not available for detecting system errors between masters. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . serial peripheral interface module (spi) functional description mmc2114 MMC2113 mmc2112 ? rev. 1.0 advance information motorola serial peripheral interface module (spi) 421 18.8.6 bidirectional mode setting the spc0 bit in spicr1 selects bidirectional mode (see table 18-7 ). the spi uses only one data pin for the interface with external device(s). the mstr bit determines which pin to use. in master mode, the mosi pin is the master out/master in pin, momi. in slave mode, the miso pin is the slave out/slave in pin, siso. the miso pin in master mode and mosi pin in slave mode are general-purpose i/o pins. the direction of each data i/o pin depends on its data direction register bit. a pin configured as an output is the output from the shift register. a pin configured as an input is the input to the shift register, and data coming out of the shift register is discarded. the sck pin is an output in master mode and an input in slave mode. the ss pin can be an input or an output in master mode, and it is always an input in slave mode. in bidirectional mode, a mode fault does not clear ddrsp0, the data direction bit for the siso pin. table 18-7. normal mode and bidirectional mode spe = 1 master mode, mstr = 1 slave mode, mstr = 0 normal mode spc0 = 0 swom enables open drain output . swom enables open drain output . bidirectional mode spc0 = 1 swom enables open drain output. spi port pin 0 is general-purpose i/o. swom enables open drain output. spi port pin 1 is general-purpose i/o. spi mosi miso ddrsp1 serial out serial in spi mosi miso serial in serial out ddrsp0 spi momi spi port ddrsp1 serial out serial in pin 0 spi siso ddrsp0 serial in serial out spi port pin 1 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . advance information mmc2114 MMC2113 mmc2112 ? rev. 1.0 422 serial peripheral interface module (spi) motorola serial peripheral interface module (spi) 18.8.7 error conditions the spi has two error conditions: write collision error mode fault error 18.8.7.1 write collision error the wcol flag in spisr indicates that a serial transfer was in progress when the mcu tried to write new data to spidr. valid write times are listed below (see figure 18-11 and figure 18-12 for definitions of t t and t i ): in master mode, a valid write is within t i (when ss is high). in slave phase 0, a valid write within t i (when ss is high). in slave phase 1, a valid write is within t t or t i (after the last sck edge and before ss goes low), excluding the first two spi clocks after the last sck edge (the beginning of t t is an illegal write). a write during any other time causes a wcol error. the write is disabled to avoid writing over the data being transmitted. wcol does not generate an interrupt request because the wcol flag can be read upon completion of the transmission that was in progress at the time of the error. 18.8.7.2 mode fault error if the ss input of a master spi goes low, it indicates a system error in which more than one master may be trying to drive the mosi and sck lines simultaneously. this condition is not permitted in normal operation; it sets the modf flag in spisr. if the spie bit in spicr1 is also set, modf generates an interrupt request. configuring the ss pin as a general-purpose output or a slave-select output disables the mode fault function. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . serial peripheral interface module (spi) functional description mmc2114 MMC2113 mmc2112 ? rev. 1.0 advance information motorola serial peripheral interface module (spi) 423 a mode fault clears the spe and mstr bits and the ddrsp bits of the sck, miso, and mosi (or momi) pins. this forces those pins to be high-impedance inputs to avoid any conflict with another output driver. if the mode fault error occurs in bidirectional mode, the ddrsp bit of the siso pin is not affected, since it is a general-purpose i/o pin. 18.8.8 low-power mode options this subsection describes the low-power mode options. 18.8.8.1 run mode clearing the spe bit in spicr1 puts the spi in a disabled, low-power state. spi registers are accessible, but spi clocks are disabled. 18.8.8.2 doze mode spi operation in doze mode depends on the state of the spisdoz bit in spicr2. if spisdoz is clear, the spi operates normally in doze mode. if spisdoz is set, the spi clock stops, and the spi enters a low-power state in doze mode. ? any master transmission in progress stops at doze mode entry and resumes at doze mode exit. ? any slave transmission in progress continues if a master continues to drive the slave sck pin. the slave stays synchronized to the master sck clock. note: although the slave shift register can receive mosi data, it cannot transfer data to spidr or set the spif flag in doze or stop mode. if the slave enters doze mode in an idle state and exits doze mode in an idle state, spif remains clear and no transfer to spidr occurs. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . advance information mmc2114 MMC2113 mmc2112 ? rev. 1.0 424 serial peripheral interface module (spi) motorola serial peripheral interface module (spi) 18.8.8.3 stop mode spi operation in stop mode is the same as in doze mode with the spisdoz bit set. 18.9 reset reset initializes the spi registers to a known startup state as described in 18.7 memory map and registers . a transmission from a slave after reset and before writing to the spidr register is either indeterminate or the byte last received from the master before the reset. reading the spidr after reset returns 0s. 18.10 interrupts 18.10.1 mode fault (modf) flag modf is set when the ss pin of a master spi is driven low and the ss pin is configured as a mode-fault input. if the spie bit is also set, modf generates an interrupt request. a mode fault clears the spe, mstr, and ddrsp[2:0] bits. clear modf by reading spisr with modf set and then writing to spicr1. reset clears modf. 18.10.2 spi interrupt flag (spif) spif is set after the eighth sck cycle in a transmission when received data transfers from the shift register to spidr. if the spie bit is also set, spif generates an interrupt request. once spif is set, no new data can be transferred into spidr until spif is cleared. clear spif by reading spisr with spif set and then accessing spidr. reset clears spif. table 18-8. spi interrupt request sources interrupt request flag enable bit mode fault modf spie transmission complete spif f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . mmc2114 MMC2113 mmc2112 ? rev. 1.0 advance information motorola queued analog-to-digital converter (qadc) 425 advance information ? mmc2114, MMC2113, and mmc2112 section 19. queued analog-to-digital converter (qadc) 19.1 contents 19.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .427 19.3 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .428 19.4 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .429 19.5 modes of operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .430 19.5.1 debug mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .430 19.5.2 stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .431 19.6 signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .431 19.6.1 port qa pin functions . . . . . . . . . . . . . . . . . . . . . . . . . . . .432 19.6.1.1 port qa analog input pins . . . . . . . . . . . . . . . . . . . . . . .432 19.6.1.2 port qa digital input/output pins . . . . . . . . . . . . . . . . .433 19.6.2 port qb pin functions . . . . . . . . . . . . . . . . . . . . . . . . . . . .433 19.6.2.1 port qb analog input pins . . . . . . . . . . . . . . . . . . . . . . .433 19.6.2.2 port qb digital input pins . . . . . . . . . . . . . . . . . . . . . . .433 19.6.3 external trigger input pins. . . . . . . . . . . . . . . . . . . . . . . . .434 19.6.4 multiplexed address output pins . . . . . . . . . . . . . . . . . . . .434 19.6.5 multiplexed analog input pins . . . . . . . . . . . . . . . . . . . . . .435 19.6.6 voltage reference pins . . . . . . . . . . . . . . . . . . . . . . . . . . .435 19.6.7 dedicated analog supply pins . . . . . . . . . . . . . . . . . . . . . .435 19.6.8 dedicated digital i/o port supply pin. . . . . . . . . . . . . . . . . 435 19.7 memory map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .436 19.8 register descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 437 19.8.1 qadc module configuration register (qadcmcr) . . . . .437 19.8.2 qadc test register (qadctest) . . . . . . . . . . . . . . . . . .438 19.8.3 port data registers (portqa and portqb) . . . . . . . . .438 19.8.4 port qa and qb data direction register (ddrqa and ddrqb) . . . . . . . . . . . . . . . . . . . . . . . . . 440 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . advance information mmc2114 MMC2113 mmc2112 ? rev. 1.0 426 queued analog-to-digital converter (qadc) motorola queued analog-to-digital converter (qadc) 19.8.5 control registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .442 19.8.5.1 qadc control register 0 (qacr0) . . . . . . . . . . . . . . . . 442 19.8.5.2 qadc control register 1 (qacr1) . . . . . . . . . . . . . . . . 445 19.8.5.3 qadc control register 2 (qacr2) . . . . . . . . . . . . . . . . 448 19.8.6 status registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .453 19.8.6.1 qadc status register 0 (qasr0). . . . . . . . . . . . . . . . .453 19.8.6.2 qadc status register 1 (qasr1). . . . . . . . . . . . . . . . .462 19.8.7 conversion command word table (ccw) . . . . . . . . . . . .463 19.8.8 result registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .468 19.8.8.1 right-justified unsigned result register (rjurr) . . . .468 19.8.8.2 left-justified signed result register (ljsrr) . . . . . . .469 19.8.8.3 left-justified unsigned result register (ljurr) . . . . . 470 19.9 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .470 19.9.1 result coherency. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .470 19.9.2 external multiplexing . . . . . . . . . . . . . . . . . . . . . . . . . . . . .471 19.9.2.1 external multiplexing operation . . . . . . . . . . . . . . . . . . .471 19.9.2.2 module version options. . . . . . . . . . . . . . . . . . . . . . . . .473 19.9.3 analog subsystem . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .474 19.9.3.1 analog-to-digital converter operation . . . . . . . . . . . . . .474 19.9.3.2 conversion cycle times . . . . . . . . . . . . . . . . . . . . . . . .475 19.9.3.3 channel decode and multiplexer . . . . . . . . . . . . . . . . . .476 19.9.3.4 sample buffer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .476 19.9.3.5 digital-to-analog converter (dac) array . . . . . . . . . . . .476 19.9.3.6 comparator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .477 19.9.3.7 bias . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .477 19.9.3.8 successive approximation register. . . . . . . . . . . . . . . . 477 19.9.3.9 state machine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .477 19.10 digital control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .478 19.10.1 queue priority timing examples . . . . . . . . . . . . . . . . . . . .478 19.10.1.1 queue priority . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .478 19.10.1.2 queue priority schemes . . . . . . . . . . . . . . . . . . . . . . . .481 19.10.2 boundary conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . .492 19.10.3 scan modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .493 19.10.4 disabled mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .494 19.10.5 reserved mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .494 19.10.6 single-scan modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .494 19.10.6.1 software-initiated single-scan mode. . . . . . . . . . . . . . .495 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . queued analog-to-digital converter (qadc) introduction mmc2114 MMC2113 mmc2112 ? rev. 1.0 advance information motorola queued analog-to-digital converter (qadc) 427 19.10.6.2 externally triggered single-scan mode. . . . . . . . . . . . .496 19.10.6.3 externally gated single-scan mode . . . . . . . . . . . . . . .497 19.10.6.4 interval timer single-scan mode. . . . . . . . . . . . . . . . . .497 19.10.7 continuous-scan modes . . . . . . . . . . . . . . . . . . . . . . . . . .499 19.10.7.1 software-initiated continuous-scan mode. . . . . . . . . . .500 19.10.7.2 externally triggered continuous-scan mode . . . . . . . .501 19.10.7.3 externally gated continuous-scan mode . . . . . . . . . . .501 19.10.7.4 periodic timer continuous-scan mode . . . . . . . . . . . . .502 19.10.8 qadc clock (qclk) generation . . . . . . . . . . . . . . . . . . . .503 19.10.9 periodic/interval timer . . . . . . . . . . . . . . . . . . . . . . . . . . . .504 19.10.10 conversion command word table . . . . . . . . . . . . . . . . . .505 19.10.11 result word table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .509 19.11 pin connection considerations . . . . . . . . . . . . . . . . . . . . . . .509 19.11.1 analog reference pins. . . . . . . . . . . . . . . . . . . . . . . . . . . .509 19.11.2 analog power pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .510 19.11.3 conversion timing schemes . . . . . . . . . . . . . . . . . . . . . . .512 19.11.4 analog supply filtering and grounding . . . . . . . . . . . . . . .515 19.11.5 accommodating positive/negative stress conditions . . . .517 19.11.6 analog input considerations . . . . . . . . . . . . . . . . . . . . . . .519 19.11.7 analog input pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .521 19.11.7.1 settling time for the external circuit . . . . . . . . . . . . . . .522 19.11.7.2 error resulting from leakage . . . . . . . . . . . . . . . . . . . .523 19.12 interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .524 19.12.1 interrupt operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .524 19.12.2 interrupt sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .525 19.2 introduction the queued analog-to-digital converter (qadc) is a 10-bit, unipolar, successive approximation converter. up to eight analog input channels can be supported using internal multiplexing. a maximum of 18 input channels can be supported in the expanded, externally multiplexed mode. the qadc consists of an analog front-end and a digital control subsystem, which includes an ipbus interface block. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . advance information mmc2114 MMC2113 mmc2112 ? rev. 1.0 428 queued analog-to-digital converter (qadc) motorola queued analog-to-digital converter (qadc) the analog section includes input pins, an analog multiplexer, and sample and hold analog circuits. the analog conversion is performed by the digital-to-analog converter (dac) resistor-capacitor (rc) array and a high-gain comparator. the digital control section contains queue control logic to sequence the conversion process and interrupt generation logic. also included are the periodic/interval timer, control and status registers, the conversion command word (ccw) table, random-access memory (ram), and the result table ram. the bus interface unit (biu) provides access to registers that configure the qadc, control the analog-to-digital converter and queue mechanism, and present formatted conversion results. 19.3 features features of the qadc module include: internal sample and hold up to eight analog input channels using internal multiplexing up to four external analog multiplexers directly supported up to 18 total input channels with internal and external multiplexing programmable input sample time for various source impedances two conversion command word (ccw) queues with a total of 64 entries for setting conversion parameters of each a/d conversion subqueues possible using pause mechanism queue complete and pause interrupts available on both queues queue pointers indicating current location for each queue automated queue modes initiated by: ? external edge trigger and gated trigger ? periodic/interval timer, within qadc module (queues 1 and 2) ? software command f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . queued analog-to-digital converter (qadc) block diagram mmc2114 MMC2113 mmc2112 ? rev. 1.0 advance information motorola queued analog-to-digital converter (qadc) 429 single scan or continuous scan of queues 64 result registers output data readable in three formats: ? right-justified unsigned ? left-justified signed ? left-justified unsigned unused analog channels can be used as discrete input/output pins. 19.4 block diagram figure 19-1. qadc block diagram digital external external reference analog power 64-entry queue control of 10-bit conversion command words ipbus interface 10-bit analog-to-digital converter analog input mux and digital pin functions 64-entry table of 10-bit 10-bit to 16-bit result alignment (18 with external muxing) mux address triggers inputs inputs (ccws) results 8 analog channels f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . advance information mmc2114 MMC2113 mmc2112 ? rev. 1.0 430 queued analog-to-digital converter (qadc) motorola queued analog-to-digital converter (qadc) 19.5 modes of operation this subsection describes the two modes of operation in which the qadc does not perform conversions in a regular fashion: debug mode stop mode 19.5.1 debug mode the qdbg bit in the module configuration register (qadcmcr) governs behavior of the qadc when the cpu enters background debug mode. when qdbg is clear, the qadc operates normally and is unaffected by cpu background debug mode. see 19.8.1 qadc module configuration register (qadcmcr) . when qdbg is set and the cpu enters background debug mode, the qadc finishes any conversion in progress and then freezes. this is qadc debug mode. depending on when debug mode is entered, the three possible queue freeze scenarios are: when a queue is not executing, the qadc freezes immediately. when a queue is executing, the qadc completes the current conversion and then freezes. if during the execution of the current conversion, the queue operating mode for the active queue is changed, or a queue 2 abort occurs, the qadc freezes immediately. when the qadc enters debug mode while a queue is active, the current ccw location of the queue pointer is saved. debug mode: stops the analog clock holds the periodic/interval timer in reset prevents external trigger events from being captured keeps all qadc registers and ram accessible f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . queued analog-to-digital converter (qadc) signals mmc2114 MMC2113 mmc2112 ? rev. 1.0 advance information motorola queued analog-to-digital converter (qadc) 431 although the qadc saves a pointer to the next ccw in the current queue, software can force the qadc to execute a different ccw by reconfiguring the qadc. when the qadc exits debug mode, it looks at the queue operating modes, the current queue pointer, and any pending trigger events to decide which ccw to execute. 19.5.2 stop mode the qadc enters a low-power idle state whenever the qstop bit is set or the cpu enters low-power stop mode. qadc stop: disables the analog-to-digital converter, effectively turning off the analog circuit aborts the conversion sequence in progress makes the data direction register (ddrqa), port data registers (portqa and portqb), control registers (qacr2, qacr1, and qacr0) and the status registers (qasr1 and qasr0) read-only. only the module configuration register (qadcmcr) remains writable. makes the ram inaccessible, so that valid data cannot be read from ram (result word table and ccw) or written to ram (result word table and ccw) resets qacr1, qacr2, qasr0, and qasr1 holds the qadc periodic/interval timer in reset because the bias currents to the analog circuit are turned off in stop mode, the qadc requires some recovery time (t sr ) to stabilize the analog circuits. 19.6 signals the qadc uses the external pins shown in figure 19-2 . there are eight channel/port pins that can support up to 18 channels when external multiplexing is used (including internal channels). all of the channel pins f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . advance information mmc2114 MMC2113 mmc2112 ? rev. 1.0 432 queued analog-to-digital converter (qadc) motorola queued analog-to-digital converter (qadc) also have some general-purpose input or input/output functionality. in addition, there are also two analog reference pins and two analog submodule power pins. the qadc has external trigger inputs and multiplexer outputs that are shared with some of the analog input pins. 19.6.1 port qa pin functions the four port qa pins can be used as analog inputs or as a bidirectional 4-bit digital input/output port. 19.6.1.1 port qa analog input pins when used as analog inputs, the four port qa pins are referred to as an[56:55, 53:52]. due to the digital output drivers associated with port qa, the analog characteristics of port qa may be different from those of port qb. figure 19-2. qadc input and output signals an52/ma0/pqa0 an53/ma1/pqa1 an55/etrig1/pqa3 an56/etrig2/pqa4 an0/anw/pqb0 an1/anx/pqb1 an2/any/pqb2 an3/anz/pqb3 digital analog v ssi analog power and ground internal digital power port qb converter results and control analog mux and port qb analog inputs external mux inputs digital inputs port qa analog inputs external trigger inputs external mux address outputs v ddi v ssa v dda v rh v rl analog references shared with other modules digital i/o port logic port qa f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . queued analog-to-digital converter (qadc) signals mmc2114 MMC2113 mmc2112 ? rev. 1.0 advance information motorola queued analog-to-digital converter (qadc) 433 19.6.1.2 port qa digital input/output pins port qa pins are referred to as pqa[4:3, 1:0] when used as a bidirectional 4-bit digital input/output port. these four pins may be used for general-purpose digital input signals or digital output signals. port qa pins are connected to a digital input synchronizer during reads and may be used as general-purpose digital inputs when the applied voltages meet high-voltage input (v ih ) and low-voltage input (v il ) requirements. each port qa pin is configured as an input or output by programming the port data direction register (ddrqa). the digital input signal states are read from the port qa data register (portqa) when ddrqa specifies that the pins are inputs. the digital data in portqa is driven onto the port qa pins when the corresponding bits in ddrqa specify output. see 19.8.4 port qa and qb data direction register (ddrqa and ddrqb) . 19.6.2 port qb pin functions the four port qb pins can be used as analog inputs or as a 4-bit digital input-only port. 19.6.2.1 port qb analog input pins when used as analog inputs, the four port qb pins are referred to as an[3:0]. because port qb functions as analog and digital input only, the analog characteristics may be different from those of port qa. 19.6.2.2 port qb digital input pins port qb pins are referred to as pqb[3:0] when used as a 4-bit digital input/output port. in addition to functioning as analog input pins, the port qb pins are also connected to the input of a synchronizer during reads and may be used as general-purpose digital inputs when the applied voltages meet v ih and v il requirements. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . advance information mmc2114 MMC2113 mmc2112 ? rev. 1.0 434 queued analog-to-digital converter (qadc) motorola queued analog-to-digital converter (qadc) each port qb pin is configured as an input or output by programming the port data direction register (ddrqb). the digital input signal states are read from the port qb data register (portqb) when ddrqb specifies that the pins are inputs. the digital data in portqb is driven onto the port qb pins when the corresponding bits in ddrqb specify output. see 19.8.4 port qa and qb data direction register (ddrqa and ddrqb) . 19.6.3 external trigger input pins the qadc has two external trigger pins, etrig2 and etrig1. each external trigger input is associated with one of the scan queues, queue 1 or queue 2. the assignment of etrig[2:1] to a queue is made by the trg bit in qadc control register 0 (qacr0). when trg = 0, etrig1 triggers queue 1 and etrig2 triggers queue 2. when trg = 1, etrig1 triggers queue 2 and etrig2 triggers queue 1. see 19.8.5 control registers . 19.6.4 multiplexed address output pins in non-multiplexed mode, the qadc analog input pins are connected to an internal multiplexer which routes the analog signals into the internal a/d converter. in externally multiplexed mode, the qadc allows automatic channel selection through up to four external 4-to-1 multiplexer chips. the qadc provides a 2-bit multiplexed address output to the external multiplexer chips to allow selection of one of four inputs. the multiplexed address output signals, ma1 and ma0, can be used as multiplexed address output bits or as general-purpose i/o when external multiplexed mode is not being used. ma[1:0] are used as the address inputs for up to four 4-channel multiplexer chips. because the ma[1:0] pins are digital outputs in multiplexed mode, the state of their corresponding data direction bits in ddrqa is ignored. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . queued analog-to-digital converter (qadc) signals mmc2114 MMC2113 mmc2112 ? rev. 1.0 advance information motorola queued analog-to-digital converter (qadc) 435 19.6.5 multiplexed analog input pins in external multiplexed mode, four of the port qb pins are redefined to each represent four analog input channels. see table 19-1 . 19.6.6 voltage reference pins v rh and v rl are the dedicated input pins for the high and low reference voltages. separating the reference inputs from the power supply pins allows for additional external filtering, which increases reference voltage precision and stability, and subsequently contributes to a higher degree of conversion accuracy. note: v rh and v rl must be set to v dda and v ssa potential, respectively. 19.6.7 dedicated analog supply pins the v dda and v ssa pins supply power to the analog subsystems of the qadc module. dedicated power is required to isolate the sensitive analog circuitry from the normal levels of noise present on the digital power supply. 19.6.8 dedicated digital i/o port supply pin v ddh provides 5-v power to the digital i/o functions of qadc port qa and port qb. this allows those pins to tolerate 5 volts when configured as inputs and drive 5 volts when configured as outputs. table 19-1. multiplexed analog input channels multiplexed analog input channels anw even numbered channels from 0 to 6 anx odd numbered channels from 1 to 7 any even numbered channels from 16 to 22 anz odd numbered channels from 17 to 23 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . advance information mmc2114 MMC2113 mmc2112 ? rev. 1.0 436 queued analog-to-digital converter (qadc) motorola queued analog-to-digital converter (qadc) 19.7 memory map the qadc occupies 1 kbyte, or 512 half-word (16-bit) entries, of address space. ten half-word registers are control, port, and status registers, 64 half-word entries are the ccw table, and 64 half-word entries are the result table which occupies 192 half-word address locations because the result data is readable in three data alignment formats. table 19-2 is the qadc memory map. table 19-2. qadc memory map address msb lsb access (1) 0x00ca_0000 qadc module configuration register (qadcmcr) s 0x00ca_0002 qadc test register (qadctest) (2) s 0x00ca_0004 reserved (3) ? 0x00ca_0006 port qa data register (portqa) port qb data register (portqb) s/u 0x00ca_0008 port qa data direction register (ddrqa) port qb data direction register (ddrqb) s/u 0x00ca_000a qadc control register 0 (qacr0) s/u 0x00ca_000c qadc control register 1 (qacr1) s/u 0x00ca_000e qadc control register 2 (qacr2) s/u 0x00ca_0010 qadc status register 0 (qasr0) s/u 0x00ca_0012 qadc status register 1 (qasr1) s/u 0x00ca_0014 ? 0x00ca_01fe reserved (3) ? 0x00ca_0200 ? 0x00ca_027e conversion command word table (ccw) s/u 0x00ca_0280 ? 0x00ca_02fe right justified, unsigned result register (rjurr) s/u 0x00ca_0300 ? 0x00ca_037e left justified, signed result register (ljsrr) s/u 0x00ca_0380 ? 0x00ca_03fe left justified, unsigned result register (ljurr) s/u 1. s = cpu supervisor mode access only. s/u = cpu supervisor or user mode access. user mode accesses to supervisor only addresses have no effect and result in a cycle termination transfer error. 2. access results in the module generating an access termination transfer error if not in test mode. 3. read/writes have no effect and the access terminates with a transfer error exception. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . queued analog-to-digital converter (qadc) register descriptions mmc2114 MMC2113 mmc2112 ? rev. 1.0 advance information motorola queued analog-to-digital converter (qadc) 437 19.8 register descriptions this subsection describes the qadc registers. 19.8.1 qadc module configuration register (qadcmcr) qadcmcr contains bits that control qadc debug and stop modes and determines the privilege level required to access most registers. qstop ? stop enable bit 1 = force qadc to idle state. 0 = qadc operates normally. qdbg ? debug enable bit 1 = finish any conversion in progress, then freeze in debug mode 0 = qadc operates normally. supv ? supervisor/unrestricted data space bit 1 = all qadc registers are accessible in supervisor mode only; user mode accesses have no effect and result in a cycle termination error. 0 = only qadcmcr and qadctest require supervisor mode access; access to all other qadc registers is unrestricted address: 0x00ca_0000 and 0x00ca_0001 bit 15 14 13 12 11 10 9 bit 8 read: qstop qdbg 000000 write: reset:00000000 bit 7654321bit 0 read: supv 0000000 write: reset:10000000 = writes have no effect and the access terminates without a transfer error exception. figure 19-3. qadc module configuration register (qadcmcr) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . advance information mmc2114 MMC2113 mmc2112 ? rev. 1.0 438 queued analog-to-digital converter (qadc) motorola queued analog-to-digital converter (qadc) 19.8.2 qadc test register (qadctest) qadctest is used only during factory testing of the mcu. attempts to access this register outside of factory test mode will result in access privilege violation. 19.8.3 port data registers (portqa and portqb) qadc ports qa and qb are accessed through two 8-bit port data registers (portqa and portqb). port qa pins are referred to as pqa[4:3, 1:0] when used as a bidirectional, 4-bit, input/output port. port qa can also be used for analog inputs (an[56:55, 53:52]), external trigger inputs (etrig[2:1]), and external multiplexer address outputs (ma[1:0]). port qb pins are referred to as pqb[3:0] when used as a 4-bit, digital input-only port. port qb can also be used for non-multiplexed (an[3:0]) and multiplexed (anz, any, anx, anw) analog inputs. portqa and portqb are not initialized by reset. address: 0x00ca_0002 and 0x00ca_0003 bit 15 14 13 12 11 10 9 bit 8 read: access results in the module generating an access termination transfer error if not in test mode. write: bit 7654321bit 0 read: access results in the module generating an access termination transfer error if not in test mode. write: figure 19-4. qadc test register (qadctest) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . queued analog-to-digital converter (qadc) register descriptions mmc2114 MMC2113 mmc2112 ? rev. 1.0 advance information motorola queued analog-to-digital converter (qadc) 439 read: anytime write: anytime except during stop mode address: 0x00ca_0006 bit 7654321bit 0 read: 0 0 0 pqa4 pqa3 0 pqa1 pqa0 write: reset: 0 0 0 p p 0 p p = writes have no effect and the access terminates without a transfer error exception. p = current pin state if ddr is input; otherwise, undefined analog channel: muxed address outputs: external trigger inputs: an56 etrig2 an55 etrig1 an53 ma1 an52 ma0 figure 19-5. qadc port qa data register (portqa) address: 0x00ca_0007 bit 7654321bit 0 read: 0 0 0 0 pqb3 pqb2 pqb1 pqb0 write: reset:00 00pppp = writes have no effect and the access terminates without a transfer error exception. p = current pin state if ddr is input; otherwise, undefined analog channel: muxed analog inputs: an3 an2 an2 any an1 anx an0 anw figure 19-6. qadc port qb data register (portqb) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . advance information mmc2114 MMC2113 mmc2112 ? rev. 1.0 440 queued analog-to-digital converter (qadc) motorola queued analog-to-digital converter (qadc) 19.8.4 port qa and qb data direction register (ddrqa and ddrqb) the port qa and qb data direction register (ddrqa and ddrqb) are associated with port qa and qb digital i/o pins. setting a bit in these registers configures the corresponding pin as an output. clearing a bit in these registers configures the corresponding pin as an input. during qadc initialization, port qa and qb pins that will be used as direct or multiplexed analog inputs must have their corresponding data direction register bits cleared. when a port qa or qb pin that is programmed as an output is selected for analog conversion, the voltage sampled is that of the output digital driver as influenced by the load. when the mux (externally multiplexed) bit is set in qacr0, the data direction register settings are ignored for the bits corresponding to pqa[1:0], the two multiplexed address (ma[1:0]) output pins. the ma[1:0] pins are forced to be digital outputs, regardless of their data direction setting, and the multiplexed address outputs are driven. the data returned during a port data register read is the value of the ma[1:0] pins, regardless of their data direction setting. similarly, when the external trigger pins are assigned to port pins and external trigger queue operating mode is selected, the data direction setting for the corresponding pins, pqa3 and/or pqa4, is ignored. the port pins are forced to be digital inputs for etrig1 and/or etrig2. the data returned during a port data register read is the value of etrig[2:1] pins, regardless of their data direction setting. note: use caution when mixing digital and analog inputs. they should be isolated as much as possible. rise and fall times should be as large as possible to minimize ac coupling effects. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . queued analog-to-digital converter (qadc) register descriptions mmc2114 MMC2113 mmc2112 ? rev. 1.0 advance information motorola queued analog-to-digital converter (qadc) 441 read: anytime write: anytime except during stop mode address: 0x00ca_0008 and 0x00ca_0009 bit 15 14 13 12 11 10 9 bit 8 read: 0 0 0 ddqa4 ddqa3 0 ddqa1 ddqa0 write: reset:00000000 bit 7654321bit 0 read: 0 0 0 0 ddqb3 ddqb2 ddqb1 ddqb0 write: reset:00000000 = writes have no effect and the access terminates without a transfer error exception. figure 19-7. qadc port qa data direction register (ddrqa) and port qb data direction register (ddrqb) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . advance information mmc2114 MMC2113 mmc2112 ? rev. 1.0 442 queued analog-to-digital converter (qadc) motorola queued analog-to-digital converter (qadc) 19.8.5 control registers this subsection describes the qadc control registers. 19.8.5.1 qadc control register 0 (qacr0) qadc control register 0 (qacr0) establishes the qadc sampling clock (qclk) with prescaler parameter fields and defines whether external multiplexing is enabled. typically, these bits are written once when the qadc is initialized and not changed thereafter. read: anytime write: anytime except during stop mode mux ? externally multiplexed mode bit the mux bit configures the qadc for operation in externally multiplexed mode, which affects the interpretation of the channel numbers and forces the ma[1:0] pins to be outputs. 1 = externally multiplexed, up to 18 possible channels 0 = internally multiplexed, up to 8 possible channels address: 0x00ca_000a and 0x00ca_000b bit 15 14 13 12 11 10 9 bit 8 read: mux 00 trg 0000 write: reset:00000000 bit 7654321bit 0 read: 0 qpr6 qpr5 qpr4 qpr3 qpr2 qpr1 qpr0 write: reset:00010011 = writes have no effect and the access terminates without a transfer error exception. figure 19-8. qadc control register 0 (qacr0) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . queued analog-to-digital converter (qadc) register descriptions mmc2114 MMC2113 mmc2112 ? rev. 1.0 advance information motorola queued analog-to-digital converter (qadc) 443 trg ? trigger assignment bit the trg bit determines the queue assignment of the etrig[2:1] pins. 1 = etrig1 triggers queue 2; etrig2 triggers queue 1. 0 = etrig1 triggers queue 1; etrig2 triggers queue 2. qpr[6:0] ? prescaler clock divider bits the read/write qpr[6:0] bits select the system clock divisor to generate the qadc clock as table 19-3 shows. the resulting qadc clock rate can be given as: where: 1 <= qpr[6:0] <= 127. if qpr[6:0] = 0, then the qpr register field value is read as a 1 and the prescaler divisor is 2. the prescaler should be selected so that the qadc clock rate is within the required fqclk range. see table 23-8. qadc conversion specifications (operating) . f qclk = f sys qpr[6:0] + 1 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . advance information mmc2114 MMC2113 mmc2112 ? rev. 1.0 444 queued analog-to-digital converter (qadc) motorola queued analog-to-digital converter (qadc) table 19-3. prescaler f sys divide-by values qpr[6:0] f sys divisor qpr[6:0] f sys divisor qpr[6:0] f sys divisor qpr[6:0] f sys divisor 0000000 2 0100000 33 1000000 65 1100000 97 0000001 2 0100001 34 1000001 66 1100001 98 0000010 3 0100010 35 1000010 67 1100010 99 0000011 4 0100011 36 1000011 68 1100011 100 0000100 5 0100100 37 1000100 69 1100100 101 0000101 6 0100101 38 1000101 70 1100101 102 0000110 7 0100110 39 1000110 71 1100110 103 0000111 8 0100111 40 1000111 72 1100111 104 0001000 9 0101000 41 1001000 73 1101000 105 0001001 10 0101001 42 1001001 74 1101001 106 0001010 11 0101010 43 1001010 75 1101010 107 0001011 12 0101011 44 1001011 76 1101011 108 0001100 13 0101100 45 1001100 77 1101100 109 0001101 14 0101101 46 1001101 78 1101101 110 0001110 15 0101110 47 1001110 79 1101110 111 0001111 16 0101111 48 1001111 80 1101111 112 0010000 17 0110000 49 1010000 81 1110000 113 0010001 18 0110001 50 1010001 82 1110001 114 0010010 19 0110010 51 1010010 83 1110010 115 0010011 20 0110011 52 1010011 84 1110011 116 0010100 21 0110100 53 1010100 85 1110100 117 0010101 22 0110101 54 1010101 86 1110101 118 0010110 23 0110110 55 1010110 87 1110110 119 0010111 24 0110111 56 1010111 88 1110111 120 0011000 25 0111000 57 1011000 89 1111000 121 0011001 26 0111001 58 1011001 90 1111001 122 0011010 27 0111010 59 1011010 91 1111010 123 0011011 28 0111011 60 1011011 92 1111011 124 0011100 29 0111100 61 1011100 93 1111100 125 0011101 30 0111101 62 1011101 94 1111101 126 0011110 31 0111110 63 1011110 95 1111110 127 0011111 32 0111111 64 1011111 96 1111111 128 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . queued analog-to-digital converter (qadc) register descriptions mmc2114 MMC2113 mmc2112 ? rev. 1.0 advance information motorola queued analog-to-digital converter (qadc) 445 19.8.5.2 qadc control register 1 (qacr1) qadc control register 1 (qacr1) is the mode control register for queue 1. this register governs queue operating mode and the use of completion and/or pause interrupts. typically, these bits are written once when the qadc is initialized and not changed thereafter. stop mode resets this register ($0000). read: anytime write: anytime except during stop mode cie1 ? queue 1 completion interrupt enable bit cie1 enables an interrupt request upon completion of queue 1. the interrupt request is initiated when the conversion is complete for the last ccw in queue 1. 1 = enable queue 1 completion interrupt. 0 = disable queue 1 completion interrupt. address: 0x00ca_000c and 0x00ca_000d bit 15 14 13 12 11 10 9 bit 8 read: cie1 pie1 0 mq112 mq111 mq110 mq19 mq18 write: sse1 reset:00000000 bit 7654321bit 0 read: 0 0 000000 write: reset:00000000 = writes have no effect and the access terminates without a transfer error exception. figure 19-9. qadc control register 1 (qacr1) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . advance information mmc2114 MMC2113 mmc2112 ? rev. 1.0 446 queued analog-to-digital converter (qadc) motorola queued analog-to-digital converter (qadc) pie1 ? queue 1 pause interrupt enable bit pie1 enables an interrupt request when queue 1 enters the pause state. the interrupt request is initiated when conversion is complete for a ccw that has the pause bit set. 1 = enable the queue 1 pause interrupt. 0 = disable the queue 1 pause interrupt. sse1 ? queue 1 single-scan enable bit sse1 enables a single-scan of queue 1 after a trigger event occurs. sse1 may be set during the same write cycle that sets the mq1 bits for one of the single-scan queue operating modes. the single-scan enable bit can be written to 1 or 0, but is always read as a 0, unless the qadc is in test mode. the qadc clears sse1 when the single-scan is complete. 1 = allow a trigger event to start queue 1 in a single-scan mode. 0 = trigger events are ignored for queue 1 single-scan modes. mq1[12:8] ? queue 1 operating mode field the mq1 field selects the operating mode for queue 1. table 19-4 shows the bits in the mq1 field which enable different queue 1 operating modes. table 19-4. queue 1 operating modes mq1[12:8] operating mode 00000 disabled mode, conversions do not occur 00001 software-triggered single-scan mode (started with sse1) 00010 external-trigger rising-edge single-scan mode 00011 external-trigger falling-edge single-scan mode 00100 interval timer single-scan mode: time = qclk period 2 7 00101 interval timer single-scan mode: time = qclk period 2 8 00110 interval timer single-scan mode: time = qclk period 2 9 00111 interval timer single-scan mode: time = qclk period 2 10 01000 interval timer single-scan mode: time = qclk period 2 11 01001 interval timer single-scan mode: time = qclk period 2 12 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . queued analog-to-digital converter (qadc) register descriptions mmc2114 MMC2113 mmc2112 ? rev. 1.0 advance information motorola queued analog-to-digital converter (qadc) 447 01010 interval timer single-scan mode: time = qclk period 2 13 01011 interval timer single-scan mode: time = qclk period 2 14 01100 interval timer single-scan mode: time = qclk period 2 15 01101 interval timer single-scan mode: time = qclk period 2 16 01110 interval timer single-scan mode: time = qclk period 2 17 01111 externally gated single-scan mode (started with sse1) 10000 reserved mode 10001 software-triggered continuous-scan mode 10010 external-trigger rising-edge continuous-scan mode 10011 external-trigger falling-edge continuous-scan mode 10100 periodic timer continuous-scan mode: time = qclk period 2 7 10101 periodic timer continuous-scan mode: time = qclk period 2 8 10110 periodic timer continuous-scan mode: time = qclk period 2 9 10111 periodic timer continuous-scan mode: time = qclk period 2 10 11000 periodic timer continuous-scan mode: time = qclk period 2 11 11001 periodic timer continuous-scan mode: time = qclk period 2 12 11010 periodic timer continuous-scan mode: time = qclk period 2 13 11011 periodic timer continuous-scan mode: time = qclk period 2 14 11100 periodic timer continuous-scan mode: time = qclk period 2 15 11101 periodic timer continuous-scan mode: time = qclk period 2 16 11110 periodic timer continuous-scan mode: time = qclk period 2 17 11111 externally gated contin uous-scan mode table 19-4. queue 1 operating modes (continued) mq1[12:8] operating mode f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . advance information mmc2114 MMC2113 mmc2112 ? rev. 1.0 448 queued analog-to-digital converter (qadc) motorola queued analog-to-digital converter (qadc) 19.8.5.3 qadc control register 2 (qacr2) qadc control register 2 (qacr2) is the mode control register for queue 2. this register governs queue operating mode and the use of completion and/or pause interrupts. typically, these bits are written once when the qadc is initialized and not changed thereafter. stop mode resets this register ($007f). read: anytime write: anytime except during stop mode cie2 ? queue 2 completion software interrupt enable bit cie2 enables an interrupt request upon completion of queue 2. the interrupt request is initiated when the conversion is complete for the last ccw in queue 2. 1 = enable queue 2 completion interrupts. 0 = disable queue 2 completion interrupts. address: 0x00ca_000e and 0x00ca_000f bit 15 14 13 12 11 10 9 bit 8 read: cie2 pie2 0 mq212 mq211 mq210 mq29 mq28 write: sse2 reset:00000000 bit 7654321bit 0 read: resume bq26 bq25 bq24 bq23 bq22 bq21 bq20 write: reset:01111111 figure 19-10. qadc control register 2 (qacr2) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . queued analog-to-digital converter (qadc) register descriptions mmc2114 MMC2113 mmc2112 ? rev. 1.0 advance information motorola queued analog-to-digital converter (qadc) 449 pie2 ? queue 2 pause software interrupt enable bit pie2 enables an interrupt request when queue 2 enters the pause state. the interrupt request is initiated when conversion is complete for a ccw that has the pause bit set. 1 = enable the queue 2 pause interrupt. 0 = disable the queue 2 pause interrupt. sse2 ? queue 2 single-scan enable bit sse2 enables a single-scan of queue 2 after a trigger event occurs. sse2 may be set during the same write cycle that sets the mq2 bits for one of the single-scan queue operating modes. the single-scan enable bit can be written to 1 or 0, but is always read as a 0, unless the qadc is in test mode. the qadc clears sse2 when the single-scan is complete. 1 = allow a trigger event to start queue 2 in a single-scan mode. 0 = trigger events are ignored for queue 2 single-scan modes. mq2[12:8] ? queue 2 operating mode field the mq2 field selects the operating mode for queue 2. table 19-5 shows the bits in the mq2 field which enable different queue 2 operating modes. table 19-5. queue 2 operating modes mq2[12:8] operating modes 00000 disabled mode, conversions do not occur 00001 software triggered single-scan mode (started with sse2) 00010 externally triggered rising edge single-scan mode 00011 externally triggered falling edge single-scan mode 00100 interval timer single-scan mode: time = qclk period x 2 7 00101 interval timer single-scan mode: time = qclk period x 2 8 00110 interval timer single-scan mode: time = qclk period x 2 9 00111 interval timer single-scan mode: time = qclk period x 2 10 01000 interval timer single-scan mode: time = qclk period x 2 11 01001 interval timer single-scan mode: time = qclk period x 2 12 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . advance information mmc2114 MMC2113 mmc2112 ? rev. 1.0 450 queued analog-to-digital converter (qadc) motorola queued analog-to-digital converter (qadc) 01010 interval timer single-scan mode: time = qclk period x 2 13 01011 interval timer single-scan mode: time = qclk period x 2 14 01100 interval timer single-scan mode: time = qclk period x 2 15 01101 interval timer single-scan mode: time = qclk period x 2 16 01110 interval timer single-scan mode: time = qclk period x 2 17 01111 r eserved m ode 10000 reserved mode 10001 software triggered continuous-scan mode 10010 externally triggered rising edge continuous-scan mode 10011 externally triggered falling edge continuous-scan mode 10100 periodic timer continuous-scan mode: time = qclk period x 2 7 10101 periodic timer continuous-scan mode: time = qclk period x 2 8 10110 periodic timer continuous-scan mode: time = qclk period x 2 9 10111 periodic timer continuous-scan mode: time = qclk period x 2 10 11000 periodic timer continuous-scan mode: time = qclk period x 2 11 11001 periodic timer continuous-scan mode: time = qclk period x 2 12 11010 periodic timer continuous-scan mode: time = qclk period x 2 13 11011 periodic timer continuous-scan mode: time = qclk period x 2 14 11100 periodic timer continuous-scan mode: time = qclk period x 2 15 11101 periodic timer continuous-scan mode: time = qclk period x 2 16 11110 periodic timer continuous-scan mode: time = qclk period x 2 17 11111 r eserved m ode table 19-5. queue 2 operating modes (continued) mq2[12:8] operating modes f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . queued analog-to-digital converter (qadc) register descriptions mmc2114 MMC2113 mmc2112 ? rev. 1.0 advance information motorola queued analog-to-digital converter (qadc) 451 resume ? queue 2 resume bit resume selects the resumption point for queue 2 after its operation is suspended due to a queue 1 trigger event. if resume is changed during the execution of queue 2, the change is not recognized until an end-of-queue condition is reached or the operating mode of queue 2 is changed. the primary reason for selecting re-execution of the entire queue or subqueue is to guarantee that all samples are taken consecutively in one scan (coherency). when subqueues are not used, queue 2 execution restarts after suspension with the first ccw in queue 2. when a pause has previously occurred in queue 2 execution, queue execution restarts after suspension with the first ccw in the current subqueue. a subqueue is considered to be a stand-alone sequence of conversions. once a pause flag has been set to report subqueue completion, that subqueue is not repeated until all ccws in queue 2 are executed. an example of using the resume bit is when the frequency of queue 1 trigger events prohibit queue 2 completion. if the rate of queue 1 execution is too high, it is best for queue 2 execution to continue with the ccw that was being converted when queue 2 was suspended. this allows queue 2 to eventually complete execution. 1 = after suspension, begin execution with the aborted ccw in queue 2. 0 = after suspension, begin execution with the first ccw of queue 2 or the current subqueue of queue 2. bq2[6:0] ? beginning of queue 2 field bq2[6:0] denotes the ccw location where queue 2 begins. this allows the length of queue 1 and queue 2 to vary. the bq2 field also serves as an end-of-queue condition for queue 1. the beginning of queue 2 is defined by programming the bq2 field in qacr2. bq2 is usually set before or at the same time as the queue operating mode for queue 2 is selected. if bq2[6:0] 64, queue 2 has no entries, the entire ccw table is dedicated to queue 1, and ccw63 is the end-of-queue 1. if bq2[6:0] is 0, the entire ccw table is dedicated to queue 2. a special case occurs when an operating mode f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . advance information mmc2114 MMC2113 mmc2112 ? rev. 1.0 452 queued analog-to-digital converter (qadc) motorola queued analog-to-digital converter (qadc) is selected for queue 1 and a trigger event occurs for queue 1 with bq2 set to 0. queue 1 execution starts momentarily, but is terminated after ccw0 is read. no conversions occur. the bq2[6:0] pointer may be changed dynamically to alternate between queue 2 scan sequences. a change in bq2 after queue 2 has begun or when queue 2 has a trigger pending does not affect queue 2 until it is started again. for example, two scan sequences could be defined as follows: the first sequence starts at ccw10, with a pause after ccw11 and an end of queue (eoq) programmed in ccw15; the second sequence starts at ccw16, with a pause after ccw17 and an eoq programmed in ccw39. with bq2[6:0] set to ccw10 and the continuous-scan mode selected, queue execution begins. when the pause is encountered in ccw11, an interrupt service routine can retarget bq2[6:0] to ccw16. when the end-of-queue is recognized in ccw15, an internal retrigger event is generated and execution restarts at ccw16. when the pause software interrupt occurs again, bq2 can be changed back to ccw10. after the end-of-queue is recognized in ccw39, an internal retrigger event is created and execution now restarts at ccw10. if bq2[6:0] is changed while queue 1 is active, the effect of bq2[6:0] as an end-of-queue indication for queue 1 is immediate. however, beware of the risk of losing the end-of-queue 1 when changing bq2[6:0]. using eoq (channel 63) to end queue 1 is recommended. note: if bq2[6:0] was assigned to the ccw that queue 1 is currently working on, then that conversion is completed before the change to bq2[6:0] takes effect. each time a ccw is read for queue 1, the ccw location is compared with the current value of the bq2[6:0] pointer to detect a possible end-of-queue condition. for example, if bq2[6:0] is changed to ccw3 while queue 1 is converting ccw2, queue 1 is terminated after the conversion is completed. however, if bq2[6:0] is changed to ccw1 while queue 1 is converting ccw2, the qadc would not recognize a bq2[6:0] end-of-queue condition until queue 1 execution reached ccw1 again, presumably on the next pass through the queue. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . queued analog-to-digital converter (qadc) register descriptions mmc2114 MMC2113 mmc2112 ? rev. 1.0 advance information motorola queued analog-to-digital converter (qadc) 453 19.8.6 status registers this subsection describes the qadc status registers. 19.8.6.1 qadc status register 0 (qasr0) qadc status register 0 (qasr0) contains information about the state of each queue and the current a/d conversion. stop mode resets this register ($0000). read: anytime write: for flag bits (cf1, pf1, cf2, pf2, tor1, tor2): writing a 1 has no effect, write a 0 to clear. for qs[9:6] and cwp: writes have no effect. cf1 ? queue 1 completion flag cf1 indicates that a queue 1 scan has been completed. cf1 is set by the qadc when the input channel sample requested by the last ccw in queue 1 is converted, and the result is stored in the result table. address: 0x00ca_0010 and 0x00ca_0011 bit 15 14 13 12 11 10 9 bit 8 read: cf1 pf1 cf2 pf2 tor1 tor2 qs9 qs8 write: reset:00000000 bit 7654321bit 0 read: qs7 qs6 cwp5 cwp4 cwp3 cwp2 cwp1 cwp0 write: reset:00000000 = writes have no effect and the access terminates without a transfer error exception. figure 19-11. qadc status register 0 (qasr0) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . advance information mmc2114 MMC2113 mmc2112 ? rev. 1.0 454 queued analog-to-digital converter (qadc) motorola queued analog-to-digital converter (qadc) the end-of-queue 1 is identified when execution is complete on the ccw in the location prior to that pointed to by bq2, when the current ccw contains the end-of-queue code (channel 63) instead of a valid channel number, or when the currently completed ccw is in the last location of the ccw ram. when cf1 is set and queue 1 completion interrupts are enabled (cie1 = 1), the qadc requests an interrupt. the interrupt request is cleared when a 0 is written to the cf1 bit after it has been read as a 1. once set, cf1 can be cleared only by a reset or by writing a 0 to it. cf1 is updated by the qadc regardless of whether the corresponding interrupt is enabled. this allows polled recognition of queue 1 scan completion. pf1 ? queue 1 pause flag pf1 indicates that a queue 1 scan has reached a pause. pf1 is set by the qadc when the current queue 1 ccw has the pause bit set, the selected input channel has been converted, and the result has been stored in the result table. once pf1 is set, the queue enters the paused state and waits for a trigger event to allow queue execution to continue. however, a special case occurs when the ccw with the pause bit set is the last ccw in a queue; queue execution is complete. the queue status becomes idle, not paused, and both the pause and completion flags are set. another special case occurs when queue 1 is operating in software-initiated single-scan or continuous-scan mode and a ccw pause bit is set. the qadc will set pf1 and will also automatically generate a retrigger event that restarts execution after two qclk cycles. pause mode is never entered. when pf1 is set and interrupts are enabled (pie1 = 1), the qadc requests an interrupt. the interrupt request is cleared when a 0 is written to pf1, after it has been read as a 1. once set, pf1 can be cleared only by reset or by writing a 0 to it. in externally gated single-scan and continuous-scan mode, the behavior of pf1 has been redefined. when the gate closes before the end-of-queue 1 is reached, pf1 is set to indicate that an incomplete scan has occurred. in single-scan mode, a resultant interrupt can be f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . queued analog-to-digital converter (qadc) register descriptions mmc2114 MMC2113 mmc2112 ? rev. 1.0 advance information motorola queued analog-to-digital converter (qadc) 455 used to determine if queue 1 should be enabled again. in either externally gated mode, setting pf1 indicates that the results for queue 1 have not been collected during one scan (coherently). note: if a set ccw pause bit is encountered in either externally gated mode, the pause flag will not set, and execution continues without pausing. this has allowed for the modified behavior of pf1 in the externally gated modes. pf1 is maintained by the qadc regardless of whether the corresponding interrupt is enabled. pf1 may be polled to determine if the qadc has reached a pause in scanning a queue. 1 = queue 1 has reached a pause or gate closed before end-of-queue in gated mode. 0 = queue 1 has not reached a pause or gate has not closed before end-of-queue in gated mode. see table 19-6 for a summary of ccw pause bit response in all scan modes. cf2 ? queue 2 completion flag cf2 indicates that a queue 2 scan has been completed. cf2 is set by the qadc when the input channel sample requested by the last ccw in queue 2 is converted, and the result is stored in the result table. the end-of-queue 2 is identified when the current ccw contains an end-of-queue code (channel 63) instead of a valid channel number table 19-6. ccw pause bit response scan mode queue operation pf asserts? externally triggered single-scan pauses yes externally triggered continuous-scan pauses yes interval timer trigger single-scan pauses yes interval timer continuous-scan pauses yes software-initiated single-scan continues yes software-initiated continuous-scan continues yes externally gated single-scan continues no externally gated continuous-scan continues no f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . advance information mmc2114 MMC2113 mmc2112 ? rev. 1.0 456 queued analog-to-digital converter (qadc) motorola queued analog-to-digital converter (qadc) or when the currently completed ccw is in the last location of the ccw ram. when cf2 is set and queue 2 completion interrupts are enabled (cie2 = 1), the qadc requests an interrupt. the interrupt request is cleared when a 0 is written to the cf2 bit after it has been read as a 1. once set, cf2 can be cleared only by a reset or by writing a 0 to it. cf2 is updated by the qadc regardless of whether the corresponding interrupt is enabled. this allows polled recognition of queue 2 scan completion. pf2 ? queue 2 pause flag pf2 indicates that a queue 2 scan has reached a pause. pf2 is set by the qadc when the current queue 2 ccw has the pause bit set, the selected input channel has been converted, and the result has been stored in the result table. once pf2 is set, the queue enters the paused state and waits for a trigger event to allow queue execution to continue. however, a special case occurs when the ccw with the pause bit set is the last ccw in a queue: queue execution is complete. the queue status becomes idle, not paused, and both the pause and completion flags are set. another special case occurs when queue 2 is operating in software-initiated single-scan or continuous-scan mode and a ccw pause bit is set. the qadc will set pf2 and will also automatically generate a retrigger event that restarts execution after two qclk cycles. pause mode is never entered. when pf2 is set and interrupts are enabled (pie2 = 1), the qadc requests an interrupt. the interrupt request is cleared when a 0 is written to pf2, after it has been read as a 1. once set, pf2 can be cleared only by a reset or by writing a 0 to it. pf2 is maintained by the qadc regardless of whether the corresponding interrupt is enabled. pf2 may be polled to determine if the qadc has reached a pause in scanning a queue. 1 = queue 2 has reached a pause. 0 = queue 2 has not reached a pause. see table 19-6 for a summary of pause response in all scan modes. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . queued analog-to-digital converter (qadc) register descriptions mmc2114 MMC2113 mmc2112 ? rev. 1.0 advance information motorola queued analog-to-digital converter (qadc) 457 tor1 ? queue 1 trigger overrun flag tor1 indicates that an unexpected trigger event has occurred for queue 1. tor1 can be set only while queue 1 is in the active state. a trigger event generated by a transition on the external trigger pin or by the periodic/interval timer may be captured as a trigger overrun. tor1 cannot be set when the software-initiated single-scan mode or the software-initiated continuous-scan mode is selected. tor1 is set when a trigger event is received while a queue is executing and before the scan has completed or paused. tor1 has no effect on queue execution. after a trigger event has occurred for queue 1, and before the scan has completed or paused, additional queue 1 trigger events are not retained. such trigger events are considered unexpected, and the qadc sets the tor1 error status bit. an unexpected trigger event may denote a system overrun situation. in externally gated continuous-scan mode, the behavior of tor1 has been redefined. in the case when queue 1 reaches an end-of-queue condition for the second time during an open gate, tor1 is set. this is considered an overrun condition. in this case cf1 has been set for the first end-of-queue 1 condition and then tor1 sets for the second end-of-queue 1 condition. for tor1 to set, cf2 must not be cleared before the second end-of-queue 1. once set, tor1 is cleared only by a reset or by writing a 0 to it. 1 = at least one unexpected queue 1 trigger event has occurred or queue 1 reaches an end-of-queue condition for the second time in externally gated continuous scan. 0 = no unexpected queue 1 trigger events have occurred. tor2 ? queue 2 trigger overrun flag tor2 indicates that an unexpected trigger event has occurred for queue 2. tor2 can be set when queue 2 is in the active, suspended, and trigger pending states. the tor2 trigger overrun can occur only when using an external trigger mode or a periodic/interval timer mode. trigger overruns cannot occur when the software-initiated single-scan mode and the software-initiated continuous-scan mode are selected. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . advance information mmc2114 MMC2113 mmc2112 ? rev. 1.0 458 queued analog-to-digital converter (qadc) motorola queued analog-to-digital converter (qadc) tor2 is set when a trigger event is received while queue 2 is executing, suspended, or a trigger is pending. tor2 has no effect on queue execution. a trigger event that causes a trigger overrun is not retained since it is considered unexpected. an unexpected trigger event may be a system overrun situation. once set, tor2 is cleared only by a reset or by writing a 0 to it. 1 = at least one unexpected queue 2 trigger event has occurred. 0 = no unexpected queue 2 trigger events have occurred. qs[9:6] ? queue status field the 4-bit read-only qs field indicates the current condition of queue 1 and queue 2. the five queue status conditions are: ? idle ? active ? paused ? suspended ? trigger pending the two most significant bits are associated primarily with queue 1, and the remaining two bits are associated with queue 2. because the priority scheme between the two queues causes the status to be interlinked, the status bits must be considered as one 4-bit field. table 19-7 shows the bits in the qs field and how they denote the status of queue 1 and queue 2. table 19-7. queue status qs[9:6] queue 1/queue 2 states 0000 queue 1 idle, queue 2 idle 0001 queue 1 idle, queue 2 paused 0010 queue 1 idle, queue 2 active 0011 queue 1 idle, queue 2 trigger pending 0100 queue 1 paused, queue 2 idle 0101 queue 1 paused, queue 2 paused 0110 queue 1 paused, queue 2 active f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . queued analog-to-digital converter (qadc) register descriptions mmc2114 MMC2113 mmc2112 ? rev. 1.0 advance information motorola queued analog-to-digital converter (qadc) 459 one or both queues may be in the idle state. when a queue is idle, ccws are not being executed for that queue, the queue is not in the pause state, and no trigger is pending. the idle state occurs when a queue is disabled, when a queue is in a reserved mode, or when a queue is in a valid queue operating mode awaiting a trigger event to initiate queue execution. a queue is in the active state when a valid queue operating mode is selected, when the selected trigger event has occurred, or when the qadc is performing a conversion specified by a ccw from that queue. only one queue can be active at a time. one or both queues can be in the paused state. a queue is paused when the previous ccw executed from that queue had the pause bit set. the qadc does not execute any ccws from the paused queue until a trigger event occurs. consequently, the qadc can service queue 2 while queue 1 is paused. only queue 2 can be in the suspended state. when a trigger event occurs on queue 1 while queue 2 is executing, the current queue 2 conversion is aborted. the queue 2 status is reported as suspended. queue 2 transitions back to the active state when queue 1 becomes idle or paused. 0111 queue 1 paused, queue 2 trigger pending 1000 queue 1 active, queue 2 idle 1001 queue 1 active, queue 2 paused 1010 queue 1 active, queue 2 suspended 1011 queue 1 active, queue 2 trigger pending 1100 reserved 1101 reserved 1110 reserved 1111 reserved table 19-7. queue status (continued) qs[9:6] queue 1/queue 2 states f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . advance information mmc2114 MMC2113 mmc2112 ? rev. 1.0 460 queued analog-to-digital converter (qadc) motorola queued analog-to-digital converter (qadc) a trigger pending state is required because both queues cannot be active at the same time. the status of queue 2 is changed to trigger pending when a trigger event occurs for queue 2 while queue 1 is active. in the opposite case, when a trigger event occurs for queue 1 while queue 2 is active, queue 2 is aborted and the status is reported as queue 1 active, queue 2 suspended. so due to the priority scheme, only queue 2 can be in the trigger pending state. two transition cases cause the queue 2 status to be trigger pending before queue 2 is shown to be in the active state. when queue 1 is active and there is a trigger pending on queue 2, after queue 1 completes or pauses, queue 2 continues to be in the trigger pending state for a few clock cycles. the fleeting status conditions are: queue 1 idle with queue 2 trigger pending queue 1 paused with queue 2 trigger pending figure 19-12 displays the status conditions of the qs field as the qadc goes through the transition from queue 1 active to queue 2 active. the queue status field is affected by qadc stop mode. because all of the analog logic and control registers are reset, the queue status field is reset to queue 1 idle, queue 2 idle. during debug mode, the queue status field is not modified. the queue status field retains the status it held prior to freezing. as a result, the queue status can show queue 1 active, queue 2 idle, even though neither queue is being executed during freeze. cwp[5:0] ? command word pointer field the command word pointer (cwp) denotes which ccw is executing at present or was last completed. cwp is a read-only field with a valid range of 0 to 63; write operations have no effect. when a queue enters the paused state, cwp points to the ccw with the pause bit set. while in pause, the cwp value is maintained until a trigger event occurs on either queue. usually, the cwp is updated a few clock cycles before the queue status field shows that the queue has become active. for example, a read of cwp may point to a ccw in queue 2, while the queue status field shows queue 1 paused and queue 2 trigger pending. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . queued analog-to-digital converter (qadc) register descriptions mmc2114 MMC2113 mmc2112 ? rev. 1.0 advance information motorola queued analog-to-digital converter (qadc) 461 figure 19-12. queue status transition when the qadc finishes a queue scan, the cwp points to the ccw where the end-of-queue condition was detected. therefore, when the end-of-queue condition is a ccw with the eoq code (channel 63), the cwp points to the ccw containing the eoq. when the last ccw in a queue is the last ccw table location (ccw63), and it does not contain the eoq code, the end-of-queue is detected when the following ccw is read, so the cwp points to word ccw0. q1 idle/ q2 active q1 idle/ q2 idle q1 active/ q2 idle q1 paused/ q2 idle q1 active/ q2 suspended q1 active/ q2 paused q1 paused/ q2 active q1 idle/ q2 paused q1 paused/ q2 paused q1 active/ q2 trigger pending q1 paused/ q2 trigger pending (temporary) q2 complete delayed transition q1 pause bit set q2 trigger event q1 trigger event q1 pause bit set q1 complete q1 trigger event q1 complete delayed transition q1 trigger event q1 complete q1 pause bit set q1 trigger event q2 complete q2 trigger event q2 pause bit set q2 trigger event q1 trigger event q1 complete q1 trigger event q1 pause bit set q2 pause bit set q2 trigger event q1 idle/ q2 trigger pending (temporary) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . advance information mmc2114 MMC2113 mmc2112 ? rev. 1.0 462 queued analog-to-digital converter (qadc) motorola queued analog-to-digital converter (qadc) finally, when queue 1 operation is terminated after a ccw is read that is pointed to by bq2, the cwp points to the same ccw as bq2. during stop mode, cwp is reset to 0 because the control registers and the analog logic are reset. when debug mode is entered, cwp is not changed; it points to the last executed ccw. 19.8.6.2 qadc status register 1 (qasr1) stop mode resets this register ($3f3f). read: anytime write: never cwpq1[5:0] ? queue 1 command word pointer field cwpq1[5:0] points to the last queue 1 ccw executed. this is a read-only field with a valid range of 0 to 63; writes have no effect. cwpq1 always points to the last executed ccw in queue 1, regardless of which queue is active. in contrast to cwp, cpwq1 is updated when a conversion result is written. when the qadc finishes a conversion in queue 1, both the result register is written and cwpq1 is updated. address: 0x00ca_0012 and 0x00ca_0013 bit 15 14 13 12 11 10 9 bit 8 read: 0 0 cwpq15 cwpq14 cwpq13 cwpq12 cwpq11 cwpq10 write: reset:00111111 bit 7654321bit 0 read: 0 0 cwpq25 cwpq24 cwpq23 cwpq22 cwpq21 cwpq20 write: reset:00111111 = writes have no effect and the access terminates without a transfer error exception. figure 19-13. qadc status register 1 (qasr1) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . queued analog-to-digital converter (qadc) register descriptions mmc2114 MMC2113 mmc2112 ? rev. 1.0 advance information motorola queued analog-to-digital converter (qadc) 463 finally, when queue 1 operation is terminated after a ccw is read that is pointed to by bq2, cwp points to bq2 while cwpq1 points to the last queue 1 ccw. during stop mode, cwpq1 is reset to 63, because the control registers and the analog logic are reset. when debug mode is entered, cwpq1 is not changed; it points to the last executed ccw in queue 1. cwpq2[5:0] ? queue 2 command word pointer field cwpq2[5:0] points to the last queue 2 ccw executed. this is a read-only field with a valid range of 0 to 63; writes have no effect. cwpq2 always points to the last executed ccw in queue 2, regardless which queue is active. in contrast to cwp, cpwq2 is updated when a conversion result is written. when the qadc finishes a conversion in queue 2, both the result register is written and cwpq2 is updated. during stop mode, cwpq2 is reset to 63 because the control registers and the analog logic are reset. when debug mode is entered, cwpq2 is not changed; it points to the last executed ccw in queue 2. 19.8.7 conversion command word table (ccw) the conversion command word (ccw) table is 64 half-word (128 byte) long ram with 10 bits of each entry implemented. the ccw table is written by the user and is not modified by the qadc. each ccw requests the conversion of one analog channel to a digital result. the ccw specifies the analog channel number, the input sample time, and whether the queue is to pause after the current ccw. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . advance information mmc2114 MMC2113 mmc2112 ? rev. 1.0 464 queued analog-to-digital converter (qadc) motorola queued analog-to-digital converter (qadc) read: anytime except reads during stop mode are invalid write: anytime except during stop mode p ? pause bit the pause bit allows subqueues to be created within queue 1 and queue 2. the qadc performs the conversion specified by the ccw with the pause bit set and then the queue enters the pause state. another trigger event causes execution to continue from the pause to the next ccw. 1 = enter pause state after execution of current ccw. 0 = do not enter pause state after execution of current ccw. note: the p bit does not cause the queue to pause in the software. initiated modes or externally gated modes. byp ? sample amplifier bypass bit setting byp in a ccw enables the amplifier bypass mode for a conversion and subsequently changes the timing. the initial sample time is eliminated, reducing the potential conversion time by two qclks. however, due to internal rc effects, a minimum final sample time of four qclks must be allowed. when using this mode, the address: 0x00ca_0200 through 0x00ca_027e bit 15 14 13 12 11 10 9 bit 8 read: 0 0 0000 pbyp write: reset:000000uu bit 7654321bit 0 read: ist1 ist0 chan5 chan4 chan3 chan2 chan1 chan0 write: reset:uuuuuuuu = writes have no effect and the access terminates without a transfer error exception. u = unaffected figure 19-14. conversion command word table (ccw) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . queued analog-to-digital converter (qadc) register descriptions mmc2114 MMC2113 mmc2112 ? rev. 1.0 advance information motorola queued analog-to-digital converter (qadc) 465 external circuit should be of low source impedance. loading effects of the external circuitry need to be considered because the benefits of the sample amplifier are not present. 1 = amplifier bypass mode enabled 0 = amplifier bypass mode disabled note: byp is maintained for software compatibility but has no functional benefit on this version of the qadc. ist[1:0] ? input sample time field the ist field specifies the length of the sample window. the input sample time can be varied, under software control, to accommodate various input channel source impedances. longer sample times permit more accurate a/d conversions of signals with higher source impedances. table 19-8 shows the four selectable input sample times. the programmable sample time can also be used to adjust queue execution time or sampling rate by increasing the time interval between conversions. chan[5:0] ? channel number field the chan field selects the input channel number. the ccw channel field is programmed with the channel number corresponding to the analog input pin to be sampled and converted. the analog input pin channel number assignments and the pin definitions vary depending on whether the qadc multiplexed or non-multiplexed mode is used by the application. as far as queue scanning operations are concerned, there is no distinction between an internally or externally multiplexed analog input. table 19-8. input sample times ist[1:0] input sample times 00 input sample time = qclk period 2 01 input sample time = qclk period 4 10 input sample time = qclk period 8 11 input sample time = qclk period 16 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . advance information mmc2114 MMC2113 mmc2112 ? rev. 1.0 466 queued analog-to-digital converter (qadc) motorola queued analog-to-digital converter (qadc) table 19-9 shows the channel number assignments for non-multiplexed mode. table 19-10 shows the channel number assignments for multiplexed mode. programming the channel field to channel 63 denotes the end of the queue. channels 60 to 62 are special internal channels. when one of the special channels is selected, the sampling amplifier is not used. the value of v rl , v rh , or (v rh ? v rl )/2 is converted directly. programming any input sample time other than two has no benefit for the special internal channels except to lengthen the overall conversion time. table 19-9. non-multiplexed channel assignments and pin designations non-multiplexed input pins channel number (1) in ccw chan field port pin name analog pin name other functions pin type binary decimal pqb0 pqb1 pqb2 pqb3 an0 an1 an2 an3 ? ? ? ? input input input input 000000 000001 000010 000011 0 1 2 3 pqa0 pqa1 an52 an53 ? ? input/output input/output 110100 110101 52 53 pqa3 pqa4 an55 an56 etrig1 etrig2 input/output input/output 110111 111000 55 56 v rl v rh ? low reference high reference ? ? ? (v rh ? v rl )/2 input input ? 111100 111101 111110 60 61 62 ?? end-of-queue code ? 111111 63 1. all channels not listed are reserved or unimplemented and return undefined results. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . queued analog-to-digital converter (qadc) register descriptions mmc2114 MMC2113 mmc2112 ? rev. 1.0 advance information motorola queued analog-to-digital converter (qadc) 467 table 19-10. multiplexed channel assignments and pin designations multiplexed input pins channel number (1) in ccw chan field port pin name analog pin name other functions pin type binary decimal pqb0 pqb1 pqb2 pqb3 anw anx any anz ? ? ? ? input input input input 000xx0 000xx1 010xx0 010xx1 0, 2, 4, 6 1, 3, 5, 7 16, 18, 20, 22 17, 19, 21, 23 pqa0 pqa1 ? ? ma0 ma1 output output 110100 110101 52 53 pqa3 pqa4 an55 an56 etrig1 etrig2 input/output input/output 110111 111000 55 56 v rl v rh ? low reference high reference ? ? ? (v rh ? v rl )/2 input input ? 111100 111101 111110 60 61 62 ?? end-of-queue code ? 111111 63 1. all channels not listed are reserved or unimplemented and return undefined results. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . advance information mmc2114 MMC2113 mmc2112 ? rev. 1.0 468 queued analog-to-digital converter (qadc) motorola queued analog-to-digital converter (qadc) 19.8.8 result registers the result word table is a 64 half-word (128 byte) long by 10-bit wide ram. an entry is written by the qadc after completing an analog conversion specified by the corresponding ccw table entry. 19.8.8.1 right-justified unsigned result register (rjurr) read: anytime except reads during stop mode are invalid write: anytime except during stop mode result[9:0] ? result field the conversion result is unsigned, right-justified data. address: 0x00ca_0280 through 0x00ca_02fe bit 15 14 13 12 11 10 9 bit 8 read: 0 0 0000 result write: reset:000000 bit 7654321bit 0 read: result write: reset: = writes have no effect and the access terminates without a transfer error exception. figure 19-15. right-justified unsigned result register (rjurr) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . queued analog-to-digital converter (qadc) register descriptions mmc2114 MMC2113 mmc2112 ? rev. 1.0 advance information motorola queued analog-to-digital converter (qadc) 469 19.8.8.2 left-justified signed result register (ljsrr) s ? sign bit the left justified, signed format corresponds to a half-scale, offset binary, two ? s complement data format. conversion values corresponding to 1/2 full scale, 0x0200, or higher are interpreted as positive values and have a sign bit of 0. an unsigned, right justified conversion of 0x0200 would be represented as 0x0000 in this signed register, where the sign = 0 and the result = 0. for an unsigned, right justified conversion of 0x3ff (full range or v rh ), the signed equivalent in this register would be 0x7fc0, sign = 0 and result = 0x1ff. for an unsigned, right justified conversion of 0x0000 (v rl ), the signed equivalent in this register would be 0x8000, sign = 1 and result = 0x000, a two ? s complement value representing ? 512. result[14:6] ? result field the conversion result is signed, left-justified data. address: 0x00ca_0300 through 0x00ca_037e bit 15 14 13 12 11 10 9 bit 8 read: s result write: reset: bit 7654321bit 0 read: result 000000 write: reset: 000000 = writes have no effect and the access terminates without a transfer error exception. figure 19-16. left-justified signed result register (ljsrr) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . advance information mmc2114 MMC2113 mmc2112 ? rev. 1.0 470 queued analog-to-digital converter (qadc) motorola queued analog-to-digital converter (qadc) 19.8.8.3 left-justified unsigned result register (ljurr) result[15:6] ? result field the conversion result is unsigned, left-justified data. 19.9 functional description this subsection provides a functional description of the qadc. 19.9.1 result coherency the qadc supports byte and half-word reads and writes across a 16-bit data bus interface. all conversion results are stored in half-word registers, and the qadc does not allow more than one result register to be read at a time. for this reason, the qadc does not guarantee read coherency. specifically, this means that while the qadc is operating, the data in the result registers can change from one read to the next. simply initiating a read of one result register will not prevent another from being updated with a new conversion result. thus, to read any given number of result registers coherently, the queue or queues capable of modifying these registers must be inactive. this can be guaranteed by system operating conditions (such as, known completion of a software-initiated queue single-scan or no possibility of an externally triggered/gated queue scan) or by simply disabling the queues (writing mq1 and/or mq2 to 0). address: 0x00ca_0380 through 0x00ca_03fe bit 15 14 13 12 11 10 9 bit 8 read: result write: reset: bit 7654321bit 0 read: result 000000 write: reset: 000000 = writes have no effect and the access terminates without a transfer error exception. figure 19-17. left-justified unsigned result register (ljurr) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . queued analog-to-digital converter (qadc) functional description mmc2114 MMC2113 mmc2112 ? rev. 1.0 advance information motorola queued analog-to-digital converter (qadc) 471 19.9.2 external multiplexing external multiplexer chips concentrate a number of analog signals onto a few qadc inputs. this is useful for applications that need to convert more analog signals than the qadc converter can normally support. external multiplexing also puts the multiplexed chip closer to the signal source. this minimizes the number of analog signals that need to be shielded due to the proximity of noisy high speed digital signals at the microcontroller chip. for example, four 4-input multiplexer chips can be put at the connector where the analog signals first arrive on the printed circuit board. as a result, only four analog signals need to be shielded from noise as they approach the microcontroller chip, rather than having to protect 16 analog signals. however, external multiplexer chips may introduce additional noise and errors if not properly utilized. therefore, it is necessary to maintain low ? on ? resistance (the impedance of an analog switch when active within a multiplexed chip) and insert a low pass filter (r/c) on the input side of the multiplexed chip. 19.9.2.1 external multiplexing operation the qadc can use from one to four external multiplexer chips to expand the number of analog signals that may be converted. up to 16 analog channels can be converted through external multiplexer selection. the externally multiplexed channels are automatically selected from the channel field of the ccw, the same as internally multiplexed channels. the qadc is configured for the externally multiplexed mode by setting the mux bit in control register 0 (qacr0). figure 19-18 shows the maximum configuration of four external multiplexer chips connected to the qadc. the external multiplexer chips select one of four analog inputs and connect it to one analog output, which becomes an input to the qadc. the qadc provides two multiplexed address signals ? ma[1:0] ? to select one of four inputs. these inputs are connected to all four external multiplexer chips. the analog output of the four multiplexer chips are each connected to separate qadc inputs (anw, anx, any, and anz) as shown in figure 19-18 . f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . advance information mmc2114 MMC2113 mmc2112 ? rev. 1.0 472 queued analog-to-digital converter (qadc) motorola queued analog-to-digital converter (qadc) figure 19-18. external multiplexing configuration an52/ma0/pqa0 an53/ma1/pqa1 an55/etrig1pqa3 an56/etrig2/pqa4 an0/anw/pqb0 an1/anx/pqb1 an2/any/pqb2 an3/anz/pqb3 port qb port qa an0 an2 an4 an6 an1 an3 an5 an7 an16 an18 an20 an22 an17 an19 an21 an23 mux mux mux mux f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . queued analog-to-digital converter (qadc) functional description mmc2114 MMC2113 mmc2112 ? rev. 1.0 advance information motorola queued analog-to-digital converter (qadc) 473 when externally multiplexed mode is selected, the qadc automatically drives the ma output signals from the channel number in each ccw. the qadc also converts the proper input channel (anw, anx, any, and anz) by interpreting the ccw channel number. as a result, up to 16 externally multiplexed channels appear to the conversion queues as directly connected signals. user software simply puts the channel number of externally multiplexed channels into ccws. figure 19-18 shows that the two ma signals may also be analog input pins. when external multiplexing is selected, none of the ma pins can be used for analog or digital inputs. they become multiplexed address outputs and are unaffected by ddrqa[1:0]. 19.9.2.2 module version options the number of available analog channels varies, depending on whether external multiplexing is used. a maximum of eight analog channels are supported by the internal multiplexing circuitry of the converter. table 19-11 shows the total number of analog input channels supported with 0 to 4 external multiplexer chips. table 19-11. analog input channels number of analog input channels available directly connected + external multiplexed = total channels (1) , (2) 1. the external trigger inputs are not shared with two analog input pins. 2. when external multiplexing is used, two input channels are configured as multiplexed ad- dress outputs, and for each external multiplexer chip, one input channel is a multiplexed analog input. no external mux one external mux two external muxes three external muxes four external muxes 8 5 + 4 = 9 4 + 8 = 12 3 + 12 = 15 2 + 16 = 18 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . advance information mmc2114 MMC2113 mmc2112 ? rev. 1.0 474 queued analog-to-digital converter (qadc) motorola queued analog-to-digital converter (qadc) 19.9.3 analog subsystem this section describes the qadc analog subsystem, which includes the front-end analog multiplexer and analog-to-digital converter. 19.9.3.1 analog-to-digital converter operation the analog subsystem consists of the path from the input pins to the a/d converter block. signals from the queue control logic are fed to the multiplexer and state machine. the end-of-conversion (eoc) signal and the successive approximation register (sar) reflect the result of the conversion. figure 19-19 shows a block diagram of the qadc analog subsystem. figure 19-19. qadc analog subsystem block diagram pqa4 pqa0 pqb3 pqb0 v dda v ssa v rh v rl qclk start conv end of conv rst stop sar[9:0] 10-bit a/d converter input analog power 2 ist sample compar- successive ator bias circuit approximation register buffer 10 10 chan[5:0] 10-bit rc dac c samp 10 chan. decode & mux 16:1 signals from/to queue control logic 16 state machine & logic power- down internal channel decode sar timing 4 6 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . queued analog-to-digital converter (qadc) functional description mmc2114 MMC2113 mmc2112 ? rev. 1.0 advance information motorola queued analog-to-digital converter (qadc) 475 19.9.3.2 conversion cycle times total conversion time is made up of initial sample time, final sample time, and resolution time. initial sample time refers to the time during which the selected input channel is coupled through the sample buffer amplifier to the sample capacitor. the sample buffer is used to quickly reproduce its input signal on the sample capacitor and minimize charge sharing errors. during the final sampling period the amplifier is bypassed, and the multiplexer input charges the sample capacitor array directly for improved accuracy. during the resolution period, the voltage in the sample capacitor is converted to a digital value and stored in the sar. initial sample time is fixed at two qclk cycles. final sample time can be 2, 4, 8, or 16 qclk cycles, depending on the value of the ist field in the ccw. resolution time is 10 qclk cycles. a conversion requires a minimum of 14 qclk cycles (7 s with a 2.0-mhz qclk). if the maximum final sample time period of 16 qclks is selected, the total conversion time is 28 qclks or 14 s (with a 2.0-mhz qclk). figure 19-20. conversion timing if the amplifier bypass mode is enabled for a conversion by setting the amplifier bypass (byp) field in the ccw, the timing changes to that shown in figure 19-21 . see 19.8.7 conversion command word table (ccw) for more information on the byp field. the initial sample time is eliminated, reducing the potential conversion time by two qclks. when using the bypass mode, the external circuit should be of low source impedance (typically less than 10 k ? ). also, the loading effects on the external circuitry of the qadc need to be considered, because the benefits of the sample amplifier are not present. sample time successive approximation resolution sequence qclk buffer sample time: 2 cycles final sample time: n cycles (2,4,8,16) resolution time: 10 cycles f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . advance information mmc2114 MMC2113 mmc2112 ? rev. 1.0 476 queued analog-to-digital converter (qadc) motorola queued analog-to-digital converter (qadc) note: because of internal rc time constants, use of a two qclk sample time in bypass mode will cause serious errors when operating the qadc at high frequencies. figure 19-21. bypass mode conversion timing 19.9.3.3 channel decode and multiplexer the internal multiplexer selects one of the eight analog input pins for conversion. the selected input is connected to the sample buffer amplifier or to the sample capacitor. the multiplexer also includes positive and negative stress protection circuitry, which prevents deselected channels from affecting the selected channel when current is injected into the deselected channels. 19.9.3.4 sample buffer the sample buffer is used to raise the effective input impedance of the a/d converter, so that external factors (higher bandwidth or higher impedance) are less critical to accuracy. the input voltage is buffered onto the sample capacitor to reduce crosstalk between channels. 19.9.3.5 digital-to-analog converter (dac) array the digital-to-analog converter (dac) array consists of binary-weighted capacitors and a resistor-divider chain. the reference voltages, v rh and v rl , are used by the dac to perform ratiometric conversions. the dac also converts the following three internal channels: v rh ? reference voltage high v rl ? reference voltage low (v rh ? v rl )/2 ? reference voltage sample time successive approximation resolution sequence qclk sample time: n cycles (2,4,8,16) resolution time: 10 cycles f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . queued analog-to-digital converter (qadc) functional description mmc2114 MMC2113 mmc2112 ? rev. 1.0 advance information motorola queued analog-to-digital converter (qadc) 477 the dac array provides a mechanism for the successive approximation a/d conversion. resolution begins with the most significant bit (msb) and works down to the least significant bit (lsb). the switching sequence is controlled by the comparator and sar logic. the sample capacitor samples and holds the voltage to be converted. 19.9.3.6 comparator during the approximation process, the comparator senses whether the digitally selected arrangement of the dac array produces a voltage level higher or lower than the sampled input. the comparator output feeds into the sar which accumulates the a/d conversion result sequentially, beginning with the msb. 19.9.3.7 bias the bias circuit is controlled by the stop signal to power-up and power-down all the analog circuits. 19.9.3.8 successive approximation register the input of the sar is connected to the comparator output. the sar sequentially receives the conversion value one bit at a time, starting with the msb. after accumulating the 10 bits of the conversion result, the sar data is transferred to the appropriate result location, where it may be read by user software. 19.9.3.9 state machine the state machine generates all timing to perform an a/d conversion. an internal start-conversion signal indicates to the a/d converter that the desired channel has been sent to the mux. ist[1:0] denotes the desired sample time. byp determines whether to bypass the sample amplifier. once the end of conversion has been reached a signal is sent to the queue control logic indicating that a result is available for storage in the result ram. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . advance information mmc2114 MMC2113 mmc2112 ? rev. 1.0 478 queued analog-to-digital converter (qadc) motorola queued analog-to-digital converter (qadc) 19.10 digital control the digital control subsystem includes the control logic to sequence the conversion activity, the clock and periodic/interval timer, control and status registers, the conversion command word table ram, and the result word table ram. the central element for control of qadc conversions is the 64-entry conversion command word (ccw) table. each ccw specifies the conversion of one input channel. depending on the application, one or two queues can be established in the ccw table. a queue is a scan sequence of one or more input channels. by using a pause mechanism, subqueues can be created in the two queues. each queue can be operated using one of several different scan modes. the scan modes for queue 1 and queue 2 are programmed in control registers qacr1 and qacr2. once a queue has been started by a trigger event (any of the ways to cause the qadc to begin executing the ccws in a queue or subqueue), the qadc performs a sequence of conversions and places the results in the result word table. 19.10.1 queue priority timing examples this subsection describes the qadc priority scheme when trigger events on two queues overlap or conflict. 19.10.1.1 queue priority queue 1 has priority over queue 2 execution. these cases show the conditions under which queue 1 asserts its priority: when a queue is not active, a trigger event for queue 1 or queue 2 causes the corresponding queue execution to begin. when queue 1 is active and a trigger event occurs for queue 2, queue 2 cannot begin execution until queue 1 reaches completion or the paused state. the status register records the trigger event by reporting the queue 2 status as trigger pending. additional trigger events for queue 2, which occur before execution can begin, are flagged as trigger overruns. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . queued analog-to-digital converter (qadc) digital control mmc2114 MMC2113 mmc2112 ? rev. 1.0 advance information motorola queued analog-to-digital converter (qadc) 479 when queue 2 is active and a trigger event occurs for queue 1, the current queue 2 conversion is aborted. the status register reports the queue 2 status as suspended. any trigger events occurring for queue 2 while it is suspended are flagged as trigger overruns. once queue 1 reaches the completion or the paused state, queue 2 begins executing again. the programming of the resume bit in qacr2 determines which ccw is executed in queue 2. when simultaneous trigger events occur for queue 1 and queue 2, queue 1 begins execution and the queue 2 status is changed to trigger pending. when subqueues are paused the pause feature can be used to divide queue 1 and/or queue 2 into multiple subqueues. a subqueue is defined by setting the pause bit in the last ccw of the subqueue. figure 19-22 shows the ccw format and an example of using pause to create subqueues. queue 1 is shown with four ccws in each subqueue and queue 2 has two ccws in each subqueue. the operating mode selected for queue 1 determines what type of trigger event causes the execution of each of the subqueues within queue 1. similarly, the operating mode for queue 2 determines the type of trigger event required to execute each of the subqueues within queue 2. for example, when the external trigger rising edge continuous-scan mode is selected for queue 1, and there are six subqueues within queue 1, a separate rising edge is required on the external trigger pin after every pause to begin the execution of each subqueue (refer to figure 19-22 ). the choice of single-scan or continuous-scan applies to the full queue, and is not applied to each subqueue. once a subqueue is initiated, each ccw is executed sequentially until the last ccw in the subqueue is executed and the pause state is entered. execution can only continue with the next ccw, which is the beginning of the next subqueue. a subqueue cannot be executed a second time before the overall queue execution has been completed. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . advance information mmc2114 MMC2113 mmc2112 ? rev. 1.0 480 queued analog-to-digital converter (qadc) motorola queued analog-to-digital converter (qadc) figure 19-22. qadc queue operation with pause trigger events which occur during the execution of a subqueue are ignored, except that the trigger overrun flag is set. when a continuous-scan mode is selected, a trigger event occurring after the completion of the last subqueue (after the queue completion flag is set), causes the execution to continue with the first subqueue, starting with the first ccw in the queue. when the qadc encounters a ccw with the pause bit set, the queue enters the paused state after completing the conversion specified in the ccw with the pause bit. the pause flag is set and a pause interrupt may optionally be requested. the status of the queue is shown to be paused, indicating completion of a subqueue. the qadc then waits for another trigger event to again begin execution of the next subqueue. beginning of queue 1 00 channel select, sample, hold, a/d conversion conversion command result word table 0 pause word (ccw) table 0 0 1 0 0 0 1 0 pause 00 p 0 pause 0 0 1 0 1 0 1 0 pause p end of queue 1 beginning of queue 2 bq2 pause pause end of queue 2 p 1 0 63 63 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . queued analog-to-digital converter (qadc) digital control mmc2114 MMC2113 mmc2112 ? rev. 1.0 advance information motorola queued analog-to-digital converter (qadc) 481 19.10.1.2 queue priority schemes because there are two conversion command queues and only one a/d converter, a priority scheme determines which conversion occurs. each queue has a variety of trigger events that are intended to initiate conversions, and they can occur asynchronously in relation to each other and other conversions in progress. for example, a queue can be idle awaiting a trigger event; a trigger event can have occurred, but the first conversion has not started; a conversion can be in progress; a pause condition can exist awaiting another trigger event to continue the queue; and so on. the following paragraphs and figures outline the prioritizing criteria used to determine which conversion occurs in each overlap situation. note: each situation in figure 19-23 through figure 19-33 is labeled s1 through s19. in each diagram, time is shown increasing from left to right. the execution of queue 1 and queue 2 (q1 and q2) is shown as a string of rectangles representing the execution time of each ccw in the queue. in most of the situations, there are four ccws (labeled c1 to c4) in both queue 1 and queue 2. in some of the situations, ccw c2 is presumed to have the pause bit set, to show the similarities of pause and end-of-queue as terminations of queue execution. trigger events are described in table 19-12 . when a trigger event causes a ccw execution in progress to be aborted, the aborted conversion is shown as a ragged end of a shortened ccw rectangle. table 19-12. trigger events trigger events t1 events that trigger queue 1 execution (external trigger, software-initiated single-scan enable bit, or completion of the previous continuous loop) t2 events that trigger queue 2 execution (external trigger, software-initiated single-scan enable bit, timer period/interval expired, or completion of the previous continuous loop) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . advance information mmc2114 MMC2113 mmc2112 ? rev. 1.0 482 queued analog-to-digital converter (qadc) motorola queued analog-to-digital converter (qadc) the situation diagrams also show when key status bits are set. table 19-13 describes the status bits. below the queue execution flows are three sets of blocks that show the status information that is made available to the user. the first two rows of status blocks show the condition of each queue as: idle active pause suspended (queue 2 only) trigger pending the third row of status blocks shows the 4-bit qs status register field that encodes the condition of the two queues. two transition status cases, qs = 0011 and qs = 0111, are not shown because they exist only very briefly between stable status conditions. the first three examples in figure 19-23 through figure 19-25 (s1, s2, and s3) show what happens when a new trigger event is recognized before the queue has completed servicing the previous trigger event on the same queue. in situation s1 ( figure 19-23 ), one trigger event is being recognized on each queue while that queue is still working on the previously recognized trigger event. the trigger overrun error status bit is set, and the premature trigger event is otherwise ignored. a trigger event that occurs before the servicing of the previous trigger event is through does not disturb the queue execution in progress. table 19-13. status bits bit function cf flag set when the end of the queue is reached pf flag set when a queue completes execution up through a pause bit trigger overrun error (tor) set when a new trigger event occurs before the queue is finished servicing the previous trigger event f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . queued analog-to-digital converter (qadc) digital control mmc2114 MMC2113 mmc2112 ? rev. 1.0 advance information motorola queued analog-to-digital converter (qadc) 483 figure 19-23. ccw priority situation 1 in situation s2 ( figure 19-24 ), more than one trigger event is recognized before servicing of a previous trigger event is complete. the trigger overrun bit is again set, but the additional trigger events are otherwise ignored. after the queue is complete, the first newly detected trigger event causes queue execution to begin again. when the trigger event rate is high, a new trigger event can be seen very soon after completion of the previous queue, leaving little time to retrieve the previous results. also, when trigger events are occurring at a high rate for queue 1, the lower priority queue 2 channels may not get serviced at all. figure 19-24. ccw priority situation 2 q1: q2: qs: idle idle active idle 0000 1000 0000 0010 0000 tor1 t1 t1 q1: c1 c2 c3 c4 cf1 c1 c2 c3 c4 tor2 t2 t2 q2: cf2 idle active t1 active idle q1: q2: qs: idle active idle active idle 1000 1000 0000 0010 0000 c1 c2 c3 c4 tor2 t2 t2 q2: cf2 idle c1 c2 c3 c4 t1 cf1 c1 c2 c3 c4 tor1 t1 q1: cf1 tor1 t1 tor1 t1 tor2 t2 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . advance information mmc2114 MMC2113 mmc2112 ? rev. 1.0 484 queued analog-to-digital converter (qadc) motorola queued analog-to-digital converter (qadc) situation s3 ( figure 19-25 ) shows that when the pause feature is used, the trigger overrun error status bit is set the same way and that queue execution continues unchanged. figure 19-25. ccw priority situation 3 the next two situations consider trigger events that occur for the lower priority queue 2, while queue 1 is actively being serviced. situation s4 ( figure 19-26 ) shows that a queue 2 trigger event is recognized while queue 1 is active is saved, and as soon as queue 1 is finished, queue 2 servicing begins. figure 19-26. ccw priority situation 4 pause q1: q2: qs: idle active idle active idle 1000 0110 0001 0010 active 0000 idle c1 c2 t1 t1 q1: tor1 pf1 c1 c2 0000 q2: 0100 tor2 pf2 t2 t2 0101 c3 c4 t1 t1 tor1 cf1 active pause 1001 c3 c4 cf2 t2 t2 tor2 q1: q2: qs: idle idle active idle 0000 1000 0010 active 0000 c1 c2 c3 c4 t1 q1: cf1 q2: c1 c2 c3 c4 t2 cf2 idle 1011 triggered f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . queued analog-to-digital converter (qadc) digital control mmc2114 MMC2113 mmc2112 ? rev. 1.0 advance information motorola queued analog-to-digital converter (qadc) 485 situation s5 ( figure 19-27 ) shows that when multiple queue 2 trigger events are detected while queue 1 is busy, the trigger overrun error bit is set, but queue 1 execution is not disturbed. situation s5 also shows that the effect of queue 2 trigger events during queue 1 execution is the same when the pause feature is used for either queue. figure 19-27. ccw priority situation 5 the remaining situations, s6 through s11, show the impact of a queue 1 trigger event occurring during queue 2 execution. because queue 1 has higher priority, the conversion taking place in queue 2 is aborted so that there is no variable latency time in responding to queue 1 trigger events. in situation 6 ( figure 19-28 ), the conversion initiated by the second ccw in queue 2 is aborted just before the conversion is complete, so that queue 1 execution can begin. queue 2 is considered suspended. after queue 1 is finished, queue 2 starts over with the first ccw, when the resume control bit is set to 0. situation s7 ( figure 19-29 ) shows that when pause operation is not used with queue 2, queue 2 suspension works the same way. q1: q2: qs: idle idle idle 0000 1000 0010 active 0000 c1 c2 t1 q1: c1 c2 pf2 c3 c4 c3 c4 cf2 idle 1011 trig q2: t2 t2 pf1 pause active pause tor2 t2 t2 cf1 tor2 t1 active trig 0110 active active 0101 1001 1011 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . advance information mmc2114 MMC2113 mmc2112 ? rev. 1.0 486 queued analog-to-digital converter (qadc) motorola queued analog-to-digital converter (qadc) figure 19-28. ccw priority situation 6 figure 19-29. ccw priority situation 7 idle q1: q2: qs idle idle 0000 1000 active c1 c2 t1 q1: c1 c3 c4 idle q2: pf1 pause active cf1 t1 active suspend 0100 active active 0110 1010 c1 c2 c3 c4 cf2 t2 0010 0000 resume = 0 c2 t1 pause q1: q2: qs: idle active idle active idle 0010 0110 1010 0010 active 0000 idle q1: pf1 c1 c2 0000 1010 active 0110 c1 q2: t2 c1 pf2 t1 c3 c4 cf1 c3 cf2 suspend pause suspend t2 c1 c3 c2 active act 0101 c4 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . queued analog-to-digital converter (qadc) digital control mmc2114 MMC2113 mmc2112 ? rev. 1.0 advance information motorola queued analog-to-digital converter (qadc) 487 situations s8 and s9 ( figure 19-30 and figure 19-31 ) repeat the same two situations with the resume bit set to a 1. when the resume bit is set, following suspension, queue 2 resumes execution with the aborted ccw, not the first ccw, in the queue. figure 19-30. ccw priority situation 8 figure 19-31. ccw priority situation 9 idle q1: q2: qs: idle idle 0000 1000 0010 active c1 c2 t1 q1: c1 c3 c4 idle q2: pf1 pause active cf1 t1 active suspend 0100 active active 0110 1010 c2 c3 c4 cf2 t2 0000 resume=1 c2 t1 pause q1: q2: qs: idle active idle act idle 0010 0110 1010 0010 active 0000 idle q1: pf1 c1 c2 0000 1010 0101 active pause 0110 c1 q2: t2 c2 pf2 t1 c3 c4 cf1 c4 cf2 suspend act active suspend t2 c3 c1 resume=1 c2 c4 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . advance information mmc2114 MMC2113 mmc2112 ? rev. 1.0 488 queued analog-to-digital converter (qadc) motorola queued analog-to-digital converter (qadc) situations s10 and s11 ( figure 19-32 and figure 19-33 ) show that when an additional trigger event is detected for queue 2 while the queue is suspended, the trigger overrun error bit is set, the same as if queue 2 were being executed when a new trigger event occurs. trigger overrun on queue 2 thus allows the user to know that queue 1 is taking up so much qadc time that queue 2 trigger events are being lost. figure 19-32. ccw priority situation 10 figure 19-33. ccw priority situation 11 t1 t1 pause q1: q2: qs: idle active idle active idle 0010 0110 1010 0010 active 0000 idle q1: pf1 c1 c2 0000 1010 0101 active pause 0110 q2: t2 pf2 c1 c2 c3 c4 cf1 c3 c4 cf2 t2 c3 suspend active c1 act suspend t2 tor2 t2 tor2 resume = 0 c2 t1 t1 c3 c4 cf1 pause q1: q2: qs: idle active idle act idle 0010 0110 1010 0010 active 0000 idle q1: pf1 c1 c2 0000 1010 0101 active pause 0110 q2: t2 suspend act c1 active suspend t2 tor2 t2 tor2 c2 pf2 c4 cf2 t2 c3 c2 c4 resume = 1 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . queued analog-to-digital converter (qadc) digital control mmc2114 MMC2113 mmc2112 ? rev. 1.0 advance information motorola queued analog-to-digital converter (qadc) 489 the previous situations cover normal overlap conditions that arise with asynchronous trigger events on the two queues. an additional conflict to consider is that the freeze condition can arise while the qadc is actively executing ccws. the conventional use for the debug mode is for software/hardware debugging. when the cpu enters background debug mode, peripheral modules can cease operation. when freeze is detected, the qadc completes the conversion in progress, unlike the abort that occurs when queue 1 suspends queue 2. after the freeze condition is removed, the qadc continues queue execution with the next ccw in sequence. trigger events that occur during freeze are not captured. when a trigger event is pending for queue 2 before freeze begins, that trigger event is remembered when the freeze is passed. similarly, when freeze occurs while queue 2 is suspended, after freeze, queue 2 resumes execution as soon as queue 1 is finished. situations 12 through 19 ( figure 19-34 to figure 19-41 ) show examples of all of the freeze situations. figure 19-34. ccw freeze situation 12 figure 19-35. ccw freeze situation 13 c3 c4 cf1 c1 c2 t1 q1: freeze c1 c2 t2 q2: cf2 c3 c4 freeze f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . advance information mmc2114 MMC2113 mmc2112 ? rev. 1.0 490 queued analog-to-digital converter (qadc) motorola queued analog-to-digital converter (qadc) figure 19-36. ccw freeze situation 14 figure 19-37. ccw freeze situation 15 figure 19-38. ccw freeze situation 16 c1 c2 t1 q1: cf1 c3 c4 freeze t1 t1 t2 t2 triggers ignored c1 c2 t2 q2: cf2 c3 c4 freeze t2 t2 t1 t1 triggers ignored c1 c2 t1 q1: cf1 c3 c4 freeze t1 t1 pf1 triggers ignored f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . queued analog-to-digital converter (qadc) digital control mmc2114 MMC2113 mmc2112 ? rev. 1.0 advance information motorola queued analog-to-digital converter (qadc) 491 figure 19-39. ccw freeze situation 17 figure 19-40. ccw freeze situation 18 figure 19-41. ccw freeze situation 19 c1 c2 t2 q2: cf2 c3 c4 freeze t2 t2 pf2 triggers ignored c1 c2 t1 q1: cf1 c3 c4 freeze t2 c1 c2 q2: c3 cf2 c4 trigger captured, response delayed after freeze c1 c2 t1 q1: cf1 c4 freeze cf2 c4 c1 c2 t2 q2: c3 c3 c4 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . advance information mmc2114 MMC2113 mmc2112 ? rev. 1.0 492 queued analog-to-digital converter (qadc) motorola queued analog-to-digital converter (qadc) 19.10.2 boundary conditions the queue operation boundary conditions are: the first ccw in a queue specifies channel 63, the end-of-queue (eoq) code. the queue becomes active and the first ccw is read. the end-of-queue is recognized, the completion flag is set, and the queue becomes idle. a conversion is not performed. bq2 (beginning of queue 2) is set at the end of the ccw table (63) and a trigger event occurs on queue 2. the end-of-queue condition is recognized, a conversion is performed, the completion flag is set, and the queue becomes idle. bq2 is set to ccw0 and a trigger event occurs on queue 1. after reading ccw0, the end-of-queue condition is recognized, the completion flag is set, and the queue becomes idle. a conversion is not performed. bq2 (beginning of queue 2) is set beyond the end of the ccw table (64 ? 127) and a trigger event occurs on queue 2. the end-of-queue condition is recognized immediately, the completion flag is set, and the queue becomes idle. a conversion is not performed. note: multiple end-of-queue conditions may be recognized simultaneously, although there is no change in qadc behavior. for example, if bq2 is set to ccw0, ccw0 contains the eoq code, and a trigger event occurs on queue 1, the qadc reads ccw0 and detects both end-of-queue conditions. the completion flag is set and queue 1 becomes idle. boundary conditions also exist for combinations of pause and end-of-queue. one case is when a pause bit is in one ccw and an end-of-queue condition is in the next ccw. the conversion specified by the ccw with the pause bit set completes normally. the pause flag is set. however, because the end-of-queue condition is recognized, the completion flag is also set and the queue status becomes idle, not paused. examples of this situation include: the pause bit is set in ccw5 and the channel 63 (eoq) code is in ccw6. the pause is in ccw63. during queue 1 operation, the pause bit is set in ccw20 and bq2 points to ccw21. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . queued analog-to-digital converter (qadc) digital control mmc2114 MMC2113 mmc2112 ? rev. 1.0 advance information motorola queued analog-to-digital converter (qadc) 493 another pause and end-of-queue boundary condition occurs when the pause and an end-of-queue condition occur in the same ccw. both the pause and end-of-queue conditions are recognized simultaneously. the end-of-queue condition has precedence so a conversion is not performed for the ccw and the pause flag is not set. the qadc sets the completion flag and the queue status becomes idle. examples of this situation are: the pause bit is set in ccw10 and eoq is programmed into ccw10. during queue 1 operation, the pause bit set in ccw32, which is also bq2. 19.10.3 scan modes the qadc queuing mechanism allows application software to utilize different requirements for automatically scanning input channels. in single-scan mode, a single pass through a sequence of conversions defined by a queue is performed. in continuous-scan mode, multiple passes through a sequence of conversions defined by a queue are executed. the possible modes are: disabled mode and reserved mode software-initiated single-scan mode externally triggered single-scan mode externally gated single-scan mode interval timer single-scan mode software-initiated continuous-scan mode externally triggered continuous-scan mode externally gated continuous-scan mode periodic timer continuous-scan mode the following paragraphs describe single-scan and continuous-scan operations. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . advance information mmc2114 MMC2113 mmc2112 ? rev. 1.0 494 queued analog-to-digital converter (qadc) motorola queued analog-to-digital converter (qadc) 19.10.4 disabled mode when disabled mode is selected, the queue is not active. trigger events cannot initiate queue execution. when both queue 1 and queue 2 are disabled, there is no possibility of encountering wait states when accessing ccw table and result ram. when both queues are disabled, it is safe to change the qclk prescaler values. 19.10.5 reserved mode reserved mode is available for future mode definitions. when reserved mode is selected, the queue is not active. the behavior is the same as disabled mode. 19.10.6 single-scan modes a single-scan queue operating mode is used to execute a single pass through a sequence of conversions defined by a queue. by programming the mq1 field in qacr1 or the mq2 field in qacr2, these modes can be selected: software-initiated single-scan mode externally triggered single-scan mode externally gated single-scan mode interval timer single-scan mode note: queue 2 cannot be programmed for externally gated single-scan mode. in all single-scan queue operating modes, queue execution is enabled by writing the single-scan enable bit to a 1 in the queue ? s control register. the single-scan enable bits, sse1 and sse2, are provided for queue 1 and queue 2, respectively. until a queue ? s single-scan enable bit is set, any trigger events for that queue are ignored. the single-scan enable bit may be set to a 1 during the same write cycle that selects the single-scan queue operating mode. the single-scan enable bit can be written only to 1, but will always read 0. once set, writing the single-scan enable bit to 0 has no effect. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . queued analog-to-digital converter (qadc) digital control mmc2114 MMC2113 mmc2112 ? rev. 1.0 advance information motorola queued analog-to-digital converter (qadc) 495 only the qadc can clear the single-scan enable bit. the completion flag, completion interrupt, or queue status is used to determine when the queue has completed. after the single-scan enable bit is set, a trigger event causes the qadc to begin execution with the first ccw in the queue. the single-scan enable bit remains set until the queue is completed. after the queue reaches completion, the qadc resets the single-scan enable bit to 0. writing the single-scan enable bit to a 1 or a 0 before the queue scan is complete has no effect; however, if the queue operating mode is changed, the new queue operating mode and the value of the single-scan enable bit are recognized immediately. the conversion in progress is aborted, and the new queue operating mode takes effect. in software-initiated single-scan mode, writing a 1 to the single-scan enable bit causes the qadc to generate a trigger event internally, and queue execution begins immediately. in the other single-scan queue operating modes, once the single-scan enable bit is written, the selected trigger event must occur before the queue can start. the single-scan enable bit allows the entire queue to be scanned once. a trigger overrun is captured if a trigger event occurs during queue execution in an edge-sensitive external trigger mode or a periodic/interval timer mode. in the interval timer single-scan mode, the next expiration of the timer is the trigger event for the queue. after queue execution is complete, the queue status is shown as idle. the queue can be restarted by setting the single-scan enable bit to 1. queue execution begins with the first ccw in the queue. 19.10.6.1 software-initiated single-scan mode software can initiate the execution of a scan sequence for queue 1 or 2 by selecting software-initiated single-scan mode and writing the single-scan enable bit in qacr1 or qacr2. a trigger event is generated internally and the qadc immediately begins execution of the first ccw in the queue. if a pause occurs, another trigger event is generated internally, and then execution continues without pausing. the qadc automatically performs the conversions in the queue until an end-of-queue condition is encountered. the queue remains idle until the f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . advance information mmc2114 MMC2113 mmc2112 ? rev. 1.0 496 queued analog-to-digital converter (qadc) motorola queued analog-to-digital converter (qadc) single-scan enable bit is again set. while the time to internally generate and act on a trigger event is very short, the queue status field can be read as momentarily indicating that the queue is paused. the trigger overrun flag is never set while in software-initiated single-scan mode. the software-initiated single-scan mode is useful when: complete control of queue execution is required there is a need to easily alternate between several queue sequences 19.10.6.2 externally triggered single-scan mode the externally triggered single-scan mode is available on both queue 1 and queue 2. both rising and falling edge triggered modes are available. a scan must be enabled by setting the single-scan enable bit for the queue. the first external trigger edge causes the queue to be executed one time. each ccw is read and the indicated conversions are performed until an end-of-queue condition is encountered. after the queue is completed, the qadc clears the single-scan enable bit. the single-scan enable bit can be written again to allow another scan of the queue to be initiated by the next external trigger edge. the externally triggered single-scan mode is useful when the input trigger rate can exceed the queue execution rate. analog samples can be taken in sync with an external event, even though application software does not require data taken from every edge. externally triggered single-scan mode can be enabled to get one set of data and, at a later time, be enabled again for the next set of samples. when a pause bit is encountered during externally triggered single-scan mode, another trigger event is required for queue execution to continue. software involvement is not required for queue execution to continue from the paused state. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . queued analog-to-digital converter (qadc) digital control mmc2114 MMC2113 mmc2112 ? rev. 1.0 advance information motorola queued analog-to-digital converter (qadc) 497 19.10.6.3 externally gated single-scan mode the qadc provides external gating for queue 1 only. when externally gated single-scan mode is selected, the input level on the associated external trigger pin enables and disables queue execution. the polarity of the external gate signal is fixed so that only a high level opens the gate and a low level closes the gate. once the gate is open, each ccw is read and the indicated conversions are performed until the gate is closed. queue scan must be enabled by setting the single-scan enable bit for queue 1. if a pause is encountered, the pause flag does not set, and execution continues without pausing. while the gate is open, queue 1 executes one time. each ccw is read and the indicated conversions are performed until an end-of-queue condition is encountered. when queue 1 completes, the qadc sets the completion flag (cf1) and clears the single-scan enable bit. set the single-scan enable bit again to allow another scan of queue 1 to be initiated during the next open gate. if the gate closes before queue 1 completes execution, the current ccw completes, execution of queue 1 stops, the single-scan enable bit is cleared, and the pf1 bit is set. the cwpq1 field can be read to determine the last valid conversion in the queue. the single-scan enable bit must be set again and the pf1 bit should be cleared before another scan of queue 1 is initiated during the next open gate. the start of queue 1 is always the first ccw in the ccw table. because the gate level is only sampled after each conversion during queue execution, closing the gate for a period less than a conversion time interval does not guarantee the closure will be captured. 19.10.6.4 interval timer single-scan mode both queues can use the periodic/interval timer in a single-scan queue operating mode. the timer interval can range from 2 7 to 2 17 qclk cycles in binary multiples. when the interval timer single-scan mode is selected and the single-scan enable bit is set in qacr1 or qacr2, the timer begins counting. when the time interval elapses, an internal trigger event is generated to start the queue and the qadc begins execution with the first ccw. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . advance information mmc2114 MMC2113 mmc2112 ? rev. 1.0 498 queued analog-to-digital converter (qadc) motorola queued analog-to-digital converter (qadc) the qadc automatically performs the conversions in the queue until a pause or an end-of-queue condition is encountered. when a pause occurs, queue execution stops until the timer interval elapses again, and queue execution continues. when queue execution reaches an end-of-queue situation, the single-scan enable bit is cleared. set the single-scan enable bit again to allow another scan of the queue to be initiated by the interval timer. the interval timer generates a trigger event whenever the time interval elapses. the trigger event may cause queue execution to continue following a pause or may be considered a trigger overrun. once queue execution is completed, the single-scan enable bit must be set again to allow the timer to count again. normally, only one queue is enabled for interval timer single-scan mode, and the timer will reset at the end-of-queue. however, if both queues are enabled for either single-scan or continuous interval timer mode, the end-of-queue condition will not reset the timer while the other queue is active. in this case, the timer will reset when both queues have reached end-of-queue. see 19.10.9 periodic/interval timer for a definition of interval timer reset conditions. the interval timer single-scan mode can be used in applications that need coherent results. for example: when it is necessary that all samples are guaranteed to be taken during the same scan of the analog pins when the interrupt rate in the periodic timer continuous-scan mode would be too high in sensitive battery applications, where the interval timer single-scan mode uses less power than the software-initiated continuous-scan mode f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . queued analog-to-digital converter (qadc) digital control mmc2114 MMC2113 mmc2112 ? rev. 1.0 advance information motorola queued analog-to-digital converter (qadc) 499 19.10.7 continuous-scan modes a continuous-scan queue operating mode is used to execute multiple passes through a sequence of conversions defined by a queue. by programming the mq1 field in qacr1 or the mq2 field in qacr2, these modes can be selected: software-initiated continuous-scan mode externally triggered continuous-scan mode externally gated continuous-scan mode periodic timer continuous-scan mode note: queue 2 cannot be programmed for externally gated continuous-scan mode. when a queue is programmed for a continuous-scan mode, the single-scan enable bit in the queue control register does not have any meaning or effect. as soon as the queue operating mode is programmed, the selected trigger event can initiate queue execution. in the case of software-initiated continuous-scan mode, the trigger event is generated internally and queue execution begins immediately. in the other continuous-scan queue operating modes, the selected trigger event must occur before the queue can start. a trigger overrun is captured if a trigger event occurs during queue execution in the externally triggered continuous-scan mode or the periodic timer continuous-scan mode. after queue execution is complete, the queue status is shown as idle. because the continuous-scan queue operating modes allow the entire queue to be scanned multiple times, software involvement is not needed for queue execution to continue from the idle state. the next trigger event causes queue execution to begin again, starting with the first ccw in the queue. note: in continuous-scan modes, all samples are guaranteed to be taken during one pass through the queue (coherently), except when a queue 1 trigger event halts queue 2 execution. the time between consecutive conversions has been designed to be consistent. however, for queues that end with a ccw containing the eoq code (channel 63), the time f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . advance information mmc2114 MMC2113 mmc2112 ? rev. 1.0 500 queued analog-to-digital converter (qadc) motorola queued analog-to-digital converter (qadc) between the last queue conversion and the first queue conversion requires one additional ccw fetch cycle. continuous samples are not coherent at this boundary. in addition, the time from trigger to first conversion cannot be guaranteed, because it is a function of clock synchronization, programmable trigger events, queue priorities, and so on. 19.10.7.1 software-initiated continuous-scan mode when software-initiated continuous-scan mode is selected, the trigger event is generated automatically by the qadc. queue execution begins immediately. if a pause is encountered, another trigger event is generated internally, and execution continues without pausing. when the end-of-queue is reached, another internal trigger event is generated and queue execution restarts at the beginning of the queue. while the time to internally generate and act on a trigger event is very short, the queue status field can be read as momentarily indicating that the queue is idle. the trigger overrun flag is never set while in software-initiated continuous-scan mode. the software-initiated continuous-scan mode keeps the result registers updated more frequently than any of the other queue operating modes. the result table can always be read to get the latest converted value for each channel. the channels scanned are kept up to date by the qadc without software involvement. the software-initiated continuous-scan mode may be chosen for either queue, but is normally used only with queue 2. when software-initiated continuous-scan mode is chosen for queue 1, that queue operates continuously and queue 2, being lower in priority, never gets executed. the short interval of time between a queue 1 completion and the subsequent trigger event is not sufficient to allow queue 2 execution to begin. the software-initiated continuous-scan mode is a useful choice with queue 2 for converting channels that do not need to be synchronized to anything or for slow-to-change analog channels. interrupts are normally not used with the software-initiated continuous-scan mode. rather, the f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . queued analog-to-digital converter (qadc) digital control mmc2114 MMC2113 mmc2112 ? rev. 1.0 advance information motorola queued analog-to-digital converter (qadc) 501 latest conversion results can be read from the result table at any time. once initiated, software action is not needed to sustain conversions of channel. 19.10.7.2 externally triggered continuous-scan mode the qadc provides external trigger pins for both queues. when externally triggered continuous-scan mode is selected, a transition on the associated external trigger pin initiates queue execution. the polarity of the external trigger signal is programmable, so that a mode which begins queue execution on the rising or falling edge can be selected. each ccw is read and the indicated conversions are performed until an end-of-queue condition is encountered. when the next external trigger edge is detected, queue execution begins again automatically. software involvement is not needed between trigger events. when a pause bit is encountered in externally triggered continuous-scan mode, another trigger event is required for queue execution to continue. software involvement is not needed for queue execution to continue from the paused state. some applications need to synchronize the sampling of analog channels to external events. there are cases when it is not possible to use software initiation of the queue scan sequence, because interrupt response times vary. externally triggered continuous-scan mode is useful in these cases. 19.10.7.3 externally gated continuous-scan mode the qadc provides external gating for queue 1 only. when externally gated continuous-scan mode is selected, the input level on the associated external trigger pin enables and disables queue execution. the polarity of the external gate signal is fixed so that a high level opens the gate and a low level closes the gate. once the gate is open, each ccw is read and the indicated conversions are performed until the gate is closed. when the gate opens again, queue execution automatically restarts at the beginning of the queue. software involvement is not needed between trigger events. if a pause in a ccw is encountered, the pause flag does not set, and execution continues without pausing. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . advance information mmc2114 MMC2113 mmc2112 ? rev. 1.0 502 queued analog-to-digital converter (qadc) motorola queued analog-to-digital converter (qadc) the purpose of externally gated continuous-scan mode is to continuously collect digitized samples while the gate is open and to have the most recent samples available. it is up to the programmer to ensure that the gate is not opened so long that an end-of-queue is reached. in the event that the queue completes before the gate closes, the cf1 flag will set, and the queue will roll over to the beginning and continue conversions until the gate closes. if the gate remains open and the cf1 flag is not cleared, when the queue completes a second time the tor1 flag will set and the queue will roll-over again. the queue will continue to execute until the gate closes or the mode is disabled. if the gate closes before queue 1 completes execution, the qadc stops and sets the pf1 bit to indicate an incomplete queue. the cwpq1 field can be read to determine the last valid conversion in the queue. if the gate opens again, execution of queue 1 restarts. the start of queue 1 is always the first ccw in the ccw table. the condition of the gate is only sampled after each conversion during queue execution, so closing the gate for a period less than a conversion time interval does not guarantee the closure will be captured. 19.10.7.4 periodic timer continuous-scan mode the qadc includes a dedicated periodic timer for initiating a scan sequence on queue 1 and/or queue 2. a programmable timer interval ranging from 2 7 to 2 17 times the qclk period in binary multiples can be selected. the qclk period is prescaled down from the mcu clock. when a periodic timer continuous-scan mode is selected, the timer begins counting. after the programmed interval elapses, the timer generated trigger event starts the appropriate queue. the qadc automatically performs the conversions in the queue until an end-of-queue condition or a pause is encountered. when a pause occurs, the qadc waits for the periodic interval to expire again, then continues with the queue. once eoq has been detected, the next trigger event causes queue execution to restart with the first ccw in the queue. the periodic timer generates a trigger event whenever the time interval elapses. the trigger event may cause queue execution to continue following a pause or queue completion or may be considered a trigger f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . queued analog-to-digital converter (qadc) digital control mmc2114 MMC2113 mmc2112 ? rev. 1.0 advance information motorola queued analog-to-digital converter (qadc) 503 overrun. as with all continuous-scan queue operating modes, software action is not needed between trigger events. because both queues may be triggered by the periodic/interval timer, see 19.10.9 periodic/interval timer for a summary of periodic/interval timer reset conditions. 19.10.8 qadc clock (qclk) generation figure 19-42 is a block diagram of the clock subsystem. the qclk provides the timing for the a/d converter state machine which controls the timing of the conversion. the qclk is also the input to a 17-stage binary divider which implements the periodic/interval timer. to retain the specified analog conversion accuracy, the qclk frequency (f qclk ) must be within the tolerance specified in table 23-8. qadc conversion specifications (operating) . before using the qadc, the prescaler must be initialized with values that put the qclk within the specified range. though most applications initialize the prescaler once and do not change it, write operations to the prescaler fields are permitted. figure 19-42. qadc clock subsystem functions atd converter state machine 2 7 2 8 2 9 2 10 2 11 2 12 2 13 2 14 2 15 2 16 2 17 periodic timer/interval timer select binary counter queue 1 and queue 2 timer mode rate selection input sample time from ccw sar sar control periodic/interval trigger event for q1 and q2 prescaler system clock 2 8 10 2 qpr[6:0] f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . advance information mmc2114 MMC2113 mmc2112 ? rev. 1.0 504 queued analog-to-digital converter (qadc) motorola queued analog-to-digital converter (qadc) caution: a change in the prescaler value while a conversion is in progress is likely to corrupt the result. therefore, any prescaler write operation should be done only when both queues are in the disabled modes. to accommodate the wide range of the main mcu clock frequency, qclk is generated by a programmable prescaler which divides the mcu system clock. to allow the a/d conversion time to be maximized across the spectrum of system clock frequencies, the qadc prescaler permits the qclk frequency to be software selectable. the frequency of qclk is set with the qpr field in qacr0. the mcu system clock frequency is the basis of qadc timing. the qadc requires that the system clock frequency be at least twice the qclk frequency. 19.10.9 periodic/interval timer the qadc periodic/interval timer can be used to generate trigger events at a programmable interval, initiating execution of queue 1 and/or queue 2. the periodic/interval timer stays reset under these conditions: both queue 1 and queue 2 are programmed to any mode which does not use the periodic/interval timer. system reset is asserted. stop mode is enabled. debug mode is enabled. note: interval timer single-scan mode does not start the periodic/interval timer until the single-scan enable bit is set. these conditions will cause a pulsed reset of the periodic/interval timer during use: a queue 1 operating mode change to a mode which uses the periodic/interval timer, even if queue 2 is already using the timer a queue 2 operating mode change to a mode which uses the periodic/interval timer, provided queue 1 is not in a mode which uses the periodic/interval timer roll over of the timer f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . queued analog-to-digital converter (qadc) digital control mmc2114 MMC2113 mmc2112 ? rev. 1.0 advance information motorola queued analog-to-digital converter (qadc) 505 during stop mode, the periodic/interval timer is held in reset. because stop mode causes qacr1 and qacr2 to be reset to 0, a valid periodic or interval timer mode must be written after leaving stop mode to release the timer from reset. when qadc debug mode is entered and a periodic or interval timer mode is selected, the timer counter is reset after the conversion in progress completes. when the periodic or interval timer mode has been enabled (the timer is counting), but a trigger event has not been issued, debug mode takes effect immediately, and the timer is held in reset. removal of the qadc debug condition restarts the counter from the beginning. refer to 19.5.1 debug mode for more information. 19.10.10 conversion command word table the conversion command word (ccw) table is 64 half-word (128 byte) long ram with 10 bits of each entry implemented. the ccw table is written by the user and is not modified by the qadc. each ccw requests the conversion of one analog channel to a digital result. the ccw specifies the analog channel number, the input sample time, and whether the queue is to pause after the current ccw. the 10 implemented bits of the ccw can be read and written. the remaining six bits are unimplemented and read as 0s; write operations have no effect. each location in the ccw table corresponds to a location in the result word table. when a conversion is completed for a ccw entry, the 10-bit result is written in the corresponding result word entry. the beginning of queue 1 is the first location in the ccw table. the first location of queue 2 is specified by the beginning of queue 2 pointer field (bq2) in qacr2. to dedicate the entire ccw table to queue 1, place queue 2 in disabled mode and write bq2 to 64 or greater. to dedicate the entire ccw table to queue 2, place queue 1 in disabled mode and set bq2 to the first location in the ccw table (ccw0). figure 19-43 illustrates the operation of the queue structure. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . advance information mmc2114 MMC2113 mmc2112 ? rev. 1.0 506 queued analog-to-digital converter (qadc) motorola queued analog-to-digital converter (qadc) figure 19-43. qadc conversion queue operation to prepare the qadc for a scan sequence, write to the ccw table to specify the desired channel conversions. the criteria for queue execution is established by selecting the queue operating mode. the queue operating mode determines what type of trigger event starts queue execution. a trigger event refers to any of the ways that cause the qadc to begin executing the ccws in a queue or subqueue. an external trigger is only one of the possible trigger events. a scan sequence may be initiated by: a software command expiration of the periodic/interval timer an external trigger signal an external gated signal (queue 1 only) beginning of queue 1 00 channel select, sample, hold, a/d conversion conversion command result word table word (ccw) table 00 end of queue 1 beginning of queue 2 end of queue 2 63 63 byp p ist chan 8 9 [7:6] [5:0] p ? pause after conversion until next trigger byp ? bypass buffer amplifier ist ? input sample time chan ? channel number and end-of-queue code 10-bit conversion command word format 0 result [9:0] 10-bit result, readable in three 16-bit formats 0 0 0 0 0 15 14 13 12 11 10 0 result 0 0 0 0 0 right-justified, unsigned result left-justified, unsigned result left-justified, signed result 0 result 0 0 0 0 0 s [5:0] [5:0] [15:6] [15:6] f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . queued analog-to-digital converter (qadc) digital control mmc2114 MMC2113 mmc2112 ? rev. 1.0 advance information motorola queued analog-to-digital converter (qadc) 507 the queue can be scanned in single pass or continuous fashion. when a single-scan mode is selected, the scan must be engaged by setting the single-scan enable bit. when a continuous-scan mode is selected, the queue remains active in the selected queue operating mode after the qadc completes each queue scan sequence. during queue execution, the qadc reads each ccw from the active queue and executes conversions in three stages: initial sample final sample resolution during initial sample, a buffered version of the selected input channel is connected to the sample capacitor at the input of the sample buffer amplifier. during the final sample period, the sample buffer amplifier is bypassed, and the multiplexer input charges the sample capacitor directly. each ccw specifies a final input sample time of 2, 4, 8, or 16 qclk cycles. when an analog-to-digital conversion is complete, the result is written to the corresponding location in the result word table. the qadc continues to sequentially execute each ccw in the queue until the end of the queue is detected or a pause bit is found in a ccw. when the pause bit is set in the current ccw, the qadc stops execution of the queue until a new trigger event occurs. the pause status flag bit is set, and an interrupt may optionally be requested. after the trigger event occurs, the paused state ends, and the qadc continues to execute each ccw in the queue until another pause is encountered or the end of the queue is detected. an end-of-queue condition occurs when: the ccw channel field is programmed with 63 to specify the end of the queue. the end-of-queue 1 is implied by the beginning of queue 2, which is specified by the bq2 field in qacr2. the physical end of the queue ram space defines the end of either queue. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . advance information mmc2114 MMC2113 mmc2112 ? rev. 1.0 508 queued analog-to-digital converter (qadc) motorola queued analog-to-digital converter (qadc) when any of the end-of-queue conditions is recognized, a queue completion flag is set, and if enabled, an interrupt is requested. these situations prematurely terminate queue execution: queue 1 is higher in priority than queue 2. when a trigger event occurs on queue 1 during queue 2 execution, the execution of queue 2 is suspended by aborting the execution of the ccw in progress, and queue 1 execution begins. when queue 1 execution is complete, queue 2 conversions restart with the first ccw entry in queue 2 or the first ccw of the queue 2 subqueue being executed when queue 2 was suspended. alternately, conversions can restart with the aborted queue 2 ccw entry. the resume bit in qacr2 selects where queue 2 begins after suspension. by choosing to re-execute all of the suspended queue 2 ccws (resume = 0), all of the samples are guaranteed to have been taken during the same scan pass. however, a high trigger event rate for queue 1 can prevent completion of queue 2. if this occurs, execution of queue 2 can begin with the aborted ccw entry (resume = 1). any conversion in progress for a queue is aborted when that queue ? s operating mode is changed to disabled. putting a queue into the disabled mode does not power down the converter. changing a queue ? s operating mode to another valid mode aborts any conversion in progress. the queue restarts at its beginning once an appropriate trigger event occurs. for low-power operation, the stop bit can be set to prepare the module for a loss of clocks. the qadc aborts any conversion in progress when stop mode is entered. when the qadc debug bit is set and the cpu enters background debug mode, the qadc freezes at the end of the conversion in progress. after leaving debug mode, the qadc resumes queue execution beginning with the next ccw entry. refer to 19.5.1 debug mode for more information. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . queued analog-to-digital converter (qadc) pin connection considerations mmc2114 MMC2113 mmc2112 ? rev. 1.0 advance information motorola queued analog-to-digital converter (qadc) 509 19.10.11 result word table the result word table is a 64 half-word (128 byte) long by 10-bit wide ram. an entry is written by the qadc after completing an analog conversion specified by the corresponding ccw table entry. the result word table can be read or written, but in normal operation is only read to obtain analog conversions from the qadc. unimplemented bits read as 0s and writes have no effect. note: although the result ram can be written, some write operations, like bit manipulation, may not operate as expected because the hardware cannot access a true 16-bit value. while there is only one result word table, the half-word (16-bit) data can be accessed in three different data formats: right justified with 0s in the higher order unused bits left justified with the most significant bit inverted to form a sign bit, and 0s in the unused lower order bits left justified with 0s in the lower order unused bits the left justified, signed format corresponds to a half-scale, offset binary, two ? s complement data format. the address used to read the result table determines the data alignment format. all write operations to the result word table are right justified. 19.11 pin connection considerations the qadc requires accurate, noise-free input signals for proper operation. this section discusses the design of external circuitry to maximize qadc performance. 19.11.1 analog reference pins no a/d converter can be more accurate than its analog reference. any noise in the reference can result in at least that much error in a conversion. the reference for the qadc, supplied by pins v rh and v rl , should be low-pass filtered from its source to obtain a noise-free, clean signal. in many cases, simple capacitive bypassing may suffice. in f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . advance information mmc2114 MMC2113 mmc2112 ? rev. 1.0 510 queued analog-to-digital converter (qadc) motorola queued analog-to-digital converter (qadc) extreme cases, inductors or ferrite beads may be necessary if noise or rf energy is present. series resistance is not advisable, because there is an effective dc current required from the reference voltage by the internal resistor string in the rc dac array. external resistance may introduce error in this architecture under certain conditions. any series devices in the filter network should contain a minimum amount of dc resistance. for accurate conversion results, the analog reference voltages must be within the limits defined by v dda and v ssa , as explained in this subsection. 19.11.2 analog power pins the analog supply pins (v dda and v ssa ) define the limits of the analog reference voltages (v rh and v rl ) and of the analog multiplexer inputs. figure 19-44 is a diagram of the analog input circuitry. figure 19-44. equivalent analog input circuitry because the sample amplifier is powered by v dda and v ssa , it can accurately transfer input signal levels up to but not exceeding v dda and down to but not below v ssa . if the input signal is outside of this range, the output from the sample amplifier is clipped. sample amp 16 channels total v rl v dda v rh s/h rc dac comparator cp v ssa f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . queued analog-to-digital converter (qadc) pin connection considerations mmc2114 MMC2113 mmc2112 ? rev. 1.0 advance information motorola queued analog-to-digital converter (qadc) 511 in addition, v rh and v rl must be within the range defined by v dda and v ssa . as long as v rh is less than or equal to v dda , and v rl is greater than or equal to v ssa , and the sample amplifier has accurately transferred the input signal, resolution is ratiometric within the limits defined by v rl and v rh . if v rh is greater than v dda , the sample amplifier can never transfer a full-scale value. if v rl is less than v ssa , the sample amplifier can never transfer a 0 value. figure 19-45 shows the results of reference voltages outside the range defined by v dda and v ssa . at the top of the input signal range, v dda is 10 mv lower than v rh . this results in a maximum obtainable 10-bit conversion value 0x03fe. at the bottom of the signal range, v ssa is 15 mv higher than v rl , resulting in a minimum obtainable 10-bit conversion value of 0x0003. figure 19-45. errors resulting from clipping 0 .020 5.100 5.110 1 2 3 4 5 6 7 8 3fa 3fb 3fc 3fd 3fe 3ff .010 .030 5.120 5.130 10-bit result (hexadecimal) inputs in volts (v rh = 5.120 v, v rl = 0 v) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . advance information mmc2114 MMC2113 mmc2112 ? rev. 1.0 512 queued analog-to-digital converter (qadc) motorola queued analog-to-digital converter (qadc) 19.11.3 conversion timing schemes this section contains some conversion timing examples. figure 19-46 shows the timing for basic conversions where it is assumed that: q1 begins with ccw0 and ends with ccw3. ccw0 has pause bit set. ccw1 does not have pause bit set. external trigger rising edge for q1 ccw4 = bq2 and q2 is disabled. q1 res shows relative result register updates. recall that when qs = 0, both queues are disabled; when qs = 8, queue 1 is active and queue 2 is idle; and when qs = 4; queue 1 is paused and queue 2 is disabled. figure 19-46. external positive edge trigger mode timing with pause r1 last r0 ccw0 ccw1 ccw2 ccw1 conversion time time between qclk trig1 eoc qs cwp cwpq1 q1 res 0 last 8 4 8 ccw0 triggers = 14 qclks conversion time = 14 qclks f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . queued analog-to-digital converter (qadc) pin connection considerations mmc2114 MMC2113 mmc2112 ? rev. 1.0 advance information motorola queued analog-to-digital converter (qadc) 513 a time separator is provided between the triggers and the end of conversion (eoc). the relationship to qclk displayed is not guaranteed. cwpq1 and cwpq2 typically lag cwp and only match cwp when the associated queue is inactive. another way to view cwpq1 and cwpq2 is that these registers update when eoc triggers the write to the result register. for the ccw with the pause bit set (ccw0), cwp does not increment until triggered. for the ccw with the pause bit clear (ccw1), the cwp increments with the eoc. the conversion results q1 resx show the result associated with ccwx, such that r0 represents the result associated with ccw0. figure 19-47 shows the timing for conversions in externally gated single-scan with same assumptions in example 1 except: no pause bits set in any ccw externally gated single scan mode for q1 single scan enable bit (sse1) is set. when the gate closes and opens again, the conversions start with the first ccw in q1. when the gate closes, the active conversion completes before the queue goes idle. when q1 completes, both the cf1 bit sets and the sse bit clears. in this mode, the pf1 bit sets to reflect that a gate closing occurred before the queue completed. figure 19-48 shows the timing for conversions in externally gated continuous scan mode with the same assumptions as in figure 19-47 . at the end of q1,the completion flag cf1 sets and the queue restarts. if the queue starts a second time and completes, the trigger overrun flag tor1 sets. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . advance information mmc2114 MMC2113 mmc2112 ? rev. 1.0 514 queued analog-to-digital converter (qadc) motorola queued analog-to-digital converter (qadc) figure 19-47. gated mode, single scan timing figure 19-48. gated mode, continuous scan timing 08 0 8 0 ccw3 ccw2 ccw1 ccw0 last ccw0 ccw1 r3 r2 r1 r0 last r0 r1 trig1 (gate) eoc qs cwp cwpq1 q1 res sse cf1 pf1 last ccw0 ccw1 ccw1 ccw0 ccw2 ccw3 eoc qs cwp cspq1 q1 res cf1 ccw0 ccw3 ccw0 ccw3 ccw2 ccw1 ccw0 last last ccw0 ccw1 ccw2 ccw3 last r0 r1 r2 r3 r2 ccw2 xx 08 queue restart queue restart tor1 ccw3 r3 trig1 (gate) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . queued analog-to-digital converter (qadc) pin connection considerations mmc2114 MMC2113 mmc2112 ? rev. 1.0 advance information motorola queued analog-to-digital converter (qadc) 515 19.11.4 analog supply filtering and grounding two important factors influencing performance in analog integrated circuits are supply filtering and grounding. generally, digital circuits use bypass capacitors on every v dd /v ss pin pair. this applies to analog subsystems and submodules also. equally important as bypassing is the distribution of power and ground. analog supplies should be isolated from digital supplies as much as possible. this necessity stems from the higher performance requirements often associated with analog circuits. therefore, deriving an analog supply from a local digital supply is not recommended. however, if for cost reasons digital and analog power are derived from a common regulator, filtering of the analog power is recommended in addition to the bypassing of the supplies already mentioned. for example, an rc low pass filter could be used to isolate the digital and analog supplies when generated by a common regulator. if multiple high precision analog circuits are locally employed (for example, two a/d converters), the analog supplies should be isolated from each other as sharing supplies introduces the potential for interference between analog circuits. grounding is the most important factor influencing analog circuit performance in mixed signal systems (or in standalone analog systems). close attention must be paid not to introduce additional sources of noise into the analog circuitry. common sources of noise include ground loops, inductive coupling, and combining digital and analog grounds together inappropriately. the problem of how and when to combine digital and analog grounds arises from the large transients which the digital ground must handle. if the digital ground is not able to handle the large transients, the associated current can return to ground through the analog ground. it is this excess current overflowing into the analog ground which causes performance degradation by developing a differential voltage between the true analog ground and the microcontroller ? s ground pins. the end result is that the ground observed by the analog circuit is no longer true ground and thus skews converter performance. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . advance information mmc2114 MMC2113 mmc2112 ? rev. 1.0 516 queued analog-to-digital converter (qadc) motorola queued analog-to-digital converter (qadc) two similar approaches to improving or eliminating the problems associated with grounding excess transient currents involve star-point ground systems. one approach is to star-point the different grounds at the power supply origin, thus keeping the ground isolated. refer to figure 19-49 . another approach is to star-point the different grounds near the analog ground pin on the microcontroller by using small traces for connecting the non-analog grounds to the analog ground. the small traces are meant only to accommodate dc differences, not ac transients. note: this star-point scheme still requires adequate grounding for digital and analog subsystems in addition to the star-point ground. figure 19-49. star-ground at the point of power supply origin qadc v rh v rl v ssa v dda v dd v ss analog power supply +5 v +5 v agnd digital power supply +5 v pgnd pcb f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . queued analog-to-digital converter (qadc) pin connection considerations mmc2114 MMC2113 mmc2112 ? rev. 1.0 advance information motorola queued analog-to-digital converter (qadc) 517 other suggestions for pcb layout in which the qadc is employed include: analog ground must be low impedance to all analog ground points in the circuit. bypass capacitors should be as close to the power pins as possible. the analog ground should be isolated from the digital ground. this can be done by cutting a separate ground plane for the analog ground. non-minimum traces should be utilized for connecting bypass capacitors and filters to their corresponding ground/power points. minimum distance for trace runs when possible. 19.11.5 accommodating positive/negative stress conditions positive or negative stress refers to conditions which exceed nominally defined operating limits. examples include applying a voltage exceeding the normal limit on an input (for example, voltages outside of the suggested supply/reference ranges) or causing currents into or out of the pin which exceed normal limits. qadc specific considerations are voltages greater than v dda or less than v ssa applied to an analog input which cause excessive currents into or out of the input. refer to table 23-6. qadc absolute maximum ratings and table 23-7. qadc electrical specifications (operating) for more information on exact magnitudes. either stress conditions can potentially disrupt conversion results on neighboring inputs. parasitic devices, associated with cmos processes, can cause an immediate disruptive influence on neighboring pins. common examples of parasitic devices are diodes to substrate and bipolar devices with the base terminal tied to substrate (v ss /v ssa ground). under stress conditions, current injected on an adjacent pin can cause errors on the selected channel by developing a voltage drop across the selected channel ? s impedances. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . advance information mmc2114 MMC2113 mmc2112 ? rev. 1.0 518 queued analog-to-digital converter (qadc) motorola queued analog-to-digital converter (qadc) figure 19-50 shows an active parasitic bipolar npn transistor when an input pin is subjected to negative stress conditions. figure 19-51 shows positive stress conditions can activate a similar pnp transistor. figure 19-50. input pin subjected to negative stress figure 19-51. input pin subjected to positive stress the current into the pin (i injn or i injp ) under negative or positive stress is determined by these equations: where: v stress = adjustable voltage source v eb = parasitic pnp emitter/base voltage v be = parasitic npn base/emitter voltage r stress = source impedance (10 k ? resistor in figure 19-50 and figure 19-51 on stressed channel) r selected = source impedance on channel selected for conversion r stress r selected adjacent 10 k ? pin under parasitic i injn i in + stress v stress device pin v in an n an n+1 r stress r selected adjacent 10 k ? pin under parasitic i injp i in + stress v stress device pin v in v dda an n an n+1 i injn v stress v be ? () ? r stress ----------------------------------------------- = i injp v stress v eb ? v dda ? r stress -------------------------------------------------------------- - = f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . queued analog-to-digital converter (qadc) pin connection considerations mmc2114 MMC2113 mmc2112 ? rev. 1.0 advance information motorola queued analog-to-digital converter (qadc) 519 the current into (i in ) the neighboring pin is determined by the k n (current coupling ratio) of the parasitic bipolar transistor (k n ?? 1). the i in can be expressed by this equation: i in = ? k n * i inj where: i inj is either i injn or i injp . a method for minimizing the impact of stress conditions on the qadc is to strategically allocate qadc inputs so that the lower accuracy inputs are adjacent to the inputs most likely to see stress conditions. also, suitable source impedances should be selected to meet design goals and minimize the effect of stress conditions. 19.11.6 analog input considerations the source impedance of the analog signal to be measured and any intermediate filtering should be considered whether external multiplexing is used or not. figure 19-52 shows the connection of eight typical analog signal sources to one qadc analog input pin through a separate multiplexer chip. also, an example of an analog signal source connected directly to a qadc analog input channel is displayed. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . advance information mmc2114 MMC2113 mmc2112 ? rev. 1.0 520 queued analog-to-digital converter (qadc) motorola queued analog-to-digital converter (qadc) figure 19-52. external multiplexing of analog signal sources c p c samp c p c samp c in = c p + c samp r muxout r source 2 analog signal source filtering and interconnect typical mux chip interconnect qadc ~ c filter c source r filter 2 c muxin 0.01 f 1 c muxout (mc54hc4051, mc74hc4051, mc54hc4052, mc74hc4052, mc54hc4053, etc.) r source 2 c filter c source r filter 2 c muxin 0.01 f 1 r source 2 c filter c source r filter 2 c muxin 0.01 f 1 r source 2 c filter c source r filter 2 c muxin 0.01 f 1 r source 2 c filter c source r filter 2 c muxin 0.01 f 1 r source 2 c filter c source r filter 2 c muxin 0.01 f 1 r source 2 c filter c source r filter 2 c muxin 0.01 f 1 r source 2 c filter c source r filter 2 c muxin 0.01 f 1 c filter r filter 2 0.01 f 1 1. typical value 2. r filter , typically 10 k ? ? 20 k ? notes: r source 2 c source c pcb c pcb ~ ~ ~ ~ ~ ~ ~ ~ f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . queued analog-to-digital converter (qadc) pin connection considerations mmc2114 MMC2113 mmc2112 ? rev. 1.0 advance information motorola queued analog-to-digital converter (qadc) 521 19.11.7 analog input pins analog inputs should have low ac impedance at the pins. low ac impedance can be realized by placing a capacitor with good high frequency characteristics at the input pin of the part. ideally, that capacitor should be as large as possible (within the practical range of capacitors that still have good high-frequency characteristics). this capacitor has two effects: it helps attenuate any noise that may exist on the input. it sources charge during the sample period when the analog signal source is a high-impedance source. series resistance can be used with the capacitor on an input pin to implement a simple rc filter. the maximum level of filtering at the input pins is application dependent and is based on the bandpass characteristics required to accurately track the dynamic characteristics of an input. simple rc filtering at the pin may be limited by the source impedance of the transducer or circuit supplying the analog signal to be measured. (see 19.11.7.2 error resulting from leakage .) in some cases, the size of the capacitor at the pin may be very small. figure 19-53 is a simplified model of an input channel. refer to this model in the following discussion of the interaction between the external circuitry and the circuitry inside the qadc. figure 19-53. electrical model of an a/d input pin s1 amp r f s3 c samp v i c p c f v src internal circuit model external filter v src = source voltage = internal parasitic capacitance r f c f c p c samp = sample capacitor v i = filter impedance = filter capacitor = internal voltage source during sample and hold source r src r src = source impedance s2 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . advance information mmc2114 MMC2113 mmc2112 ? rev. 1.0 522 queued analog-to-digital converter (qadc) motorola queued analog-to-digital converter (qadc) in figure 19-53 , r f , r src , and c f comprise the external filter circuit. c p is the internal parasitic capacitor. c samp is the capacitor array used to sample and hold the input voltage. v i is an internal voltage source used to provide charge to c samp during sample phase. the following paragraphs provide a simplified description of the interaction between the qadc and the user ? s external circuitry. this circuitry is assumed to be a simple rc low-pass filter passing a signal from a source to the qadc input pin. these simplifying assumptions are made: the external capacitor is perfect (no leakage, no significant dielectric absorption characteristics, etc.). all parasitic capacitance associated with the input pin is included in the value of the external capacitor. inductance is ignored. the "on" resistance of the internal switches is 0 ohms and the "off" resistance is infinite. 19.11.7.1 settling time for the external circuit the values for r src , r f , and c f in the user's external circuitry determine the length of time required to charge c f to the source voltage level (v src ). at time t = 0, v src changes in figure 19-53 while s1 is open, disconnecting the internal circuitry from the external circuitry. assume that the initial voltage across c f is 0. as c f charges, the voltage across it is determined by the equation, where t is the total charge time: as t approaches infinity, v cf will equal v src . (this assumes no internal leakage.) with 10-bit resolution, 1/2 of a count is equal to 1/2048 full-scale value. assuming worst case (v src = full scale), table 19-14 shows the required time for c f to charge to within 1/2 of a count of the actual source voltage during 10-bit conversions. table 19-14 is based on the rc network in figure 19-53 . note: the following times are completely independent of the a/d converter architecture (assuming the qadc is not affecting the charging). v cf = v src (1 ? e ? t/(r f + r src ) c f ) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . queued analog-to-digital converter (qadc) pin connection considerations mmc2114 MMC2113 mmc2112 ? rev. 1.0 advance information motorola queued analog-to-digital converter (qadc) 523 the external circuit described in table 19-14 is a low-pass filter. measurements of an ac component of the external signal must take the characteristics of this filter into account. 19.11.7.2 error resulting from leakage a series resistor limits the current to a pin therefore, input leakage acting through a large source impedance can degrade a/d accuracy. the maximum input leakage current is specified in table 23-7. qadc electrical specifications (operating) . input leakage is greater at higher operating temperatures. in the temperature range from 125 c to 50 c, the leakage current is halved for every 8 c to 12 c reduction in temperature. assuming v rh ? v rl = 5.12 v, 1 count (with 10-bit resolution) corresponds to 5 mv of input voltage. a typical input leakage of 200 na acting through 10 k ? of external series resistance results in an error of 0.4 count (2.0 mv). if the source impedance is 100 k ? and a typical leakage of 100 na is present, an error of 2 counts (10 mv) is introduced. in addition to internal junction leakage, external leakage (for example, if external clamping diodes are used) and charge sharing effects with internal capacitors also contribute to the total leakage current. table 19-15 illustrates the effect of different levels of total leakage on accuracy for different values of source impedance. the error is listed in terms of 10-bit counts. table 19-14. external circuit settling time to 1/2 lsb filter capacitor (c f ) source resistance (r f + r src ) 100 ? ? ? ? 1 f 760 s 7.6 ms 76 ms 760 ms 0.1 f76 s 760 s 7.6 ms 76 ms 0.01 f7.6 s76 s 760 s7.6 ms 0.001 f 760 ns 7.6 s 76 s 760 s 100 pf 76 ns 760 ns 7.6 s 76 s f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . advance information mmc2114 MMC2113 mmc2112 ? rev. 1.0 524 queued analog-to-digital converter (qadc) motorola queued analog-to-digital converter (qadc) caution: leakage below 200 na is obtainable only within a limited temperature range. 19.12 interrupts the four interrupt lines are outputs of the module and have no priority or arbitration within the module. 19.12.1 interrupt operation qadc inputs can be monitored by polling or by using interrupts. when interrupts are not needed, the completion flag and the pause flag for each queue can be monitored in the status register (qasr0). in other words, flag bits can be polled to determine when new results are available. table 19-16 shows the status flag and interrupt enable bits which correspond to queue 1 and queue 2 activity. table 19-15. error resulting from input leakage (i off ) source impedance leakage value (10-bit conversions) 100 na 200 na 500 na 1000 na 1 k ? ?? 0.1 counts 0.2 counts 10 k ? 0.2 counts 0.4 counts 1 counts 2 counts 100 k ? 2 counts 4 count 10 counts 20 counts table 19-16. qadc status flags and interrupt sources queue queue activity status flag interrupt enable bit queue 1 result written for last ccw in queue 1 cf1 cie1 result written for a ccw with pause bit set in queue 1 pf1 pie1 queue 2 result written for last ccw in queue 2 cf2 cie2 result written for a ccw with pause bit set in queue 2 pf2 pie2 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . queued analog-to-digital converter (qadc) interrupts mmc2114 MMC2113 mmc2112 ? rev. 1.0 advance information motorola queued analog-to-digital converter (qadc) 525 if interrupts are enabled for an event, the qadc requests interrupt service when the event occurs. using interrupts does not require continuously polling the status flags to see if an event has taken place; however, status flags must be cleared after an interrupt is serviced, in order to remove the interrupt request in both polled and interrupt-driven operating modes, status flags must be re-enabled after an event occurs. flags are re-enabled by clearing the appropriate qasr0 bits in a particular sequence. qasr0 must first be read, then 0s must be written to the flags that are to be cleared. if a new event occurs between the time that the register is read and the time that it is written, the associated flag is not cleared. 19.12.2 interrupt sources the qadc includes four sources of interrupt requests, each of which is separately enabled. each time the result is written for the last conversion command word (ccw) in a queue, the completion flag for the corresponding queue is set, and when enabled, an interrupt is requested. in the same way, each time the result is written for a ccw with the pause bit set, the queue pause flag is set, and when enabled, an interrupt is requested. refer to table 19-16 . the pause and complete interrupts for queue 1 and queue 2 have separate interrupt vector levels, so that each source can be separately serviced. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . advance information mmc2114 MMC2113 mmc2112 ? rev. 1.0 526 queued analog-to-digital converter (qadc) motorola queued analog-to-digital converter (qadc) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . mmc2114 MMC2113 mmc2112 ? rev. 1.0 advance information motorola external bus interface module (ebi) 527 advance information ? mmc2114, MMC2113, and mmc2112 section 20. external bus interface module (ebi) 20.1 contents 20.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .528 20.3 signal descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .529 20.3.1 data bus (d[31:0]) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .530 20.3.2 show cycle strobe (shs ) . . . . . . . . . . . . . . . . . . . . . . . . .530 20.3.3 transfer acknowledge (ta ) . . . . . . . . . . . . . . . . . . . . . . . .530 20.3.4 transfer error acknowledge (tea ) . . . . . . . . . . . . . . . . . .530 20.3.5 emulation mode chip selects (cse[1:0]) . . . . . . . . . . . . .530 20.3.6 transfer code (tc[2:0]) . . . . . . . . . . . . . . . . . . . . . . . . . . .531 20.3.7 read/write (r/w ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .531 20.3.8 address bus (a[22:0]) . . . . . . . . . . . . . . . . . . . . . . . . . . . .531 20.3.9 enable byte (eb [3:0] ). . . . . . . . . . . . . . . . . . . . . . . . . . . . .531 20.3.10 chip selects (cs [3:0] ) . . . . . . . . . . . . . . . . . . . . . . . . . . . .531 20.3.11 output enable (oe ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .531 20.3.12 transfer size (tsiz[1:0]) . . . . . . . . . . . . . . . . . . . . . . . . . .532 20.3.13 processor status (pstat[3:0]) . . . . . . . . . . . . . . . . . . . . .532 20.4 memory map and registers . . . . . . . . . . . . . . . . . . . . . . . . . .532 20.5 operand transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .532 20.6 enable byte pins (eb[3:0] ) . . . . . . . . . . . . . . . . . . . . . . . . . . .534 20.7 bus master cycles . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 534 20.7.1 read cycles . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 535 20.7.1.1 state 1 (x1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .536 20.7.1.2 optional wait states (x2w) . . . . . . . . . . . . . . . . . . . . . .536 20.7.1.3 state 2 (x2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .536 20.7.2 write cycles . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 537 20.7.2.1 state 1 (x1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .538 20.7.2.2 optional wait states (x2w) . . . . . . . . . . . . . . . . . . . . . .538 20.7.2.3 state 2 (x2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .538 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . advance information mmc2114 MMC2113 mmc2112 ? rev. 1.0 528 external bus interface module (ebi) motorola external bus interface module (ebi) 20.8 bus exception operation . . . . . . . . . . . . . . . . . . . . . . . . . . . .540 20.8.1 transfer error termination . . . . . . . . . . . . . . . . . . . . . . . . .540 20.8.2 transfer abort termination . . . . . . . . . . . . . . . . . . . . . . . .540 20.9 emulation support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .540 20.9.1 emulation chip-selects (cse[1:0]) . . . . . . . . . . . . . . . . . .540 20.9.2 internal data transfer display (show cycles) . . . . . . . . . .541 20.9.3 show strobe (shs ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .542 20.9.4 transfer code (tc[2:0]) . . . . . . . . . . . . . . . . . . . . . . . . . . .543 20.9.5 processor status (pstat) . . . . . . . . . . . . . . . . . . . . . . . . .543 20.10 bus monitor. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .545 20.11 interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .545 20.2 introduction the external bus interface (ebi) module is responsible for controlling the transfer of information between the internal m core local bus and external address space. the external bus has 23 address lines and 32 data lines. in master mode and emulation mode, the ebi functions as a bus master and allows internal bus cycles to access external resources. in single-chip mode, the ebi is active, but the external data bus is not available, and no external data or termination signals are transferred to the internal bus. the ebi supports data transfers to both 32-bit and 16-bit ports. chip-select channels are programmed to define the port size for specific address ranges. when no chip-select is active during an external data transfer, the port size is defaults to 32 bits. the ebi supports a variable length external bus cycle to accommodate the access speed of any device. during an external data transfer, the ebi drives the address pins, byte enable pins, output enable pins, size pins, and read/write pins. wait states are inserted until the bus cycle is terminated by the assertion of the internal transfer acknowledge signal by a chip-select channel or by the assertion of the external ta or tea pins. the minimum external bus cycle is one clock. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . external bus interface module (ebi) signal descriptions mmc2114 MMC2113 mmc2112 ? rev. 1.0 advance information motorola external bus interface module (ebi) 529 the ebi may drive the address, size, and read/write pins during internal data transfers if show cycles is enabled, but the output enable and byte enable pins are not asserted. only internal sources can terminate internal data transfers. chip-select channels, external ta assertion, and external tea assertion cannot terminate internal data transfers. 20.3 signal descriptions table 20-1 provides an overview of the signal properties which are discussed in this subsection. table 20-1. signal properties name port function pullup d[31:0] pa, pb, pc, pd data bus ? shs pe7 show cycle strobe active ta pe6 transfer acknowledge active tea pe5 transfer error acknowledge active cse[1:0] pe[4:3] emulation chip selects active tc[2:0] pe[2:0] transfer code active r/w pf7 read/write active a[22:0] pf[6:0], pg, ph address bus active eb[3:0] pi[7:4] enable byte active cs [3:0] pi[3:0] chip selects active oe ? output enable ? tsiz[1:0] ? transfer size ? pstat[3:0] ? processor status ? f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . advance information mmc2114 MMC2113 mmc2112 ? rev. 1.0 530 external bus interface module (ebi) motorola external bus interface module (ebi) 20.3.1 data bus (d[31:0]) the three-state bidirectional data bus (d[31:0]) signals are the general-purpose data path between the microcontroller unit (mcu) and all other devices. 20.3.2 show cycle strobe (shs ) in master and emulation modes, show cycle strobe (shs ) is the strobe for capturing address, controls, and data during show cycles. in master mode this default functionality can be overridden to make the pin function as digital i/o. see 12.4.2.6 port e pin assignment register and table 12-3. ports a ? i supported pin functions . in single-chip mode, the shs pin is configured as digital i/o (pe7) by default. 20.3.3 transfer acknowledge (ta ) the transfer acknowledge (ta ) signal indicates that the external data transfer is complete. during a read cycle, when the processor recognizes ta , it latches the data and then terminates the bus cycle. during a write cycle, when the processor recognizes ta , the bus cycle is terminated. ta is an input in master and emulation modes. in single-chip mode, the ta pin is configured as digital i/o (pe6) by default. 20.3.4 transfer error acknowledge (tea ) the transfer error acknowledge (tea ) indicates an error condition exists for the bus transfer. the bus cycle is terminated and the cpu begins execution of the access error exception. tea is an input in master and emulation modes. in single-chip mode the tea pin is configured a digital i/o (pe5) by default. 20.3.5 emulation mode chip selects (cse[1:0]) the emulation mode chip select (cse[1:0]) output signals provide information for development support. in single-chip mode and master mode, these pins are configured as digital i/o (pe4 and pe3) by default. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . external bus interface module (ebi) signal descriptions mmc2114 MMC2113 mmc2112 ? rev. 1.0 advance information motorola external bus interface module (ebi) 531 20.3.6 transfer code (tc[2:0]) the transfer code (tc[2:0]) output signals indicate the data transfer code for the current bus cycle. see 20.9.4 transfer code (tc[2:0]) for codes. in single-chip mode and master mode, these pins are configured as digital i/o (pe2, pe1, pe0) by default. 20.3.7 read/write (r/w ) the read/write (r/w ) output signal indicates the direction of the data transfer on the bus. a logic 1 indicates a read from a slave device and a logic 0 indicates a write to a slave device. 20.3.8 address bus (a[22:0]) the address bus (a[22:0]) output signals provide the address for the current bus transfer. 20.3.9 enable byte (eb [3:0]) the enable byte (eb [3:0]) output signals indicate which byte of data is valid during external cycles. 20.3.10 chip selects (cs [3:0]) the chip select (cs [3:0]) output signals select external devices for external bus transactions. 20.3.11 output enable (oe ) the output enable (oe ) signal indicates when an external device can drive data during external read cycles. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . advance information mmc2114 MMC2113 mmc2112 ? rev. 1.0 532 external bus interface module (ebi) motorola external bus interface module (ebi) 20.3.12 transfer size (tsiz[1:0]) tsiz[1:0] provides an indication of the m core transfer size. see table 20-2 . this function is enabled by default in master mode and emulation mode, and disabled by default in single-chip mode. selection of this function is through the chip configuration register (see 4.7.3.1 chip configuration register ). when this feature is disabled, these pins act as pins int7 and int6 of the eport module. 20.3.13 processor status (pstat[3:0]) pstat[3:0] provides an indication of the m core processor status. see table 20-6 for status indication codes. this function is enabled by default in emulation mode, and disabled by default in master mode and single-chip mode. selection of this function is through the chip configuration register. when this feature is disabled, these pins act as pins int5, int4, int3, and int2 of the eport module. 20.4 memory map and registers the ebi is not memory-mapped and has no software-accessible registers. 20.5 operand transfer the possible operand accesses for the internal m core bus are: byte aligned upper half-word aligned lower half-word aligned word no misaligned transfers are supported. the ebi controls the byte, half-word, or word operand transfers between the m core bus and a 16-bit or 32-bit port. ? port ? refers to the width of the data path that an external device uses during a data transfer. each port is assigned to f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . external bus interface module (ebi) operand transfer mmc2114 MMC2113 mmc2112 ? rev. 1.0 advance information motorola external bus interface module (ebi) 533 particular bits of the data bus. a 16-bit port is assigned to pins d[31:16] and a 32-bit port is assigned to pins d[31:0]. table 20-2 shows each possible transfer size, alignment, and port width. the data bytes shown in the table represent external data pins. this data is multiplexed and driven to the external data bus as shown. the bytes labeled with a dash are not required; the m core will ignore them on read transfers, and drive them with undefined data on write transfers. in the case of a word (32-bit) access to a 16-bit port, the ebi runs two external bus cycles to complete the transfer. during the first external bus cycle, the a[1:0] pins are driven low, and the tsiz[1:0] pins are driven to indicate word size. during the second cycle, a1 is driven high to table 20-2. data transfer cases transfer size port width external pins data bus transfer tsiz1 tsiz0 a1 a0 byte 16 01 00 d[31:24] ??? 32 d[31:24] ??? 16 01 ? d[23:16] ?? 32 ? d[23:16] ?? 16 10 ?? d[31:24] ? 32 ?? d[15:8] ? 16 11 ??? d[23:16] 32 ??? d[7:0] half-word 16 10 00 d[31:24] d[23:16] ?? 32 d[31:24] d[23:16] ?? 16 10 ?? d[31:24] d[23:16] 32 ?? d[15:8] d[7:0] word 16 (1) 1. the ebi runs two cycles for word accesses to 16-bit ports. the table shows the data place- ment for both bus cycles. 0 0 0 0 d[31:24] d[23:16] ?? 110 ?? d[31:24] d[23:16] 32 0 0 0 d[31:24] d[23:16] d[15:8] d[7:0] f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . advance information mmc2114 MMC2113 mmc2112 ? rev. 1.0 534 external bus interface module (ebi) motorola external bus interface module (ebi) increment the external address by two bytes, a0 is still driven low, and the tsiz[1:0] pins are driven to indicate half-word size. during any word-size transfer, the ebi always drives the a[1:0] pins low during a word transfer (except on the second cycle of a word to half-word port transfer in which a1 is incremented). 20.6 enable byte pins (eb[3:0] ) the enable byte pins (eb[3:0] ) are configurable as byte enables for read and write cycles, or as write enables for write cycles only. the default function is byte enable unless there is an active chip-select match with the we bit set. in all external cycles when one or more eb pins are asserted, the encoding corresponds to the external data pins to be used for the transfer as outlined in table 20-3 . 20.7 bus master cycles in this subsection, each ebi bus cycle type is defined in terms of actions associated with a succession of internal states. read or write operations may require multiple bus cycles to complete based on the operand size and target port size. refer to 20.5 operand transfer for more information. in the discussion that follows, it is assumed that only a single bus cycle is required for a transfer. in the waveform diagrams ( figure 20-3 through figure 20-6 ), data transfers are related to clock cycles, independent of the clock frequency. the external bus states are also noted. table 20-3. eb[3:0] assertion encoding eb pin external data pins eb0 d[31:24] eb1 d[23:16] eb2 d[15:8] eb3 d[7:0] f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . external bus interface module (ebi) bus master cycles mmc2114 MMC2113 mmc2112 ? rev. 1.0 advance information motorola external bus interface module (ebi) 535 20.7.1 read cycles during a read cycle, the ebi receives data from an external memory or peripheral device. during external read cycles, the oe pin is asserted regardless of operand size. see figure 20-1 . also see figure 20-3 and figure 20-4 for read cycle timing diagrams with and without wait states. figure 20-1. read cycle flowchart 1. set r/w to read. 2. drive address on a[22:0]. 3. drive tsiz[1:0] pins for operand size. 4. assert cs if used. 1. receive cs . 2. decode address. 3. put data on d[31:16] and/or d[15:0]. 4. assert ta if necessary from slave device. 1. receive data from d[31:16] and/or d[15:0]. 2. drive data to internal data bus. 3. negate oe and eb . 1. remove data from d[31:16] and/or d[15:0]. 2. negate ta . 1. negate eb and cs if used. present data address device acquire data terminate cycle terminate cycle 5. assert oe and eb if used. mmc2114, MMC2113, and mmc2112 external peripheral start next cycle f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . advance information mmc2114 MMC2113 mmc2112 ? rev. 1.0 536 external bus interface module (ebi) motorola external bus interface module (ebi) 20.7.1.1 state 1 (x1) the ebi drives the address bus. r/w is driven high to indicate a read cycle. the tsiz[1:0] pins are driven to indicate the number of bytes in the transfer. tc[2:0] pins are driven to indicate the type of access. cs may be asserted to drive a device. later in state 1, oe is asserted. if the eb pins are not configured as write enables for this cycle, one or more eb pins are also asserted, depending on the size and position of the data to be transferred. if either the external ta pin or internal chip-select transfer acknowledge signal is asserted before the end of state 1, the ebi proceeds to state 2. 20.7.1.2 optional wait states (x2w) wait states are inserted until the slave asserts the ta pin or the internal chip-select transfer acknowledge signal is asserted. wait states are counted in full clocks. 20.7.1.3 state 2 (x2) one-half clock later in state 2, the selected device puts its information on d[31:16] and/or d[15:0]. one or both half-words of the external data bus are driven to the internal data bus. the address bus, r/w , cs , oe , eb , tc, and tsiz pins remain valid through state 2 to allow for static memory operation and signal skew. the slave device asserts data until it detects the negation of oe , after which it must remove its data within one-half state. note that the data bus may not become free until state 1. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . external bus interface module (ebi) bus master cycles mmc2114 MMC2113 mmc2112 ? rev. 1.0 advance information motorola external bus interface module (ebi) 537 20.7.2 write cycles on a write cycle, the ebi transfers data to an external memory or peripheral device. see figure 20-2 . also see figure 20-3 and figure 20-4 for write cycle timing diagrams with and without wait states. figure 20-2. write cycle flowchart 1. drive address on a[22:0]. 2. drive tsiz[1:0] pins for operand size. 3. assert cs if used. 4. clear r/w to write. 1. receive cs . 2. decode address. 3. receive data from d[31:16] and/or d[15:0]. 4. assert ta if necessary from slave device. 1. negate eb . 1. negate ta . 1. negate cs if used. accept data address device terminate output transfer terminate cycle terminate cycle 5. assert eb (one or more depending on data size and position. 6. drive data on d[31:16] and/or d[15:0]. 2. remove data from d[31:16] and/or d[15:0]. mmc2114, MMC2113, and mmc2112 external peripheral start next cycle f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . advance information mmc2114 MMC2113 mmc2112 ? rev. 1.0 538 external bus interface module (ebi) motorola external bus interface module (ebi) 20.7.2.1 state 1 (x1) the ebi drives the address bus. the tsiz[1:0] pins are driven to indicate the number of bytes in the transfer. tc[2:0] pins are driven to indicate the type of access. cs may be asserted to drive a device. oe is negated. later in state 1, r/w is driven low indicating a write cycle. one or more eb pins are asserted, depending on the size and position of the data to be transferred. if either the external ta pin or internal chip-select transfer acknowledge signal is asserted before the end of state 1, the ebi proceeds to state 2. 20.7.2.2 optional wait states (x2w) wait states are inserted until the slave asserts the ta pin or the internal chip-select transfer acknowledge signal is asserted. the ebi drives its data onto data bus lines d[31:16] and/or d[15:0] on the first optional wait state. wait states are counted in full clocks. 20.7.2.3 state 2 (x2) if the data was not already driven during optional wait states, the ebi drives its data onto d[31:16] and/or d[15:0] in state 2. eb is negated by the end of state 2. the address bus, data bus, r/w , cs , tc[2:0], and tsiz[1:0] pins remain valid through state 2 to allow for static memory operation and signal skew. figure 20-3 and figure 20-4 illustrate external bus master cycles with and without wait states and show m core bus activity. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . external bus interface module (ebi) bus master cycles mmc2114 MMC2113 mmc2112 ? rev. 1.0 advance information motorola external bus interface module (ebi) 539 figure 20-3. master mode ? 1-clock read and write cycle figure 20-4. master mode ? 2-clock read and write cycle clkout cs r/w a[22:0], tsiz[1:0] d[31:0] d1 d2 a2 ta , tea read write a1 oe eb[3:0] x1 x2 x1 x2 eb[3:0] (eb set as write enable) clkout cs r/w a[22:0], tsiz[1:0] d[31:0] d1 d2 a2 ta , tea read write a1 oe eb[3:0] (eb set as write enable) x1 x2 x2w x2 x1 x2 x2w x2 eb[3:0] f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . advance information mmc2114 MMC2113 mmc2112 ? rev. 1.0 540 external bus interface module (ebi) motorola external bus interface module (ebi) 20.8 bus exception operation 20.8.1 transfer error termination normal bus cycle termination requires the assertion of the ta pin or the internal transfer acknowledge signal. minimal bus exception support is provided by transfer error cycle termination. for transfer error cycle termination, the external tea pin or the internal transfer error acknowledge signal is asserted. transfer error cycle termination takes precedence over normal cycle termination, provided tea assertion meets its timing constraints. the internal bus monitor will assert the internal transfer error acknowledge signal when ta response time is too long, based upon the bmt[1:0] settings in the chip configuration registers (ccr). see 4.7.3.1 chip configuration register . 20.8.2 transfer abort termination external bus cycles which are aborted by the m core, still have the address, r/w , tc[2:0], tsiz[1:0], cs (if used), oe (reads only), and shs (if used) driven to the external pins. 20.9 emulation support 20.9.1 emulation chip-selects (cse[1:0]) while in emulation mode or master mode, special emulator chip-selects (cse[1:0]) are driven externally to allow internal/external accesses to be tracked by external hardware see table 20-4 . in emulation mode, all port registers are mapped externally. cse[1:0] = 10 whenever any emulated port registers are addressed. the lower bits of the address bus indicate the register accessed within the block. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . external bus interface module (ebi) emulation support mmc2114 MMC2113 mmc2112 ? rev. 1.0 advance information motorola external bus interface module (ebi) 541 accesses to the address space which contains the registers for the internal modules (except ports) are indicated by cse[1:0] = 11. internal accesses, other than to the specific module control registers, are indicated by cse[1:0] = 01. it should be noted that at higher frequencies writes to external memories emulating the internal memories may require one clock for read accesses and two clocks for write accesses. 20.9.2 internal data transfer display (show cycles) internal data transfers normally occur without showing the internal data bus activity on the external data bus. for debugging purposes, however, it may be desirable to have internal cycle data appear on the external bus. these external bus cycles are referred to as show cycles and are distinguished from normal external cycles by the fact that oe and eb[3:0] remain negated. regardless of whether show cycles are enabled, the ebi drives the address bus, tc[2:0], tsiz[1:0] and r/w signals, indicating the internal cycle activity. when show cycles are disabled, d[31:0] remains in a high impedance state. when show cycles are enabled, oe and eb[3:0] remain negated while the internal data is presented on d[31:0] on the first clock tick after the termination of the internal cycle. show cycles are always enabled in emulation mode. in master mode, show cycles are disabled coming out of reset and must be enabled by writing to the shen bit in the chip configuration register (ccr). table 20-4. emulation mode chip-select summary (1) 1. cse[1:0] is valid only for the duration of valid bus cycles or reset. undefined otherwise. cse1 cse0 indication in emulation mode 11 internal access to any register space (excluding ports) reset state (0x00c1_0000:0x00ff_ffff) 10 internal access to ports register space (0x00c0_0000:0x00c0_ffff) 01 internal access not covered by cse encoding = 11, 10 (0x0000_0000:0x00bf_ffff; 0x0100_0000:0x07ff_ffff) 00 external access (0x8000_0000 to 0xffff_ffff) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . advance information mmc2114 MMC2113 mmc2112 ? rev. 1.0 542 external bus interface module (ebi) motorola external bus interface module (ebi) note: the pepa and pcdpa bits in the ports must also be set to 1 to obtain full visibility. the waveforms shown in figure 20-5 describe show cycles. 20.9.3 show strobe (shs ) the show strobe (shs ) pin provides an indication to an external device (emulator or logic analyzer) when to latch address, tc[2:0], tsiz[1:0], r/w , cse, pstat, and data from the external pins. in master and emulation modes, show cycle strobe (shs) is enabled coming out of reset. in master mode this default functionality can be overridden to make the pin function as digital i/o. for any external cycle or show cycle, the shs pin is driven low to indicate valid address, tc, tsiz, r/w , cse, and pstat are present at the pins, and driven back high to indicate valid data. the shs pin is driven low and back high only once per external bus cycle. see figure 20-5 and figure 20-6 . figure 20-5. internal (show) cycle followed by external 1-clock read a2 a1 show data internal cycle external read ta , tea eb[3:0] oe cs clkout r/w a{22:0], tsiz[1:0] d[31:0] shs cse[1:0] 00 d1 d2 x1 x2 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . external bus interface module (ebi) emulation support mmc2114 MMC2113 mmc2112 ? rev. 1.0 advance information motorola external bus interface module (ebi) 543 figure 20-6. internal (show) cycle followed by external 1-clock write 20.9.4 transfer code (tc[2:0]) these signals are outputs from a master and inputs to a slave device. they are enabled by default in emulation mode and can be enabled in other modes by setting pepa[2:0] of port e pin assignment register (pepar). see 12.4.2.6 port e pin assignment register . these signals identify the processor state (supervisor or user) and the address space of the current bus cycle. the space and state are defined in table 20-5 . 20.9.5 processor status (pstat) these signals are outputs from the cpu and may be applied to external pins (int[5:2]). they are enabled by default in emulation mode and can be enabled in other modes by setting psten of ccr. see 4.7.3.1 chip configuration register . the pstat pins indicate the internal state and events occurring within the core, and may be monitored by a debug block to condition events, and/or may be reflected off-chip as well. table 20-6 shows the definitions of the processor status encoding. a2 a1 show data internal cycle external write ta , tea eb[3:0] oe cs clkout r/w a{22:0], tsiz[1:0] d[31:0] shs cse[1:0] 00 d1 d2 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . advance information mmc2114 MMC2113 mmc2112 ? rev. 1.0 544 external bus interface module (ebi) motorola external bus interface module (ebi) table 20-5. transfer code definitions tc[2] tc[1] tc[0] transfer type 000 user data access (1) 1. except lrw accesses. 0 0 1 reserved 010 user instruction access (2) 2. except change of flow related instruction accesses, includes lrw accesses. 011 user change of flow instruction access (3) 3. change of flow related instruction access for taken branches, jumps, and loopt instructions (includes table accesses for jmpi, jsri). 100 supervisor data access (1) 1 0 1 supervisor exception vector access 110 supervisor instruction access (2) 111 supervisor change of flow instruction access (3) table 20-6. processor status encoding pst[3] pst[2] pst[1] pst[0] internal processor state 0 0 0 0 execution stalled 0 0 0 1 execution stalled 0 0 1 0 execute exception 0011reserved 0 1 0 0 processor in stop, wait, or doze state 0 1 0 1 execution stalled 0 1 1 0 processor in debug mode 0111reserved 1000 launch instruction (1) 1. except ldm, stm, ldq, stq, hardware accelerator, lrw, change of flow, rte, or rfi instructions. 1 0 0 1 launch ldm, stm, ldq, or stq 1 0 1 0 launch hardware accelerator instruction 1 0 1 1 launch lrw 1 1 0 0 launch change of program flow instruction 1 1 0 1 launch rte or rfi 1110reserved 1 1 1 1 launch jmpi or jsri f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . external bus interface module (ebi) bus monitor mmc2114 MMC2113 mmc2112 ? rev. 1.0 advance information motorola external bus interface module (ebi) 545 20.10 bus monitor the bus monitor can be set to detect excessively long bus access termination response times. whenever an undecoded address is accessed or a peripheral is inoperative, the access is not terminated and the bus is potentially locked up while it waits for the required response. the bus monitor monitors the cycle termination response time during a bus cycle. if the cycle termination response time exceeds a programmed count, the bus monitor asserts an internal bus error. the bus monitor monitors the cycle termination response time (in system clock cycles) by using a programmable maximum allowable response period. there are four selectable response time periods for the bus monitor, selectable among 8, 16, 32, and 64 system clock cycles. the periods are selectable with the bmt[1:0] field in the chip configuration module ccr (see 4.7.3.1 chip configuration register ). the programmability of the timeout allows for varying external peripheral response times. the monitor is cleared and restarted on all bus accesses. if the cycle is not terminated within the selected response time, a timeout occurs and the bus monitor terminates the bus cycle. the bus monitor can be configured with the bme bit in the chip configuration module ccr to monitor only internal bus accesses or both internal and external bus accesses. also, the bus monitor can be disabled during debug mode for both internal and external accesses. two external bus cycles are required for a single 32-bit access to a 16-bit port. if the bus monitor is enabled to monitor external accesses, then the bus monitor views the 32-bit access as two separate external bus cycles and not as one internal bus cycle. 20.11 interrupts the ebi does not generate interrupt requests. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . advance information mmc2114 MMC2113 mmc2112 ? rev. 1.0 546 external bus interface module (ebi) motorola external bus interface module (ebi) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . mmc2114 MMC2113 mmc2112 ? rev. 1.0 advance information motorola chip select module 547 advance information ? mmc2114, MMC2113, and mmc2112 section 21. chip select module 21.1 contents 21.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .547 21.3 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .548 21.4 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .549 21.5 signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .550 21.6 memory map and registers . . . . . . . . . . . . . . . . . . . . . . . . . .550 21.6.1 memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .550 21.6.2 registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .551 21.7 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .556 21.8 interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .557 21.2 introduction the chip select module provides chip enable signals for external memory and peripheral devices. the chip selects can also be programmed to terminate bus cycles. up to four asynchronous chip select signals are available. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . advance information mmc2114 MMC2113 mmc2112 ? rev. 1.0 548 chip select module motorola chip select module 21.3 features features of the chip select module include: reduced system complexity ? no external glue logic required for typical systems if chip selects are used. four programmable asynchronous active-low chip selects (cs [3:0]) ? chip selects can be independently programmed with various features. control for external boot device ? cs0 can be enabled at reset to select an external boot device. fixed base addresses with 8-mbyte block sizes support for emulating internal memory space ? when the emint bit is set in the chip configuration register (ccr), cs1 matches only addresses in the internal memory space. support for 16-bit and 32-bit external devices ? the external port size can be programmed to be 16 or 32 bits. programmable write protection ? each chip select address range can be designated for read access only. programmable access protection ? each chip select address range can be designated for supervisor access only. write-enable selection ? the enable byte pins (eb [3:0]) can be configured as byte enables (assert on both external read and write accesses) or write enables (only assert on external write accesses). bus cycle termination ? this option allows the chip select logic to terminate the bus cycle. programmable wait states ? to interface with various devices, up to seven wait states can be programmed before the access is terminated. programmable extra wait state for write accesses ? one wait state can be added to write accesses to allow writing to memories that require additional data setup time. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . chip select module block diagram mmc2114 MMC2113 mmc2112 ? rev. 1.0 advance information motorola chip select module 549 21.4 block diagram figure 21-1 shows a programmable asynchronous chip select. all asynchronous chip selects have the same structure. all signals used to generate chip select signals are taken from the internal bus. each chip select has a chip select control register to individually program the chip select characteristics. all the chip selects share the same cycle termination generator. the active chip select for a particular bus cycle determines the number of wait states produced by the cycle termination generator before the cycle is terminated. figure 21-1. chip select block diagram data m core local bus address option compare access match match csx to cycle termination generator chip select pad control registers address compare attributes control f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . advance information mmc2114 MMC2113 mmc2112 ? rev. 1.0 550 chip select module motorola chip select module 21.5 signals table 21-1 provides an overview of the signals described here. cs [3:0] are chip-select outputs. cs [3:0] are available for general-purpose input/output (i/o) when not configured for chip select operation. 21.6 memory map and registers table 21-2 shows the chip select memory map. the registers are described in 21.6.2 registers . 21.6.1 memory map table 21-1. signal properties name function reset state pullup cs0 chip select 0 pin 1 active cs1 chip select 1 pin 1 active cs2 chip select 2 pin 1 active cs3 chip select 3 pin 1 active table 21-2. chip select memory map address bits 31 ? 16 bits 15 ? 0 access (1), (2) 0x00c2_0000 cscr0 ? chip select control register 0 cscr1 ? chip select control register 1 s 0x00c2_0004 cscr2 ? chip select control register 2 cscr3 ? chip select control register 3 s 1. user mode accesses to supervisor-only address locations have no effect and result in a cycle termination transfer error. 2. s = cpu supervisor mode access only. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . chip select module memory map and registers mmc2114 MMC2113 mmc2112 ? rev. 1.0 advance information motorola chip select module 551 21.6.2 registers the chip programming model consists of four chip select control registers (cscr0 ? cscr3), one for each chip select (cs [3:0]). cscr0 ? cscr3 are read/write always and define the conditions for asserting the chip select signals. all the chip select control registers are the same except for the reset states of the csen and ps bits in cscr0 and the csen bit in cscr1. this allows cs0 to be enabled at reset with either a 16-bit or 32-bit port size for selecting an external boot device and allows cs1 to be used to emulate internal memory. address: 0x00c2_0000 and 0x00c2_0001 bit 15 14 13 12 11 10 9 bit 8 read: so ro ps wws we ws2 ws1 ws0 write: reset:00see note11111 bit 7654321bit 0 read: 0 0 0000 taen csen write: reset:0000001see note = writes have no effect and the access terminates without a transfer error exception. note: reset state determined during reset configuration. figure 21-2. chip select control register 0 (cscr0) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . advance information mmc2114 MMC2113 mmc2112 ? rev. 1.0 552 chip select module motorola chip select module address: 0x00c2_0002 and 0x00c2_0003 bit 15 14 13 12 11 10 9 bit 8 read: so ro ps wws we ws2 ws1 ws0 write: reset:00111111 bit 7654321bit 0 read: 0 0 0000 taen csen write: reset:0000001see note = writes have no effect and the access terminates without a transfer error exception. note: reset state determined during reset configuration. figure 21-3. chip select control register 1 (cscr1) address: 0x00c2_0004 and 0x00c2_0005 bit 15 14 13 12 11 10 9 bit 8 read: so ro ps wws we ws2 ws1 ws0 write: reset:00111111 bit 7654321bit 0 read: 0 0 0000 taen csen write: reset:00000010 = writes have no effect and the access terminates without a transfer error exception. figure 21-4. chip select control register 2 (cscr2) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . chip select module memory map and registers mmc2114 MMC2113 mmc2112 ? rev. 1.0 advance information motorola chip select module 553 so ? supervisor-only bit the so bit restricts user mode access to the address range defined by the corresponding chip select. if the so bit is 1, only supervisor mode access is permitted. if the so bit is 0, both supervisor and user level accesses are permitted. when an access is made to a memory space assigned to the chip select, the chip select logic compares the so bit with bit 2 of the internal transfer code, which indicates whether the access is at the supervisor or user level. if the chip select logic detects a protection violation, the access is ignored. 1 = only supervisor mode accesses allowed; user mode accesses ignored by chip select logic 0 = supervisor and user mode accesses allowed ro ? read-only bit the ro bit restricts write accesses to the address range defined by the corresponding chip select. if the ro bit is 1, only read access is permitted. if the ro bit is 0, both read and write accesses are permitted. when an access is made to a memory space assigned to the chip select, the chip select logic compares the ro bit with the internal address: 0x00c2_00006 and 0x00c2_0007 bit 15 14 13 12 11 10 9 bit 8 read: so ro ps wws we ws2 ws1 ws0 write: reset:00111111 bit 7654321bit 0 read: 0 0 0000 taen csen write: reset:00000010 = writes have no effect and the access terminates without a transfer error exception. figure 21-5. chip select control register 3 (cscr3) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . advance information mmc2114 MMC2113 mmc2112 ? rev. 1.0 554 chip select module motorola chip select module read/write signal, which indicates whether the access is a read (read/write = 1) or a write (read/write = 0). if the chip select logic detects a violation (ro = 1 with read/write = 0), the access is ignored. 1 = only read accesses allowed; write accesses ignored by the chip select logic 0 = read and write accesses allowed ps ? port size bit the ps bit defines the width of the external data port supported by the chip select as either 16-bit or 32-bit. when a chip select is programmed as a 16-bit port, the external device must be connected to d[31:16]. for 32-bit accesses to 16-bit ports, the external memory interface initiates two bus cycles and multiplexes data as needed to complete the data transfer. 1 = 32 bit port 0 = 16 bit port wws ? write wait state bit the wws bit determines if an additional wait state is required for write cycles. wws does not affect read cycles. 1 = one additional wait state added for write cycles 0 = no additional wait state added for write cycles we ? write enable bit the we bit defines when the enable byte output pins (eb [3:0]) are asserted. when we is 0, eb [3:0] are configured as byte enables and assert for both external read and external write accesses. when we is 1, eb [3:0] are configured as write enables and assert only for external write accesses. 1 = eb [3:0] configured as write enables 0 = eb [3:0] configured as byte enables note: the we bit has no effect on the eb [3:0] pin function if the chip select is not active. if the chip select is not active, the eb [3:0] pin function is byte enable by default. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . chip select module memory map and registers mmc2114 MMC2113 mmc2112 ? rev. 1.0 advance information motorola chip select module 555 ws[2:0] ? wait states field the ws field determines the number of wait states for the chip select logic to insert before asserting the internal cycle termination signal. one wait state is equal to one system clock cycle. if ws is configured for zero wait states, then the internal cycle termination signal is asserted in the clock cycle following the start of the cycle access, resulting in one-clock transfers. a ws configured for one wait state means that the internal cycle termination signal is asserted two clock cycles after the start of the cycle access. since the internal cycle termination signal is asserted internally after the programmed number of wait states, software can adjust the bus timing to accommodate the access speed of the external device. with up to seven possible wait states, even slow devices can be interfaced with the mcu. taen ? transfer acknowledge enable bit the taen bit determines whether the internal cycle termination signal is asserted by the chip select logic when accesses occur to the address range defined by the corresponding chip select. when taen is 0, an external device is responsible for asserting the external ta pin to terminate the bus access. when taen is 1, the chip select logic asserts the internal cycle termination signal after a time determined by the programmed number of wait states. when taen is 1, external table 21-3. chip select wait states encoding ws[2:0] number of wait states wws = 0 wws = 1 read access write access read access write access 0000001 0011112 0102223 0113334 1004445 1015556 1106667 1117778 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . advance information mmc2114 MMC2113 mmc2112 ? rev. 1.0 556 chip select module motorola chip select module logic can still terminate the access before the internal cycle termination signal is asserted by asserting the external ta pin. 1 = internal cycle termination signal asserted by chip select logic 0 = internal cycle termination signal asserted by external logic csen ? chip select enable bit the csen bit enables the chip select logic. when the chip select function is disabled, the cs x signal is negated high. 1 = chip select function enabled 0 = chip select function disabled 21.7 functional description each chip select can provide a chip enable signal for an external device and assert the internal bus cycle termination signal. setting the csen bit in cscr enables the chip select to provide an external chip enable signal. setting both the csen and taen bits in cscr enables the chip select to generate the internal bus cycle termination signal. both the chip select pin assertion and the bus cycle termination function depend on an initial address/option match for activation. during the matching process, the fixed base address of each chip select is compared to the corresponding address for the bus cycle to determine whether an address match has occurred. this match is further qualified by comparing the internal read/write indication and access type with the programmed values in cscr of each chip select. when the address and option information match the current cycle, the chip select is activated. if no chip select matches the bus cycle information for the current access, the chip select logic does not respond in any way. only one chip select can be active for a given bus cycle. the configuration of the active chip select, determined by the wait state (ws/wws) field, the port size (ps) field, and the write enable (we) field, is used for the access. note: wws and ws are valid only if the taen bit is 1 for the active chip select. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . chip select module interrupts mmc2114 MMC2113 mmc2112 ? rev. 1.0 advance information motorola chip select module 557 when no chip select pin is available, the active chip select can still terminate the bus cycle. if both the csen and taen bits are 1 and the address/options match the chip select configuration, then the chip select logic asserts the internal termination signal; the bus cycle terminates after the programmed number of wait states. if the external ta or tea pin is asserted before the chip select logic asserts the internal cycle termination signal, then the bus cycle is terminated early. if internal address bit 31 is 0, then the access is internal. if internal address bit 31 is 1, then the access is external. note: chip select logic does not decode internal address bits a[30:25]. 21.8 interrupts the chip select module does not generate interrupt requests. table 21-4. chip select address range encoding chip select block size address range address bits compared (a[31:23]) (1) 1. the chip selects do not decode a[30:25]. thus, the total 32-mbyte block size is repeat- ed/mirrored in external memory space. cs0 8 mb 0x8000_0000 ? 0x807f_ffff 1xxx_xxx0_0 cs1 8 mb 0x8080_0000 ? 0x80ff_ffff 1xxx_xxx0_1 (2) 2. if the emint bit in the chip configuration module ccr is set, then cs1 matches only inter- nal accesses to the 8-mb block starting at address 0 to support emulation of internal mem- ory. thus, a[31:23] match 0xxx_xxx0_0. cs2 8 mb 0x8100_0000 ? 0x817f_ffff 1xxx_xxx1_0 cs3 8 mb 0x8180_0000 ? 0x81ff_ffff 1xxx_xxx1_1 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . advance information mmc2114 MMC2113 mmc2112 ? rev. 1.0 558 chip select module motorola chip select module f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . mmc2114 MMC2113 mmc2112 ? rev. 1.0 advance information motorola jtag test access port and once 559 advance information ? mmc2114, MMC2113, and mmc2112 section 22. jtag test access port and once 22.1 contents 22.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .561 22.3 top-level test access port (tap) . . . . . . . . . . . . . . . . . . . . .563 22.3.1 test clock (tclk) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 564 22.3.2 test mode select (tms) . . . . . . . . . . . . . . . . . . . . . . . . . .564 22.3.3 test data input (tdi) . . . . . . . . . . . . . . . . . . . . . . . . . . . . .564 22.3.4 test data output (tdo) . . . . . . . . . . . . . . . . . . . . . . . . . . .564 22.3.5 test reset (trst) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .564 22.3.6 debug event (de) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .564 22.4 top-level tap controller . . . . . . . . . . . . . . . . . . . . . . . . . . . .566 22.5 instruction shift register. . . . . . . . . . . . . . . . . . . . . . . . . . . . .567 22.5.1 extest instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .567 22.5.2 idcode instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 568 22.5.3 sample/preload instruction . . . . . . . . . . . . . . . . . . . . . 569 22.5.4 enable_mcu_once instruction . . . . . . . . . . . . . . . . . . .569 22.5.5 highz instruction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 570 22.5.6 clamp instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .570 22.5.7 bypass instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .570 22.6 idcode register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 571 22.7 bypass register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 572 22.8 boundary scan register. . . . . . . . . . . . . . . . . . . . . . . . . . . . .572 22.9 restrictions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .572 22.10 non-scan chain operation. . . . . . . . . . . . . . . . . . . . . . . . . . .573 22.11 boundary scan . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .573 22.12 low-level tap (once) module . . . . . . . . . . . . . . . . . . . . . . .579 22.13 signal descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .581 22.13.1 debug serial input (tdi) . . . . . . . . . . . . . . . . . . . . . . . . . .581 22.13.2 debug serial clock (tclk) . . . . . . . . . . . . . . . . . . . . . . . .581 22.13.3 debug serial output (tdo) . . . . . . . . . . . . . . . . . . . . . . . .581 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . advance information mmc2114 MMC2113 mmc2112 ? rev. 1.0 560 jtag test access port and once motorola jtag test access port and once 22.13.4 debug mode select (tms). . . . . . . . . . . . . . . . . . . . . . . . .582 22.13.5 test reset (trst ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .582 22.13.6 debug event (de ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .582 22.14 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .582 22.14.1 operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .583 22.14.2 once controller and serial interface. . . . . . . . . . . . . . . . .584 22.14.3 once interface signals . . . . . . . . . . . . . . . . . . . . . . . . . . .585 22.14.3.1 internal debug request input (idr ) . . . . . . . . . . . . . . .585 22.14.3.2 cpu debug request (dbgrq ) . . . . . . . . . . . . . . . . . . .586 22.14.3.3 cpu debug acknowledge (dbgack ) . . . . . . . . . . . . . .586 22.14.3.4 cpu breakpoint request (brkrq ). . . . . . . . . . . . . . . .586 22.14.3.5 cpu address, attributes (addr, attr) . . . . . . . . . . . . 587 22.14.3.6 cpu status (pstat) . . . . . . . . . . . . . . . . . . . . . . . . . . .587 22.14.3.7 once debug output (debug ) . . . . . . . . . . . . . . . . . . .587 22.14.4 once controller registers. . . . . . . . . . . . . . . . . . . . . . . . .587 22.14.4.1 once command register . . . . . . . . . . . . . . . . . . . . . . .588 22.14.4.2 once control register . . . . . . . . . . . . . . . . . . . . . . . . .590 22.14.4.3 once status register . . . . . . . . . . . . . . . . . . . . . . . . . .594 22.14.5 once decoder (odec) . . . . . . . . . . . . . . . . . . . . . . . . . . .596 22.14.6 memory breakpoint logic. . . . . . . . . . . . . . . . . . . . . . . . . .596 22.14.6.1 memory address latch (mal) . . . . . . . . . . . . . . . . . . . .597 22.14.6.2 breakpoint address base registers . . . . . . . . . . . . . . .597 22.14.7 breakpoint address mask registers . . . . . . . . . . . . . . . . .597 22.14.7.1 breakpoint address comparators . . . . . . . . . . . . . . . . .598 22.14.7.2 memory breakpoint counters . . . . . . . . . . . . . . . . . . . .598 22.14.8 once trace logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .598 22.14.8.1 once trace counter . . . . . . . . . . . . . . . . . . . . . . . . . . .599 22.14.8.2 trace operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .600 22.14.9 methods of entering debug mode . . . . . . . . . . . . . . . . . . .600 22.14.9.1 debug request during reset . . . . . . . . . . . . . . . . . . .600 22.14.9.2 debug request during normal activity . . . . . . . . . . . . .601 22.14.9.3 debug request during stop, doze, or wait mode . . . .601 22.14.9.4 software request during normal activity . . . . . . . . . . .601 22.14.10 enabling once trace mode . . . . . . . . . . . . . . . . . . . . . . .601 22.14.11 enabling once memory breakpoints. . . . . . . . . . . . . . . . .602 22.14.12 pipeline information and write-back bus register . . . . . .602 22.14.12.1 program counter register . . . . . . . . . . . . . . . . . . . . . . .603 22.14.12.2 instruction register . . . . . . . . . . . . . . . . . . . . . . . . . . . .603 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . jtag test access port and once introduction mmc2114 MMC2113 mmc2112 ? rev. 1.0 advance information motorola jtag test access port and once 561 22.14.12.3 control state register . . . . . . . . . . . . . . . . . . . . . . . . . .603 22.14.12.4 writeback bus register . . . . . . . . . . . . . . . . . . . . . . . . . 605 22.14.12.5 processor status register . . . . . . . . . . . . . . . . . . . . . . .605 22.14.13 instruction address fifo buffer (pc fifo) . . . . . . . . . . . .606 22.14.14 reserved test control registers . . . . . . . . . . . . . . . . . . . . 607 22.14.15 serial protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .607 22.14.16 once commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .608 22.14.17 target site debug system requirements . . . . . . . . . . . . .608 22.14.18 interface connector for jtag/once serial port . . . . . . . .608 22.2 introduction the mmc2114, MMC2113, and mmc2112 have two jtag (joint test action group) tap (test access port) controllers: 1. a top-level controller that allows access to the boundary scan (external pins) register, idcode register, and bypass register 2. a low-level once (on-chip emulation) controller that allows access to the central processor unit (cpu) and debugger-related registers at power-up, only the top-level tap controller will be visible. if desired, a user can then enable the low-level once controller which will in turn disable the top-level tap controller. the top-level tap controller will remain disabled until either power is removed and reapplied or until the test reset signal, trst , is asserted (logic 0). the once tap controller can be enabled in either of two ways: 1. with the top-level tap controller in its test-logic-reset state: a. deassert trst , test reset (logic1) b. assert de , the debug event (logic 0) for two tclk, test clock, cycles 2. shift the enable_mcu_once instruction, 0x3, into the top-level tap controller ? s instruction register (ir) and pass through the tap controller state update-ir. refer to figure 22-1 . f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . advance information mmc2114 MMC2113 mmc2112 ? rev. 1.0 562 jtag test access port and once motorola jtag test access port and once figure 22-1. top-level tap module and low-level (once) tap module top-level tap tap controller tap instruction register idcode (shift) register mux low-level tdo boundary scan (shift) register msb 199 0 lsb tdo bypass 1 bit low-level tap (once) de tclk tms trst msb 31 0 lsb mux mux once tap controller once cmd instruction register once data registers mux tdi module module msb 3 0 lsb ir[3:0] = 0 x 3? enable_mcu_once cmd select if yes, then b, select low-level (once) tdo; if no, than a, select ab select top-level tdo top-level tdo tdo select f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . jtag test access port and once top-level test access port (tap) mmc2114 MMC2113 mmc2112 ? rev. 1.0 advance information motorola jtag test access port and once 563 22.3 top-level test access port (tap) these devices provide a dedicated user-accessible test access port (tap) that is fully compatible with the ieee 1149.1 standard test access port and boundary-scan architecture . problems associated with testing high-density circuit boards have led to development of this proposed standard under the sponsorship of the test technology committee of ieee and the joint test action group (jtag). the implementation supports circuit-board test strategies based on this standard. the top-level tap consists of five dedicated signal pins, a 16-state tap controller, an instruction register, and three data registers, a boundary scan register for monitoring and controlling the device ? s external pins, a device identification register, and a 1-bit bypass (do nothing) register. the top-level tap provides the ability to: 1. perform boundary scan (external pin) drive and monitor operations to test circuitry external to these devices 2. disable the output pins 3. read the idcode device identification register caution: certain precautions must be observed to ensure that the top-level tap module does not interfere with non-test operation. see 22.10 non-scan chain operation for details. the top-level tap module includes a tap controller, a 4-bit instruction register, and three test data registers (a 1-bit bypass register, a 200-bit boundary scan register, and a 32-bit idcode register). the top-level tap controller and the low-level (once) tap controller share the external signals described here. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . advance information mmc2114 MMC2113 mmc2112 ? rev. 1.0 564 jtag test access port and once motorola jtag test access port and once 22.3.1 test clock (tclk) tclk is a test clock input to synchronize the test logic. tclk is independent of the processor clock. it includes an internal pullup resistor. 22.3.2 test mode select (tms) tms is a test mode select input (with an internal pullup resistor) that is sampled on the rising edge of tclk to sequence the tap controller ? s state machine. 22.3.3 test data input (tdi) tdi is a serial test data input (with an internal pullup resistor) that is sampled on the rising edge of tclk. 22.3.4 test data output (tdo) tdo is a three-state test data output that is actively driven in the shift-ir and shift-dr controller states. tdo changes on the falling edge of tclk. 22.3.5 test reset (trst ) trst is an active low asynchronous reset with an internal pullup resistor that forces the tap controller into the test-logic-reset state. 22.3.6 debug event (de ) this is a bidirectional, active-low signal. as an output, this signal will be asserted for three system clocks, synchronous to the rising clkout edge, to acknowledge that the cpu has entered debug mode as a result of a debug request or a breakpoint condition. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . jtag test access port and once top-level test access port (tap) mmc2114 MMC2113 mmc2112 ? rev. 1.0 advance information motorola jtag test access port and once 565 as an input, this signal provides multiple functions such as: the main function is a means of entering debug mode from an external command controller. this signal, when asserted, causes the cpu to finish the current instruction being executed, save the instruction pipeline information, enter debug mode, and wait for commands to be entered from the serial debug input line. this input must be asserted for at least three system clocks, sampled with the rising clkout edge. this function is ignored during reset. while the processor is in debug mode, this signal is still sampled but has no effect until debug mode is exited. another input function is to enable once. this is an alternate method to the enable_mcu_once jtag command to enable the once logic to be accessible via the jtag interface. this input signal must be asserted low (while in the test-logic-reset state with por/trst not asserted) for at least two tclk rising edges. once enabled, the once will remain enabled until the next por or trst resets. another input function is as a wake-up event from a low-power mode of operation. asynchronously asserting this signal will cause the clock controller to restart. this signal must be held asserted until the m core receives three valid rising edges on the system clock. then the processor will exit the low-power mode and go into debug mode. note: if used to enter debug mode, de must be negated before the processor exits debug mode to prevent a still low signal from being unintentionally recognized as another debug request. also, asserting this signal to enter debug mode may prevent external logic from seeing the processor output acknowledgment since the external pullup may not be able to pull the signal negated before the handshake is asserted. finally, if using this signal to enable once outside of reset it may be seen as a request to enter debug mode. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . advance information mmc2114 MMC2113 mmc2112 ? rev. 1.0 566 jtag test access port and once motorola jtag test access port and once 22.4 top-level tap controller the top-level tap controller is responsible for interpreting the sequence of logical values on the tms signal. it is a synchronous state machine that controls the operation of the jtag logic. the machine ? s states are shown in figure 22-2 . the value shown adjacent to each arc represents the value of the tms signal sampled on the rising edge of the tclk signal. the top-level tap controller can be asynchronously reset to the test- logic-reset state by asserting trst , test reset. as figure 22-2 shows, holding tms high (to logic 1) while clocking tclk through at least five rising edges will also cause the state machine to enter its test-logic-reset state. figure 22-2. top-level tap controller state machine test-logic- reset run-test/idle select-dr_scan capture-dr shift-dr exit1-dr pause-dr exit2-dr update-dr select-ir_scan capture-ir shift-ir exit1-ir pause-ir exit2-ir update-ir 0 0 0 1 1 1 0 0 1 1 1 1 0 0 1 1 1 0 0 0 1 0 1 0 0 1 0 0 0 1 1 1 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . jtag test access port and once instruction shift register mmc2114 ? MMC2113 mmc2112 ? rev. 1.0 advance information motorola jtag test access port and once 567 22.5 instruction shift register the top-level tap module uses a 4-bit instruction shift register with no parity. this register transfers its value to a parallel hold register and applies an instruction on the falling edge of tclk when the tap state machine is in the update-ir state. to load the instructions into the shift portion of the register, place the serial data on the tdi pin prior to each rising edge of tclk. the msb of the instruction shift register is the bit closest to the tdi pin and the lsb is the bit closest to the tdo pin. table 22-1 lists the instructions supported along with their opcodes, ir3 ? ir0. the last three instructions in the table are reserved for manufacturing purposes only. unused opcodes are currently decoded to perform the bypass operation, but motorola reserves the right to change their decodings in the future. 22.5.1 extest instruction the external test instruction (extest) selects the boundary scan register. the extest instruction forces all output pins and bidirectional pins configured as outputs to the preloaded fixed values (with the sample/preload instruction) and held in the boundary-scan update registers. the extest instruction can also configure the direction of bidirectional pins and establish high-impedance states on some pins. extest also asserts internal reset for the system logic to force a predictable internal state while performing external boundary scan operations. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . advance information mmc2114 MMC2113 mmc2112 ? rev. 1.0 568 jtag test access port and once motorola jtag test access port and once 22.5.2 idcode instruction the idcode instruction selects the 32-bit idcode register for connection as a shift path between the tdi pin and the tdo pin. this instruction allows interrogation of the device to determine its version number and other part identification data. the idcode register has been implemented in accordance with the ieee 1149.1 standard so that the least significant bit of the shift register stage is set to logic 1 on the rising edge of tclk following entry into the capture-dr state. therefore, the first bit to be shifted out after selecting the idcode register is table 22-1. jtag instructions instruction ir3 ? ir0 instruction summary extest 0000 selects the boundary scan register while applying fixed values to output pins and asserting functional reset idcode 0001 selects the idcode register for shift sample/preload 0010 selects the boundary scan register for shifting, sampling, and preloading without disturbing functional operation enable_mcu_once 0011 instruction to enable the m core tap controller highz 1001 selects the bypass register while three-stating all output pins and asserting functional reset clamp 1100 selects bypass while applying fixed values to output pins and asserting functional reset bypass 1111 selects the bypass register for data operations reserved 0100 0110 0101 (1) 1000 1. to exit this instruction, the trst pin must be asserted or power-on reset. instruction for chip manufacturing purposes only reserved 0111 1101 ? 1110 1010 ? 1011 decoded to select the bypass register (2) 2. motorola reserves the right to change the decoding of the unused opcodes in the future. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . jtag test access port and once junction temperature determination mmc2114 MMC2113 mmc2112 ? rev. 1.0 advance information motorola jtag test access port and once 569 always a logic 1. the remaining 31 bits are also set to fixed values on the rising edge of tclk following entry into the capture-dr state. idcode is the default instruction placed into the instruction shift register when the top-level tap resets. thus, after a tap reset, the idcode (data) register will be selected automatically. 22.5.3 sample/preload instruction the sample/preload instruction provides two separate functions. first, it obtains a sample of the system data and control signals present at the input pins and just prior to the boundary scan cell at the output pins. this sampling occurs on the rising edge of tclk in the capture-dr state when an instruction encoding of hex 2 is resident in the instruction shift register. the user can observe this sampled data by shifting it through the boundary scan register to the output tdo by using the shift-dr state. both the data capture and the shift operation are transparent to system operation. note: the user is responsible for providing some form of external synchronization to achieve meaningful results because there is no internal synchronization between tclk and the system clock. the second function of the sample/preload instruction is to initialize the boundary scan register update cells before selecting extest or clamp. this is achieved by ignoring the data being shifted out of the tdo pin while shifting in initialization data. the update-dr state in conjunction with the falling edge of tclk can then transfer this data to the update cells. this data will be applied to the external output pins when extest or clamp instruction is applied. 22.5.4 enable_mcu_once instruction the enable_mcu_once is a public instruction to enable the m core once tap controller. when the once tap controller is enabled, the top-level tap controller connects the internal once tdo to the pin tdo and remains in the run-test/idle state. it will remain in this f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . advance information mmc2114 MMC2113 mmc2112 ? rev. 1.0 570 jtag test access port and once motorola jtag test access port and once state until trst is asserted. while the once tap controller is enabled, the top-level jtag remains transparent. 22.5.5 highz instruction the highz instruction is provided as a manufacturer ? s optional public instruction to prevent having to backdrive the output pins during circuit-board testing. when highz is invoked, all output drivers, including the 2-state drivers, are turned off (for example, high impedance). the instruction selects the bypass register. highz also asserts internal reset for the system logic to force a predictable internal state. 22.5.6 clamp instruction the clamp instruction selects the bypass register and asserts internal reset while simultaneously forcing all output pins and bidirectional pins configured as outputs to the fixed values that are preloaded and held in the boundary scan update register. this instruction enhances test efficiency by reducing the overall shift path to a single bit (the bypass register) while conducting an extest type of instruction through the boundary scan register. 22.5.7 bypass instruction the bypass instruction selects the single-bit bypass register, creating a single-bit shift register path from the tdi pin to the bypass register to the tdo pin. this instruction enhances test efficiency by reducing the overall shift path when a device other than the processor becomes the device under test on a board design with multiple chips on the overall ieee 1149.1 standard defined boundary scan chain. the bypass register has been implemented in accordance with ieee 1149.1 standard so that the shift register state is set to logic 0 on the rising edge of tclk following entry into the capture-dr state. therefore, the first bit to be shifted out after selecting the bypass register is always a logic 0 (to differentiate a part that supports an idcode register from a part that supports only the bypass register). f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . jtag test access port and once idcode register mmc2114 MMC2113 mmc2112 ? rev. 1.0 advance information motorola jtag test access port and once 571 22.6 idcode register an ieee 1149.1 standard compliant jtag identification register (idcode) has been included on these devices. bits 31 ? 28 ? version number (part revision number) this is equivalent to the lower four bits of the prn of the chip identification register located in the chip configuration module. bits 27 ? 22 ? design center indicates the motorola microcontroller division bits 21 ? 12 ? device number (part identification number) bits 19-12 are equivalent to the pin of the chip identification register located in the chip configuration module. bits 11 ? 1 ? jedec id indicates the reduced jedec id for motorola. jedec refers to the joint electron device engineering council. refer to jedec publication 106-a and chapter 11 of the ieee 1149.1 standard for further information on this field. bit 0 differentiates this register as the jtag idcode register (as opposed to the bypass register), according to the ieee 1149.1 standard bit 31 30 29 28 27 26 25 bit 24 00000101 bit 23 22 21 20 19 18 17 bit 16 11000001 bit 15 14 13 12 11 10 9 bit 8 01110000 bit 7654321bit 0 00011101 figure 22-3. idcode register bit specification f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . advance information mmc2114 MMC2113 mmc2112 ? rev. 1.0 572 jtag test access port and once motorola jtag test access port and once 22.7 bypass register an ieee 1149.1 standard-compliant bypass register is included. this register which creates a single bit shift register path from tdi to the bypass register to tdo when the bypass instruction is selected. 22.8 boundary scan register an ieee 1149.1 standard-compliant boundary scan register is included. the boundary scan register is connected between tdi and tdo when the extest or sample/preload instructions are selected. this register captures signal pin data on the input pins, forces fixed values on the output signal pins, and selects the direction and drive characteristics (a logic value or high impedance) of the bidirectional and three-state signal pins. 22.9 restrictions the test logic is implemented using static logic design, and tclk can be stopped in either a high or low state without loss of data. the system logic, however, operates on a different system clock which is not synchronized to tclk internally. any mixed operation requiring the use of the ieee 1149.1 standard test logic, in conjunction with system functional logic that uses both clocks, must have coordination and synchronization of these clocks done externally. the control afforded by the output enable signals using the boundary scan register and the extest instruction requires a compatible circuit-board test environment to avoid device-destructive configurations. the user must avoid situations in which the output drivers are enabled into actively driven networks. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . jtag test access port and once non-scan chain operation mmc2114 MMC2113 mmc2112 ? rev. 1.0 advance information motorola jtag test access port and once 573 these devices feature a low-power stop mode. the interaction of the scan chain interface with low-power stop mode is: 1. the tap controller must be in the test-logic-reset state to either enter or remain in the low-power stop mode. leaving the test-logic-reset state negates the ability to achieve low-power, but does not otherwise affect device functionality. 2. the tclk input is not blocked in low-power stop mode. to consume minimal power, the tclk input should be externally connected to v dd . 3. the tms, tdi, trst pins include on-chip pullup resistors. in low-power stop mode, these three pins should remain either unconnected or connected to v dd to achieve minimal power consumption. 22.10 non-scan chain operation keeping the tap controller in the test-logic-reset state will ensure that the scan chain test logic is kept transparent to the system logic. it is recommended that tms, tdi, tclk, and trst be pulled up. trst could be connected to ground. however, since there is a pullup on trst , some amount of current will result. jtag will be initialized to the test-logic-reset state on power-up without trst asserted low due to the jtag power-on-reset internal input. the low-level tap module in the m core also has the power-on-reset input. 22.11 boundary scan the boundary scan register contains 200 bits. this register can be connected between tdi and tdo when extest or sample/preload instructions are selected. this register is used for capturing signal pin data on the input pins, forcing fixed values on the output signal pins, and selecting the direction and drive characteristics (a logic value or high impedance) of the bidirectional and three-state signal pins. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . advance information mmc2114 MMC2113 mmc2112 ? rev. 1.0 574 jtag test access port and once motorola jtag test access port and once this ieee 1149.1 standard-compliant boundary scan register contains bits for bonded-out and non-bonded signals excluding jtag signals, analog signals, power supplies, compliance enable pins, and clock signals.to maintain jtag compliance, test should be held to logic 0 and de should be held to logic 1. these non-scanned pins are shown in table 22-2 . table 22-2. list of pins not scanned in jtag mode pin name pin type extal clock/analog xtal clock/analog v ddsyn supply v sssyn supply pqa4 ? pqa3 and pqa1 ? pqa0 analog pqb3 ? pqb0 analog v rh supply v rl supply v dda supply v ssa supply v ddh supply trst jtag tclk jtag tms jtag tdi jtag tdo jtag de jtag compliance enable test jtag compliance enable v pp supply v ddf supply v ssf supply v stby supply v dd supply v ss supply f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . jtag test access port and once boundary scan mmc2114 MMC2113 mmc2112 ? rev. 1.0 advance information motorola jtag test access port and once 575 table 22-3 defines the boundary scan register. the first column shows bit numbers assigned to each of the register ? s cells. the bit nearest to tdo (the first to be shifted in) is defined as bit 0. the second column lists the logical state bit for each pin alternately with the read/write direction control bit for that pin. the logic state bits are non-inverting with respect to their associated pins, so that a 1 logical state bit equates to a logical high voltage on its corresponding pin. a direction control bit value of 1 causes a pin ? s logical state to be expressed by its logic state bit, a read of a pin. a direction control bit value of 0 causes a pin ? s logical voltage to follow the state of its logical state bit, a write to a pin. table 22-3. boundary scan register definition (sheet 1 of 4) (note: shaded regions indicate optional pins) bit logical state and direction control bits for each pin bit logical state and direction control bits for each pin 0 d31 logical state 17 a18 direction control 1 d31 direction control 18 a19 logical state 2 a12 logical state 19 a19 direction control 3 a12 direction control 20 rstout logical state 4 a13 logical state 21 rstout direction control 5 a13 direction control 22 a20 logical state 6 a14 logical state 23 a20 direction control 7 a14 direction control 24 reset logical state 8 a15 logical state 25 reset direction control 9 a15 direction control 26 a21 logical state 10 a16 logical state 27 a21 direction control 11 a16 direction control 28 a22 logical state 12 a17 logical state 29 a22 direction control 13 a17 direction control 30 tea logical state 14 clkout logical state 31 tea direction control 15 clkout direction control 32 eb0 logical state 16 a18 logical state 33 eb0 direction control f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . advance information mmc2114 MMC2113 mmc2112 ? rev. 1.0 576 jtag test access port and once motorola jtag test access port and once 34 eb1 logical state 64 cs2 logical state 35 eb1 direction control 65 cs2 direction control 36 ta logical state 66 int4 logical state 37 ta direction control 67 int4 direction control 38 eb2 logical state 68 cs3 logical state 39 eb2 direction control 69 cs3 direction control 40 shs logical state 70 tc0 logical state 41 shs direction control 71 tc0 direction control 42 eb3 logical state 72 int3 logical state 43 eb3 direction control 73 int3 direction control 44 oe logical state 74 tc1 logical state 45 oe direction control 75 tc1 direction control 46 ss logical state 76 int2 logical state 47 ss direction control 77 int2 direction control 48 sck logical state 78 int1 logical state 49 sck direction control 79 int1 direction control 50 miso logical state 80 int0 logical state 51 miso direction control 81 int0 direction control 52 mosi logical state 82 rxd1 logical state 53 mosi direction control 83 rxd1 direction control 54 int7 logical state 84 txd1 logical state 55 int7 direction control 85 txd1 direction control 56 int6 logical state 86 rxd2 logical state 57 int6 direction control 87 rxd2 direction control 58 cs0 logical state 88 tc2 logical state 59 cs0 direction control 89 tc2 direction control 60 cs1 logical state 90 txd2 logical state 61 cs1 direction control 91 txd2 direction control 62 int5 logical state 92 cse0 logical state 63 int5 direction control 93 cse0 direction control table 22-3. boundary scan register definition (sheet 2 of 4) (note: shaded regions indicate optional pins) bit logical state and direction control bits for each pin bit logical state and direction control bits for each pin f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . jtag test access port and once boundary scan mmc2114 MMC2113 mmc2112 ? rev. 1.0 advance information motorola jtag test access port and once 577 94 icoc1_0 logical state 124 d2 logical state 95 icoc1_0 direction control 125 d2 direction control 96 cse1 logical state 126 d3 logical state 97 cse1 direction control 127 d3 direction control 98 r/w logical state 128 d4 logical state 99 r/w direction control 129 d4 direction control 100 icoc1_1 logical state 130 d5 logical state 101 icoc1_1 direction control 131 d5 direction control 102 icoc1_2 logical state 132 d6 logical state 103 icoc1_2 direction control 133 d6 direction control 104 icoc1_3 logical state 134 d7 logical state 105 icoc1_3 direction control 135 d7 direction control 106 icoc2_0 logical state 136 d8 logical state 107 icoc2_0 direction control 137 d8 direction control 108 icoc2_1 logical state 138 d9 logical state 109 icoc2_1 direction control 139 d9 direction control 110 icoc2_2 logical state 140 d10 logical state 111 icoc2_2 direction control 141 d10 direction control 112 icoc2_3 logical state 142 d11 logical state 113 icoc2_3 direction control 143 d11 direction control 114 d0 logical state 144 d12 logical state 115 d0 direction control 145 d12 direction control 116 a0 logical state 146 d13 logical state 117 a0 direction control 147 d13 direction control 118 a1 logical state 148 d14 logical state 119 a1 direction control 149 d14 direction control 120 d1 logical state 150 a3 logical state 121 d1 direction control 151 a3 direction control 122 a2 logical state 152 a4 logical state 123 a2 direction control 153 a4 direction control table 22-3. boundary scan register definition (sheet 3 of 4) (note: shaded regions indicate optional pins) bit logical state and direction control bits for each pin bit logical state and direction control bits for each pin f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . advance information mmc2114 MMC2113 mmc2112 ? rev. 1.0 578 jtag test access port and once motorola jtag test access port and once 154 d15 logical state 177 a8 direction control 155 d15 direction control 178 a9 logical state 156 a5 logical state 179 a9 direction control 157 a5 direction control 180 d23 logical state 158 d16 logical state 181 d23 direction control 159 d16 direction control 182 a10 logical state 160 a6 logical state 183 a10 direction control 161 a6 direction control 184 d24 logical state 162 a7 logical state 185 d24 direction control 163 a7 direction control 186 d25 logical state 164 d17 logical state 187 d25 direction control 165 d17 direction control 188 a11 logical state 166 d18 logical state 189 a11 direction control 167 d18 direction control 190 d26 logical state 168 d19 logical state 191 d16 direction control 169 d19 direction control 192 d27 logical state 170 d20 logical state 193 d27 direction control 171 d20 direction control 194 d28 logical state 172 d21 logical state 195 d28 direction control 173 d21 direction control 196 d29 logical state 174 d22 logical state 197 d29 direction control 175 d22 direction control 198 d30 logical state 176 a8 logical state 199 d30 direction control table 22-3. boundary scan register definition (sheet 4 of 4) (note: shaded regions indicate optional pins) bit logical state and direction control bits for each pin bit logical state and direction control bits for each pin f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . jtag test access port and once low-level tap (once) module mmc2114 MMC2113 mmc2112 ? rev. 1.0 advance information motorola jtag test access port and once 579 22.12 low-level tap (once) module the low-level tap (once, on-chip emulation) circuitry provides a simple, inexpensive debugging interface that allows external access to the processor ? s internal registers and to memory/peripherals. once capabilities are controlled through a serial interface, mapped onto a jtag test access port (tap) protocol. refer to figure 22-4 for a block diagram of the once. note: the interface to the once controller and its resources is based on the tap defined for jtag in the ieee 1149.1 standard. figure 22-4. once block diagram figure 22-5 shows the once (low-level tap module) data registers. pipeline information once controller and serial breakpoint registers and pc fifo breakpoint and trace interface logic comparators tclk tdi tms tdo trst de f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . advance information mmc2114 MMC2113 mmc2112 ? rev. 1.0 580 jtag test access port and once motorola jtag test access port and once figure 22-5. low-level (once) tap module data registers (drs) ctl ir pc psr wbbr sqc dr idre tme frzc rcb bcb rca bca tdo 0 lsb 0 lsb 0 lsb 0 lsb 0 lsb 0 lsb 0 lsb 0 lsb 0 lsb 0 lsb 1 bit 1 bit msb 15 msb 15 msb 31 msb msb 31 msb 31 msb 31 msb 31 msb 15 127 112 111 96 95 64 63 32 31 17 16 15 14 13 12 11 10 6 5 4 memory bkpt counter a (shift) register, mbca program counter fifo and increment counter (shift) register, pc fifo msb 15 bkpt address base register b (shift) register, babb bkpt address mask register b (shift) register, bamb (shift) register, osr (shift) register, bypass (shift) register, otc (shift) register, mbcb (shift) register, baba (shift) register, bama (shift) register, ocr (shift) register, cpuscr bypass register pass- bypass register pass- once status trace counter memory bkpt counter b bkpt address base register a bkpt address mask register a cpu scan chain register once control register through, bypass through 0 lsb msb 31 tdi mux ocmr, 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xa 0xb 0xc 0xd 0xe 0x1f rs[4:0] = rs4 ? rs0 from once cmd (instruction) register, ocmr in figure 22-1 (test data in) (test data out) detailed view of once data registers block found in figure 22-1 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . jtag test access port and once signal descriptions mmc2114 MMC2113 mmc2112 ? rev. 1.0 advance information motorola jtag test access port and once 581 22.13 signal descriptions the once pin interface is used to transfer once instructions and data to the once control block. depending on the particular resource being accessed, the cpu may need to be placed in debug mode. for resources outside of the cpu block and contained in the once block, the processor is not disturbed and may continue execution. if a processor resource is required, the once controller may assert an internal debug request (dbgrq ) to the cpu. this causes the cpu to finish the instruction being executed, save the instruction pipeline information, enter debug mode, and wait for further commands. note: asserting dbgrq causes the device to exit stop, doze, or wait mode and to enter debug mode. 22.13.1 debug serial input (tdi) data and commands are provided to the once controller through the tdi pin. data is latched on the rising edge of the tclk serial clock. data is shifted into the once serial port least significant bit (lsb) first. 22.13.2 debug serial clock (tclk) the tclk pin supplies the serial clock to the once control block. the serial clock provides pulses required to shift data and commands into and out of the once serial port. (data is clocked into the once on the rising edge and is clocked out of the once serial port on the falling edge.) the debug serial clock frequency must be no greater than 50 percent of the processor clock frequency. 22.13.3 debug serial output (tdo) serial data is read from the once block through the tdo pin. data is always shifted out the once serial port lsb first. data is clocked out of the once serial port on the falling edge of tclk. tdo is three-stateable and is actively driven in the shift-ir and shift-dr controller states. tdo changes on the falling edge of tclk. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . advance information mmc2114 MMC2113 mmc2112 ? rev. 1.0 582 jtag test access port and once motorola jtag test access port and once 22.13.4 debug mode select (tms) the tms input is used to cycle through states in the once debug controller. toggling the tms pin while clocking with tclk controls the transitions through the tap state controller. 22.13.5 test reset (trst ) the trst input is used to reset the once controller externally by placing the once control logic in a test logic reset state. once operation is disabled in the reset controller and reserved states. 22.13.6 debug event (de ) the de pin is a bidirectional open drain pin. as an input, de provides a fast means of entering debug mode from an external command controller. as an output, this pin provides a fast means of acknowledging debug mode entry to an external command controller. the assertion of this pin by a command controller causes the cpu to finish the current instruction being executed, save the instruction pipeline information, enter debug mode, and wait for commands to be entered from the tdi line. if de was used to enter debug mode, then de must be negated after the once responds with an acknowledgment and before sending the first once command. the assertion of this pin by the cpu acknowledges that it has entered debug mode and is waiting for commands to be entered from the tdi line. 22.14 functional description the on-chip emulation (once) circuitry provides a simple, inexpensive debugging interface that allows external access to the processor ? s internal registers and to memory/peripherals. once capabilities are controlled through a serial interface, mapped onto a jtag test access port (tap) protocol. figure 22-6 shows the components of the once circuitry. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . jtag test access port and once functional description mmc2114 MMC2113 mmc2112 ? rev. 1.0 advance information motorola jtag test access port and once 583 22.14.1 operation an instruction is scanned into the once module through the serial interface and then decoded. data may then be scanned in and used to update a register or resource on a write to the resource, or data associated with a resource may be scanned out for a read of the resource. for accesses to the cpu internal state, the once controller requests the cpu to enter debug mode via the cpu dbgrq input. once the cpu enters debug mode, as indicated by the once status register (osr), the processor state may be accessed through the cpu scan register. figure 22-6. once controller capture ? dr shift ? dr exit1 ? dr pause ? dr exit2 ? dr update ? dr select ? ir scan capture ? ir shift ? ir exit1 ? ir pause ? ir exit2 ? ir update ? ir select dr- scan run-test/idle test-logic-reset 1 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 00 0 0 00 0 0 0 0 0 0 0 0 0 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . advance information mmc2114 MMC2113 mmc2112 ? rev. 1.0 584 jtag test access port and once motorola jtag test access port and once the once controller is implemented as a 16-state finite state machine, with a one-to-one correspondence to the states defined for the jtag tap controller. cpu registers and the contents of memory locations are accessed by scanning instructions and data into and out of the cpu scan chain. required data is accessed by executing the scanned instructions. memory locations may be read by scanning in a load instruction to the cpu that references the desired memory location, executing the load instruction, and then scanning out the result of the load. other resources are accessed in a similar manner. resources contained in the once module that do not require the cpu to be halted for access may be controlled while the cpu is executing and do not interfere with normal processor execution. accesses to certain resources, such as the pc fifo and the count registers, while not part of the cpu, may require the cpu to be stopped to allow access to avoid synchronization hazards. if it is known that the cpu clock is enabled and running no slower than the tclk input, there is sufficient synchronization performed to allow reads but not writes of these specific resources. debug firmware may ensure that it is safe to access these resources by reading the osr to determine the state of the cpu prior to access. all other cases require the cpu to be in the debug state for deterministic operation. 22.14.2 once controller and serial interface figure 22-7 is a block diagram of the once controller and serial interface. the once command register (ocmr) acts as the instruction register (ir) for the tap controller. all other once resources are treated as data registers (dr) by the tap controller. the command register is loaded by serially shifting in commands during the tap controller shift-ir state, and is loaded during the update-ir state. the ocmr selects a once resource to be accessed as a dr during the tap controller capture-dr, shift-dr and update-dr states. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . jtag test access port and once functional description mmc2114 MMC2113 mmc2112 ? rev. 1.0 advance information motorola jtag test access port and once 585 figure 22-7. once controller and serial interface 22.14.3 once interface signals figure 22-8 shows the interface signals for the once controller. the following paragraphs describe the once interface signals to other internal blocks associated with the once controller. these signals are not available externally, and descriptions are provided to improve understanding of once operation. 22.14.3.1 internal debug request input (idr ) the internal debug request input is a hardware signal which is used in some implementations to force an immediate debug request to the cpu. if present and enabled, it functions in an identical manner to the control function provided by the dr control bit in the ocr. this input is maskable by a control bit in the ocr. once command register once status and control registers isbkpt istrace isdr once decoder once tap controller tdi tclk tdo tms register read cpu control/ status register write f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . advance information mmc2114 MMC2113 mmc2112 ? rev. 1.0 586 jtag test access port and once motorola jtag test access port and once figure 22-8. once interface diagram 22.14.3.2 cpu debug request (dbgrq ) the dbgrq signal is asserted by the once control logic to request the cpu to enter the debug state. it may be asserted for a number of different conditions. assertion of this signal causes the cpu to finish the current instruction being executed, save the instruction pipeline information, enter debug mode, and wait for further commands. asserting dbgrq causes the device to exit stop, doze, or wait mode. 22.14.3.3 cpu debug acknowledge (dbgack ) the cpu asserts the dbgack signal upon entering the debug state. this signal is part of the handshake mechanism between the once control logic and the cpu. 22.14.3.4 cpu breakpoint request (brkrq ) the brkrq signal is asserted by the once control logic to signal that a breakpoint condition has occurred for the current cpu bus access. tck tdi tms tdo trst de once controller and serial interface breakpoint registers and comparators pc fifo pipeline information breakpoint and trace logic debug idr dbgack dbgrq brkrq addr attr pstat f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . jtag test access port and once functional description mmc2114 MMC2113 mmc2112 ? rev. 1.0 advance information motorola jtag test access port and once 587 22.14.3.5 cpu address, attributes (addr, attr) the cpu address and attribute information may be used in the memory breakpoint logic to qualify memory breakpoints with access address and cycle type information. 22.14.3.6 cpu status (pstat) the trace logic uses the pstat signals to qualify trace count decrements with specific cpu activity. 22.14.3.7 once debug output (debug ) the debug signal is used to indicate to on-chip resources that a debug session is in progress. peripherals and other units may use this signal to modify normal operation for the duration of a debug session. this may involve the cpu executing a sequence of instructions solely for the purpose of visibility/system control. these instructions are not part of the normal instruction stream that the cpu would have executed had it not been placed in debug mode. this signal is asserted the first time the cpu enters the debug state and remains asserted until the cpu is released by a write to the once command register with the go and ex bits set, and a register specified as either no register selected or the cpuscr. this signal remains asserted even though the cpu may enter and exit the debug state for each instruction executed under control of the once controller. 22.14.4 once controller registers this section describes the once controller registers: once command register (ocmr) once control register (ocr) once status register (osr) all once registers are addressed by means of the rs field in the ocmr, as shown in table 22-4 . f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . advance information mmc2114 MMC2113 mmc2112 ? rev. 1.0 588 jtag test access port and once motorola jtag test access port and once 22.14.4.1 once command register the once command register (ocmr) is an 8-bit shift register that receives its serial data from the tdi pin. this register corresponds to the jtag ir and is loaded when the update-ir tap controller state is entered. it holds the 8-bit commands shifted in during the shift-ir controller state to be used as input for the once decoder. the ocmr contains fields for controlling access to a once resource, as well as controlling single-step operation, and exit from once mode. although the ocmr is updated during the update-ir tap controller state, the corresponding resource is accessed in the dr scan sequence of the tap controller, and as such, the update-dr state must be transitioned through in order for an access to occur. in addition, the update-dr state must also be transitioned through in order for the single-step and/or exit functionality to be performed, even though the command appears to have no data resource requirement associated with it. r/w ? read/write bit 1 = read the data in the register specified by the rs field. 0 = write the data associated with the command into the register specified by the rs field. go ? go bit when the go bit is set, the device executes the instruction in the ir register in the cpuscr. to execute the instruction, the processor leaves debug mode, executes the instruction, and if the ex bit is cleared, returns to debug mode immediately after executing the instruction. the processor resumes normal operation if the ex bit is set. the go command is executed only if the operation is a read/write to either the cpuscr or to ? no register selected. ? otherwise, the go bit 7654321bit 0 r/w g ex rs4 rs3 rs2 rs1 rs0 figure 22-9. once command register (ocmr) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . jtag test access port and once functional description mmc2114 MMC2113 mmc2112 ? rev. 1.0 advance information motorola jtag test access port and once 589 bit has no effect. the processor leaves debug mode after the tap controller update-dr state is entered. 1 = execute instruction in ir 0 = inactive (no action taken) ex ? exit bit when the ex bit is set, the processor leaves debug mode and resumes normal operation until another debug request is generated. the exit command is executed only if the go bit is set and the operation is a read/write to the cpuscr or a read/write to ? no register selected. ? otherwise, the ex bit has no effect. the processor exits debug mode after the tap controller update-dr state is entered. 1 = leave debug mode 0 = remain in debug mode rs4 ? rs0 ? register select field the rs field defines the source for the read operation or the destination for the write operation. table 22-4 shows once register addresses. table 22-4. once register addressing rs4 ? rs0 register selected 00000 reserved 00001 reserved 00010 reserved 00011 otc ? once trace counter 00100 mbca ? memory breakpoint counter a 00101 mbcb ? memory breakpoint counter b 00110 pc fifo ? program counter fifo and increment counter 00111 baba ? breakpoint address base register a 01000 babb ? breakpoint address base register b 01001 bama ? breakpoint address mask register a 01010 bamb ? breakpoint address mask register b 01011 cpuscr ? cpu scan chain register 01100 bypass ? no register selected 01101 ocr ? once control register 01110 osr ? once status register f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . advance information mmc2114 MMC2113 mmc2112 ? rev. 1.0 590 jtag test access port and once motorola jtag test access port and once 22.14.4.2 once control register the 32-bit once control register (ocr) selects the events that put the device in debug mode and enables or disables sections of the once logic. 01111 reserved (factory test control register ? do not access) 10000 reserved (mem_bist ? do not access) 10001 ? 10110 reserved (bypass, do not access) 10111 reserved (lsrl, do not access) 11000 ? 11110 reserved (bypass, do not access) 11111 bypass table 22-4. once register addressing (continued) rs4 ? rs0 register selected bit 31 30 29 28 27 26 25 bit 24 read: 0 0 000000 write: reset:00000000 bit 23 22 21 20 19 18 17 bit 16 read: 0 0 0000 sqc1 sqc0 write: reset:00000000 bit 15 14 13 12 11 10 9 bit 8 read: dr idre tme frzc rcb bcb4 bcb3 bcb2 write: reset:00000000 bit 7654321bit 0 read: bcb1 bcb0 rca bca4 bca3 bca2 bca1 bca0 write: reset:00000000 = unimplemented or reserved figure 22-10. once control register (ocr) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . jtag test access port and once functional description mmc2114 MMC2113 mmc2112 ? rev. 1.0 advance information motorola jtag test access port and once 591 sqc1 and sqc0 ? sequential control field the sqc field allows memory breakpoint b and trace occurrences to be suspended until a qualifying event occurs. test logic reset clears the sqc field. see table 22-5 . dr ? debug request bit dr requests the cpu to enter debug mode unconditionally. the pm bits in the once status register indicate that the cpu is in debug mode. once the cpu enters debug mode, it returns there even with a write to the ocmr with go and ex set until the dr bit is cleared. test logic reset clears the dr bit. table 22-5. sequential control field settings sqc1 and sqc0 meaning 00 disable sequential control operation. memory breakpoints and trace operation are unaffected by this field. 01 suspend normal trace counter operation until a breakpoint condition occurs for memory breakpoint b. in this mode, memory breakpoint b occurrences no longer cause breakpoint requests to be generated. instead, trace counter comparisons are suspended until the first memory breakpoint b occurrence. after the first memory breakpoint b occurrence, trace counter control is released to perform normally, assuming tme is set. this allows a sequence of breakpoint conditions to be specified prior to trace counting. 10 qualify memory breakpoint b matches with a breakpoint occurrence for memory breakpoint a. in this mode, memory breakpoint a occurrences no longer cause breakpoint requests to be generated. instead, memory breakpoint b comparisons are suspended until the first memory breakpoint a occurrence. after the first memory breakpoint a occurrence, memory breakpoint b is enabled to perform normally. this allows a sequence of breakpoint conditions to be specified. 11 combine the 01 and 10 qualifications. in this mode, no breakpoint requests are generated, and trace count operation is enabled once a memory breakpoint b occurrence follows a memory breakpoint a occurrence if tme is set. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . advance information mmc2114 MMC2113 mmc2112 ? rev. 1.0 592 jtag test access port and once motorola jtag test access port and once idre ? internal debug request enable bit the internal debug request (idr ) input to the once control logic may not be used in all implementations. in some implementations, the idr control input may be connected and used as an additional hardware debug request. test logic reset clears the idre bit. 1 = idr input enabled 0 = idr input disabled tme ? trace mode enable bit tme enables trace operation. test logic reset clears the tme bit. trace operation is also affected by the sqc field. 1 = trace operation enabled 0 = trace operation disabled frzc ? freeze control bit this control bit is used in conjunction with memory breakpoint b registers to select between asserting a breakpoint condition when a memory breakpoint b occurs or freezing the pc fifo from further updates when memory breakpoint b occurs while allowing the cpu to continue execution. the pc fifo remains frozen until the frzo bit in the osr is cleared. 1 = memory breakpoint b occurrence freezes pc fifo and does not assert breakpoint condition. 0 = memory breakpoint b occurrence asserts breakpoint condition. rcb and rca ? memory breakpoint b and a range control bits rcb and rda condition enabled memory breakpoint occurrences happen when memory breakpoint matches are either within or outside the range defined by memory base address and mask. 1 = condition breakpoint on access outside of range 0 = condition breakpoint on access within range bcb4 ? bcb0 and bca4 ? bca0 ? memory breakpoint b and a control fields the bcb and bca fields enable memory breakpoints and qualify the access attributes to select whether the breakpoint matches are recognized for read, write, or instruction fetch (program space) accesses. test logic reset clears bcb4 ? bcb0 and bca4 ? bca0. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . jtag test access port and once functional description mmc2114 MMC2113 mmc2112 ? rev. 1.0 advance information motorola jtag test access port and once 593 table 22-6. memory breakpoint control field settings bcb4 ? bcb0 bca4 ? bca0 description 00000 breakpoint disabled 00001 qualify match with any access 00010 qualify match with any instruction access 00011 qualify match with any data access 00100 qualify match with any change of flow instruction access 00101 qualify match with any data write 00110 qualify match with any data read 00111 reserved 01xxx reserved 10000 reserved 10001 qualify match with any user access 10010 qualify match with any user instruction access 10011 qualify match with any user data access 10100 qualify match with any user change of flow access 10101 qualify match with any user data write 10110 qualify match with any user data read 10111 reserved 11000 reserved 11001 qualify match with any supervisor access 11010 qualify match with any supervisor instruction access 11011 qualify match with any supervisor data access 11100 qualify match with any supervisor change of flow access 11101 qualify match with any supervisor data write 11110 qualify match with any supervisor data read 11111 reserved f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . advance information mmc2114 MMC2113 mmc2112 ? rev. 1.0 594 jtag test access port and once motorola jtag test access port and once 22.14.4.3 once status register the 16-bit once status register (osr) indicates the reason(s) that debug mode was entered and the current operating mode of the cpu. hdro ? hardware debug request occurrence flag hdro is set when the processor enters debug mode as a result of a hardware debug request from the idr signal or the de pin. this bit is cleared on test logic reset or when debug mode is exited with the go and ex bits set. dro ? debug request occurrence flag dro is set when the processor enters debug mode and the debug request (dr) control bit in the once control register is set. this bit is cleared on test logic reset or when debug mode is exited with the go and ex bits set. mbo ? memory breakpoint occurrence flag mbo is set when a memory breakpoint request has been issued to the cpu via the brkrq input and the cpu enters debug mode. in some situations involving breakpoint requests on instruction prefetches, the cpu may discard the request along with the prefetch. in this case, this bit may become set due to the cpu entering debug mode for another reason. this bit is cleared on test logic reset or when debug mode is exited with the go and ex bits set. bit 15 14 13 12 11 10 9 bit 8 read: 0 0 0000hdrodro write: reset: 0 0 bit 7654321bit 0 read: mbo swo to frzo sqb sqa pm1 pm0 write: reset:00000000 = unimplemented or reserved figure 22-11. once status register (osr) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . jtag test access port and once functional description mmc2114 MMC2113 mmc2112 ? rev. 1.0 advance information motorola jtag test access port and once 595 swo ? software debug occurrence flag swo bit is set when the processor enters debug mode of operation as a result of the execution of the bkpt instruction. this bit is cleared on test logic reset or when debug mode is exited with the go and ex bits set. to ? trace count occurrence flag to is set when the trace counter reaches zero with the trace mode enabled and the cpu enters debug mode. this bit is cleared on test logic reset or when debug mode is exited with the go and ex bits set. frzo ? fifo freeze occurrence flag frzo is set when a fifo freeze occurs. this bit is cleared on test logic reset or when debug mode is exited with the go and ex bits set. sqb ? sequential breakpoint b arm occurrence flag sqb is set when sequential operation is enabled and a memory breakpoint b event has occurred to enable trace counter operation. this bit is cleared on test logic reset or when debug mode is exited with the go and ex bits set. sqa ? sequential breakpoint a arm occurrence flag sqa is set when sequential operation is enabled and a memory breakpoint a event has occurred to enable memory breakpoint b operation. this bit is cleared on test logic reset or when debug mode is exited with the go and ex bits set. pm1 and pm0 ? processor mode field these flags reflect the processor operating mode. they allow coordination of the once controller with the cpu for synchronization. table 22-7. processor mode field settings pm1 and pm0 meaning 00 processor in normal mode 01 processor in stop, doze, or wait mode 10 processor in debug mode 11 reserved f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . advance information mmc2114 MMC2113 mmc2112 ? rev. 1.0 596 jtag test access port and once motorola jtag test access port and once 22.14.5 once decoder (odec) the odec receives as input the 8-bit command from the ocmr and status signals from the processor. the odec generates all the strobes required for reading and writing the selected once registers. 22.14.6 memory breakpoint logic memory breakpoints can be set for a particular memory location or on accesses within an address range. the breakpoint logic contains an input latch for addresses, registers that store the base address and address mask, comparators, attribute qualifiers, and a breakpoint counter. figure 22-12 illustrates the basic functionality of the once memory breakpoint logic. this logic is duplicated to provide two independent breakpoint resources. figure 22-12. once memory breakpoint logic address comparator dec address mask register x breakpoint counter memory breakpoint qualification match bc[4:0], rcx breakpoint match occurred isbkptx count = 0 dso dsi dsck addr[31:0] attr memory address latch address base register x f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . jtag test access port and once functional description mmc2114 MMC2113 mmc2112 ? rev. 1.0 advance information motorola jtag test access port and once 597 address comparators can be used to determine where a program may be getting lost or when data is being written to areas which should not be written. they are also useful in halting a program at a specific point to examine or change registers or memory. using address comparators to set breakpoints enables the user to set breakpoints in ram or rom in any operating mode. memory accesses are monitored according to the contents of the ocr. the address comparator generates a match signal when the address on the bus matches the address stored in the breakpoint address base register, as masked with individual bit masking capability provided by the breakpoint address mask register. the address match signal and the access attributes are further qualified with the rcx4 ? rcx0 and bcx4 ? bcx0 control bits. this qualification is used to decrement the breakpoint counter conditionally if its contents are non-zero. if the contents are zero, the counter is not decremented and the breakpoint event occurs (isbkptx asserted). 22.14.6.1 memory address latch (mal) the mal is a 32-bit register that latches the address bus on every access. 22.14.6.2 breakpoint address base registers the 32-bit breakpoint address base registers (baba and babb) store memory breakpoint base addresses. baba and babb can be read or written through the once serial interface. before enabling breakpoints, the external command controller should load these registers. 22.14.7 breakpoint address mask registers the 32-bit breakpoint address mask registers (bama and bamb) registers store memory breakpoint base address masks. bama and bamb can be read or written through the once serial interface. before enabling breakpoints, the external command controller should load these registers. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . advance information mmc2114 MMC2113 mmc2112 ? rev. 1.0 598 jtag test access port and once motorola jtag test access port and once 22.14.7.1 breakpoint address comparators the breakpoint address comparators are not externally accessible. each compares the memory address stored in mal with the contents of babx, as masked by bamx, and signals the control logic when a match occurs. 22.14.7.2 memory breakpoint counters the 16-bit memory breakpoint counter registers (mbca and mbcb) are loaded with a value equal to the number of times, minus one, that a memory access event should occur before a memory breakpoint is declared. the memory access event is specified by the rcx4 ? rcx0 and bcx4 ? bcx0 bits in the ocr and by the memory base and mask registers. on each occurrence of the memory access event, the breakpoint counter, if currently non-zero, is decremented. when the counter has reached the value of zero and a new occurrence takes place, the isbkptx signal is asserted and causes the cpu ? s brkrq input to be asserted. the mbcx can be read or written through the once serial interface. anytime the breakpoint registers are changed, or a different breakpoint event is selected in the ocr, the breakpoint counter must be written afterward. this assures that the once breakpoint logic is reset and that no previous events will affect the new breakpoint event selected. 22.14.8 once trace logic the once trace logic allows the user to execute instructions in single or multiple steps before the device returns to debug mode and awaits once commands from the debug serial port. the once trace logic is independent of the m core trace facility, which is controlled through the trace mode bits in the m core processor status register. the once trace logic block diagram is shown in figure 22-13 . f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . jtag test access port and once functional description mmc2114 MMC2113 mmc2112 ? rev. 1.0 advance information motorola jtag test access port and once 599 22.14.8.1 once trace counter the once trace counter register (otc) is a 16-bit counter that allows more than one instruction to be executed in real time before the device returns to debug mode. this feature helps the software developer debug sections of code that are time-critical. the trace counter also enables the user to count the number of instructions executed in a code segment. figure 22-13. once trace logic block diagram the otc register can be read, written, or cleared through the once serial interface. if n instructions are to be executed before entering debug mode, the trace counter should be loaded with n ? 1. n must not equal zero unless the sequential breakpoint control capability is being used. in this case a value of zero (indicating a single instruction) is allowed. a hardware reset clears the otc. dec once trace counter count = 0 istrace dso dsi dsck end of instruction f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . advance information mmc2114 MMC2113 mmc2112 ? rev. 1.0 600 jtag test access port and once motorola jtag test access port and once 22.14.8.2 trace operation to initiate trace mode operation: 1. load the otc register with a value. this value must be non-zero, unless sequential breakpoint control operation is enabled in the ocr register. in this case, a value of zero (indicating a single instruction) is allowed. 2. initialize the program counter and instruction register in the cpuscr with values corresponding to the start location of the instruction(s) to be executed real-time. 3. set the tme bit in the ocr. 4. release the processor from debug mode by executing the appropriate command issued by the external command controller. when debug mode is exited, the counter is decremented after each execution of an instruction. interrupts can be serviced, and all instructions executed (including interrupt services) will decrement the trace counter. when the trace counter decrements to zero, the once control logic requests that the processor re-enter debug mode, and the trace occurrence bit to in the osr is set to indicate that debug mode has been requested as a result of the trace count function. the trace counter allows a minimum of two instructions to be specified for execution prior to entering trace (specified by a count value of one), unless sequential breakpoint control operation is enabled in the ocr. in this case, a value of zero (indicating a single instruction) is allowed. 22.14.9 methods of entering debug mode the pm status field in the osr indicates that the cpu has entered debug mode. the following paragraphs discuss conditions that invoke debug mode. 22.14.9.1 debug request during reset when the dr bit in the ocr is set, assertion of reset causes the device to enter debug mode. in this case the device may fetch the reset f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . jtag test access port and once functional description mmc2114 MMC2113 mmc2112 ? rev. 1.0 advance information motorola jtag test access port and once 601 vector and the first instruction of the reset exception handler but does not execute an instruction before entering debug mode. 22.14.9.2 debug request during normal activity setting the dr bit in the ocr during normal device activity causes the device to finish the execution of the current instruction and then enter debug mode. note that in this case the device completes the execution of the current instruction and stops after the newly fetched instruction enters the cpu instruction latch. this process is the same for any newly fetched instruction, including instructions fetched by interrupt processing or those that will be aborted by interrupt processing. 22.14.9.3 debug request during stop, doze, or wait mode setting the dr bit in the ocr when the device is in stop, doze, or wait mode (for instance, after execution of a stop, doze, or wait instruction) causes the device to exit the low-power state and enter the debug mode. note that in this case, the device completes the execution of the stop, doze, or wait instruction and halts after the next instruction enters the instruction latch. 22.14.9.4 software request during normal activity executing the bkpt instruction when the fdb (force debug enable mode) control bit in the control state register is set causes the cpu to enter debug mode after the instruction following the bkpt instruction has entered the instruction latch. 22.14.10 enabling once trace mode when the once trace mode mechanism is enabled and the trace count is greater than zero, the trace counter is decremented for each instruction executed. completing execution of an instruction when the trace counter is zero causes the cpu to enter debug mode. note: only instructions actually executed cause the trace counter to decrement. an aborted instruction does not decrement the trace counter and does not invoke debug mode. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . advance information mmc2114 MMC2113 mmc2112 ? rev. 1.0 602 jtag test access port and once motorola jtag test access port and once 22.14.11 enabling once memory breakpoints when the once memory breakpoint mechanism is enabled with a breakpoint counter value of zero, the device enters debug mode after completing the execution of the instruction that caused the memory breakpoint to occur. in case of breakpoints on instruction fetches, the breakpoint is acknowledged immediately after the execution of the fetched instruction. in case of breakpoints on data memory addresses, the breakpoint is acknowledged after the completion of the memory access instruction. 22.14.12 pipeline information and write-back bus register a number of on-chip registers store the cpu pipeline status and are configured in the cpu scan chain register (cpuscr) for access by the once controller. the cpuscr is used to restore the pipeline and resume normal device activity upon return from debug mode. the cpuscr also provides a mechanism for the emulator software to access processor and memory contents. figure 22-14 shows the block diagram of the pipeline information registers contained in the cpuscr. figure 22-14. cpu scan chain register (cpuscr) ctl wbbr 31 0 0 psr 31 0 pc 31 0 15 ir 0 15 tdo tdi f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . jtag test access port and once functional description mmc2114 MMC2113 mmc2112 ? rev. 1.0 advance information motorola jtag test access port and once 603 22.14.12.1 program counter register the program counter register (pc) is a 32-bit latch that stores the value in the cpu program counter when the device enters debug mode. the cpu pc is affected by operations performed during debug mode and must be restored by the external command controller when the cpu returns to normal mode. 22.14.12.2 instruction register the instruction register (ir) provides a mechanism for controlling the debug session. the ir allows the debug control block to execute selected instructions; the debug control module provides single-step capability. when scan-out begins, the ir contains the opcode of the next instruction to be executed at the time debug mode was entered. this opcode must be saved in order to resume normal execution at the point debug mode was entered. on scan-in, the ir can be filled with an opcode selected by debug control software in preparation for exiting debug mode. selecting appropriate instructions allows a user to examine or change memory locations and processor registers. once the debug session is complete and normal processing is to be resumed, the ir can be loaded with the value originally scanned out. 22.14.12.3 control state register the control state register (ctl) is used to set control values when debug mode is exited. on scan-in, this register is used to control specific aspects of the cpu. certain bits reflect internal processor status and should be restored to their original values. the ctl register is a 16-bit latch that stores the value of certain internal cpu state variables before debug mode is entered. this register is affected by the operations performed during the debug session and should be restored by the external command controller when returning to normal mode. in addition to saved internal state variables, the bits are used by emulation firmware to control the debug process. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . advance information mmc2114 MMC2113 mmc2112 ? rev. 1.0 604 jtag test access port and once motorola jtag test access port and once reserved bits represent the internal processor state. restore these bits to their original value after a debug session is completed, for example, when a once command is issued with the go and ex bits set and not ignored. set these bits to 1s while instructions are executed during a debug session. ffy ? feed forward y operand bit this control bit is used to force the content of the wbbr to be used as the y operand value of the first instruction to be executed following an update of the cpuscr. this gives the debug firmware the capability of updating processor registers by initializing the wbbr with the desired value, setting the ffy bit, and executing a mov instruction to the desired register. fdb ? force debug enable mode bit setting this control bit places the processor in debug enable mode. in debug enable mode, execution of the bkpt instruction as well as recognition of the brkrq input causes the processor to enter debug mode, as if the dbgrq input had been asserted. sz1 and sz0 ? prefetch size field this control field is used to drive the cpu siz1 and siz0 outputs on the first instruction pre-fetch caused by issuing a once command with the go bit set and not ignored. it should be set to indicate a 16-bit size, for example, 0b10. this field should be restored to its original value after a debug session is completed, for example, when a once command is issued with the go and ex bits set and not ignored. bit 15 14 13 12 11 10 9 bit 8 read: rsvd rsvd rsvd rsvd rsvd rsvd rsvd ffy write: reset: 0 bit 7654321bit 0 read: fdb sz1 sz0 tc2 tc1 tc0 rsvd rsvd write: reset:000000 figure 22-15. control state register (ctl) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . jtag test access port and once functional description mmc2114 MMC2113 mmc2112 ? rev. 1.0 advance information motorola jtag test access port and once 605 tc ? prefetch transfer code this control field is used to drive the cpu tc2 ? tc0 outputs on the first instruction pre-fetch caused by issuing a once command with the go bit set and not ignored. it should typically be set to indicate a supervisor instruction access, for example, 0b110. this field should be restored to its original value after a debug session is completed, for example, when a once command is issued with the go and ex bits set and not ignored. 22.14.12.4 writeback bus register the writeback bus register (wbbr) is a means of passing operand information between the cpu and the external command controller. whenever the external command controller needs to read the contents of a register or memory location, it forces the device to execute an instruction that brings that information to wbbr. for example, to read the content of processor register r0, a mov r0,r0 instruction is executed, and the result value of the instruction is latched into the wbbr. the contents of wbbr can then be delivered serially to the external command controller. to update a processor resource, this register is initialized with a data value to be written, and a mov instruction is executed which uses this value as a write-back data value. the ffy bit in the ctl register forces the value of the wbbr to be substituted for the normal source value of a mov instruction, thus allowing updates to processor registers to be performed. 22.14.12.5 processor status register the processor status register (psr) is a 32-bit latch used to read or write the m core processor status register. whenever the external command controller needs to save or modify the contents of the m core processor status register, the psr is used. this register is affected by the operations performed in debug mode and must be restored by the external command controller when returning to normal mode. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . advance information mmc2114 MMC2113 mmc2112 ? rev. 1.0 606 jtag test access port and once motorola jtag test access port and once 22.14.13 instruction address fifo buffer (pc fifo) to ease debugging activity and keep track of program flow, a first-in-first-out (fifo) buffer stores the addresses of the last eight instruction change-of-flow prefetches that were issued. the fifo is a circular buffer containing eight 32-bit registers and one 3-bit counter. all the registers have the same address, but any read access to the fifo address causes the counter to increment and point to the next fifo register. the registers are serially available to the external command controller through the common fifo address. figure 22-16 shows the structure of the pc fifo. figure 22-16. once pc fifo pc fifo register 0 tdo tclk instruction fetch address circular buffer pointer pc fifo register 1 pc fifo register 2 pc fifo register 3 pc fifo register 4 pc fifo register 5 pc fifo register 6 pc fifo register 7 pc fifo shift register f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . jtag test access port and once functional description mmc2114 MMC2113 mmc2112 ? rev. 1.0 advance information motorola jtag test access port and once 607 the fifo is not affected by operations performed in debug mode, except for incrementing the fifo pointer when the fifo is read. when debug mode is entered, the fifo counter points to the fifo register containing the address of the oldest of the eight change-of-flow pre-fetches. the first fifo read obtains the oldest address, and the following fifo reads return the other addresses from the oldest to the newest, in order of execution. to ensure fifo coherence, a complete set of eight reads of the fifo must be performed. each read increments the fifo pointer, causing it to point to the next location. after eight reads, the pointer points to the same location as before the start of the read procedure. the data in the fifo is not affected by the read operations. 22.14.14 reserved test control registers the reserved test control registers (mem_bist, ftcr, and lsrl) are reserved for factory testing. caution: to prevent damage to the device or system, do not access these registers during normal operation. 22.14.15 serial protocol the serial protocol permits an efficient means of communication between the once external command controller and the mcu. before starting any debugging activity, the external command controller must wait for an acknowledgment that the device has entered debug mode. the external command controller communicates with the device by sending 8-bit commands to the once command register and 16 to 128 bits of data to one of the other once registers. both commands and data are sent or received lsb first. after sending a command, the external command controller must wait for the processor to acknowledge execution of certain commands before it can properly access another once register. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . advance information mmc2114 MMC2113 mmc2112 ? rev. 1.0 608 jtag test access port and once motorola jtag test access port and once 22.14.16 once commands the once commands can be classified as: read commands (the device delivers the required data) write commands (the device receives data and writes the data in one of the once registers) commands with no associated data transfers 22.14.17 target site debug system requirements a typical debug environment consists of a target system in which the mcu resides in the user-defined hardware. the external command controller acts as the medium between the mcu target system and a host computer. the external command controller circuit acts as a serial debug port driver and host computer command interpreter. the controller issues commands based on the host computer inputs from a user interface program which communicates with the user. 22.14.18 interface connector for jtag/once serial port figure 22-17 shows the recommended connector pinout and interface requirements for debug controllers that access the jtag/once port. the connector has two rows of seven pins with 0.1-inch center-to-center spacing between pins in each row and each column. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . jtag test access port and once functional description mmc2114 MMC2113 mmc2112 ? rev. 1.0 advance information motorola jtag test access port and once 609 figure 22-17. recommended connector interface to jtag/once port tdi tdo tclk gpio/si target_reset key (no connect) gnd 12 34 56 78 910 10 k ? 10 k ? top view 11 12 13 14 target v dd gpio/so de (0.1 inch center-to-center) 10 k ? 10 k ? target v dd target v dd trst 10 k ? tms 10 k ? note: gpio/si and gpio/so are not required for once operation at this time. these pins can be used for high-speed downloads with a recommended interface. 10 k ? wired or with target reset circuit. this signal must be able to assert/monitor system reset. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . advance information mmc2114 MMC2113 mmc2112 ? rev. 1.0 610 jtag test access port and once motorola jtag test access port and once f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . mmc2114 ? MMC2113 mmc2112 ? rev. 1.0 advance information motorola preliminary electrical specifications 611 pre limin ary advance information ? mmc2114, MMC2113, and mmc2112 section 23. preliminary electrical specifications 23.1 contents 23.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .612 23.3 absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . .613 23.4 thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . .614 23.5 junction temperature determination . . . . . . . . . . . . . . . . . . .614 23.6 electrostatic discharge (esd) protection . . . . . . . . . . . . . . . .615 23.7 dc electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . 616 23.8 pll electrical specifications. . . . . . . . . . . . . . . . . . . . . . . . . . 618 23.9 qadc electrical characteristics . . . . . . . . . . . . . . . . . . . . . . .620 23.10 flash memory characteristics . . . . . . . . . . . . . . . . . . . . . . .624 23.11 external interface timing characteristics . . . . . . . . . . . . . . . .625 23.12 general purpose i/o timing . . . . . . . . . . . . . . . . . . . . . . . . . .630 23.13 reset and configuration override timing . . . . . . . . . . . . . . .631 23.14 spi timing characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . .632 23.15 once, jtag, and boundary scan timing . . . . . . . . . . . . . . .635 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . advance information mmc2114 MMC2113 mmc2112 ? rev. 1.0 612 preliminary electrical specifications motorola preliminary electrical specifications pre limin ary 23.2 introduction this section contains electrical and specification tables and reference timing diagrams for the mmc2114 microcontroller unit (mcu). this section contains detailed information on power considerations, dc/ac electrical characteristics, and ac timing specifications of mmc2114. the electrical specifications are preliminary and are from previous designs or design simulations. these specifications may not be fully tested or guaranteed at this early stage of the product life cycle; however, for production silicon these specifications will be met. finalized specifications will be published after complete characterization and device qualifications have been completed. note: the parameters specified in this mcu document supersede any values found in the module specifications. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . preliminary electrical specifications absolute maximum ratings mmc2114 MMC2113 mmc2112 ? rev. 1.0 advance information motorola preliminary electrical specifications 613 pre limin ary 23.3 absolute maximum ratings maximum ratings are the extreme limits to which the mcu can be exposed without permanently damaging it. see table 23-1 . the mcu contains circuitry to protect the inputs against damage from high static voltages; however, do not apply voltages higher than those shown in the table. keep v in and v out within the range v ss (v in or v out ) v dd . connect unused inputs to the appropriate voltage level, either v ss or v dd . this device is not guaranteed to operate properly at the maximum ratings. refer to 23.7 dc electrical specifications for guaranteed operating conditions. table 23-1. absolute maximum ratings parameter symbol value unit supply voltage v dd ? 0.3 to +4.0 v clock synthesizer (pll) supply voltage v dd ? 0.3 to +4.0 v ram memory standby supply voltage v stby ? 0.3 to + 4.0 v flash memory supply voltage v ddf ? 0.3 to +4.0 v analog supply voltage v dda ? 0.3 to +6.0 v analog reference supply voltage v rh ? 0.3 to +6.0 v analog esd protection voltage v ddh ? 0.3 to +6.0 v digital input voltage (1) 1. input must be current limited to the value specified. to determine the value of the required current-limiting resistor, calculate resistance values for positive and negative clamp voltages, then use the larger of the two values. v in ? 0.3 to + 5.0 v analog input voltage v ain ? 0.3 to + 6.0 v instantaneous maximum current single pin limit (applies to all pins) (2), (3) 2. all functional non-supply pins are internally clamped to v ss and v dd . 3. power supply must maintain regulation within operating v dd range during instantaneous and operating maximum current conditions. if positive injection current (v in > v dd ) is greater than i dd , the injection current may flow out of v dd and could result in external power supply going out of regulation. ensure external v dd load will shunt current greater than maximum injection current. this will be the greatest risk when the mcu is not consuming power (ex; no clock). power supply must maintain regulation within operating v dd range during instantaneous and operating maximum current conditions. i d 25 ma operating temperature range (packaged) t a (t l to t h ) ? 40 to 85 c storage temperature range t stg ? 65 to 150 c f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . advance information mmc2114 ? MMC2113 mmc2112 ? rev. 1.0 614 preliminary electrical specifications motorola preliminary electrical specifications pre limin ary 23.4 thermal characteristics 23.5 junction temperature determination table 23-2. thermal characteristics parameter symbol value unit thermal resistance plastic 100-pin lqfp surface mount plastic 144-pin lqfp surface mount plastic 196-ball m apbga ja 44 46 60 c/w the average chip-junction temperature (t j ) in c can be obtained from: t j = t a + p d x ja (1) where: t a = ambient temperature, c ja = package thermal resistance, junction-to-ambient, c/w p d = p int + p i/o p int = i dd v dd , watts ? chip internal power p i/o = power dissipation on input and output pins ? user determined for most applications, p i/o < p int and can be neglected. an approximate relationship between p d and t j (if p i/o is neglected) is: p d = k (t j + 273 c) (2) solving equations 1 and 2 for k gives: k = p d (t a + 273 c) + ja p d (3) where k is a constant pertaining to the particular part. k can be determined from equation (3) by measuring p d (at equilibrium) for a known t a . using this value of k, the values of p d and t j can be obtained by solving equations (1) and (2) iteratively for any value of t a . f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . preliminary electrical specifications electrostatic discharge (esd) protection mmc2114 MMC2113 mmc2112 ? rev. 1.0 advance information motorola preliminary electrical specifications 615 pre limin ary 23.6 electrostatic discharge (esd) protection table 23-3. esd protection characteristics parameter (1) (2) 1. all esd testing is in conformity with cdf-aec-q100 stress test qualification for automotive grade integrated circuits. 2. a device will be defined as a failure if after exposure to esd pulses the device no longer meets the device specification requirements. complete dc parametric and functional testing shall be performed per applicable device specification at room temperature followed by hot temperature, unless specified otherwise in the device specification. symbol value units esd target for human body model hbm 2000 v esd target for machine model mm 200 v hbm circuit description r series 1500 w c 100 pf mm circuit description r series 0w c 200 pf number of pulses per pin (hbm) positive pulses negative pulses ? 1 1 ? number of pulses per pin (mm) positive pulses negative pulses ? 3 3 ? interval of pulses ? 1sec f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . advance information mmc2114 MMC2113 mmc2112 ? rev. 1.0 616 preliminary electrical specifications motorola preliminary electrical specifications pre limin ary 23.7 dc electrical specifications table 23-4. dc electrical specifications (1) (v ss = v ssf = v ssa = 0 v, t a = t l to t h ) parameter symbol min max unit input high voltage v ih 0.7 x v dd 5v input low voltage v il v ss ? 0.3 0.35 x v dd v input hysteresis v hys 0.06 x v dd ? v input leakage current, v in = v dd or v ss , input-only pins i in ? 1.0 1.0 a high impedance (off-state) leakage current v in = v dd or v ss , all input/output and output pins i oz ? 1.0 1.0 a output high voltage (all input/output and all output pins) i oh = ? 2.0 ma v oh v dd ? 0.5 ? v output low voltage (all input/output and all output pins) i ol = 2.0 ma v ol ? 0.5 v weak internal pullup device current, tested at v il maximum i apu ? 10 ? 130 a input capacitance all input-only pins all input/output (three-state) pins c in ? ? 7 7 pf load capacitance 50% partial drive 100% full drive c l ? ? 25 50 pf supply voltage, includes core modules and pads v dd 2.7 3.6 v ram memory standby supply voltage normal operation: v dd > v stby ? 0.3 v standby mode: v dd < v stby ? 0.3 v v stby 0.0 2.7 3.6 3.6 v flash memory supply voltage v ddf 2.7 3.6 v low-voltage detect trip voltage (v dd falling) v ldv 2.00 2.20 v low-voltage detect hysteresis (v dd rising) v hys 60 100 mv v dd slew rate (rising or falling) for lvd recognition v slewlvd ? 5kv/ms operating supply current, external oscillator clocking (2) master mode single-chip mode wait mode doze mode stop mode i dd ? ? ? ? ? 60 40 15 10 200 ma ma ma ma a continued on next page f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . preliminary electrical specifications dc electrical specifications mmc2114 ? MMC2113 mmc2112 ? rev. 1.0 advance information motorola preliminary electrical specifications 617 pre limin ary operating supply current, crystal/pll clocking (3) master mode single-chip mode wait mode doze mode stop mode osc and pll enabled osc enabled, pll disabled osc and pll disabled i ddxtal ? ? ? ? ? ? ? 64 44 19 14 2 1 200 ma ma ma ma ma ma a ram memory standby supply current normal operation: v dd > v stby ? 0.3 v transient condition: v stby ? 0.3 v > v dd > v ss + 0.5 v standby operation: v dd < v ss + 0.5 v i stby ? ? ? 10 7 20 a ma a flash memory supply current (4) read program erase or mass erase stop mode i ddf ? ? ? ? 5 28 20 1 ma ma ma a analog supply current normal operation stop mode i dda ? ? 2 10.0 ma a esd supply current normal operation stop mode i ddh ? ? 800 10 a dc injection current (4), (5), (6) v negclamp = v ss ? 0.3 v, v posclamp = v dd + 0.3 single pin limit total mcu limit, includes sum of all stressed pins i ic ? 1.0 ? 10 1.0 10 ma 1. refer to table 23-5 through table 23-10 for additional pll, qadc and flash specifications. 2. current measured at maximum system clock frequency (unless indicated otherwise), all modules active, and default drive strength with matching load. 3. current measured at f sys = 32 mhz derived from 8.00 mhz crystal and pll, all modules active, and default drive strength with matching load. 4. all functional non-supply pins are internally clamped to v ss and their respective v dd . 5. input must be current limited to the value specified. to determine the value of the required current-limiting resistor, calc ulate resistance values for positive and negative clamp voltages, then use the larger of the two values. 6. power supply must maintain regulation within operating v dd range during instantaneous and operating maximum current conditions. if positive injection current (v in > v dd ) is greater than i dd , the injection current may flow out of v dd and could result in external power supply going out of regulation. ensure external v dd load will shunt current greater than maximum injection current. this will be the greatest risk when the mcu is not consuming power. examples are: if no system clock is present, or if clock rate is very low which would reduce overall power consumption. also, at power-up, system clock is not present during the power-up sequence until the pll has attained lock. table 23-4. dc electrical specifications (1) (continued) (v ss = v ssf = v ssa = 0 v, t a = t l to t h ) parameter symbol min max unit f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . advance information mmc2114 MMC2113 mmc2112 ? rev. 1.0 618 preliminary electrical specifications motorola preliminary electrical specifications pre limin ary 23.8 pll electrical specifications table 23-5. pll electrical specifications (v dd = 2.7 to 3.6 v, v ss = 0 v, t a = t l to t h ) characteristic symbol min max unit pll reference frequency range crystal reference (1) external reference 1:1 mode f ref_crystal f ref_ext f ref_1:1 2 2 10 10 10 33 mhz system frequency (2) external reference on-chip pll frequency f sys 0 3/64 33 33 mhz loss of reference frequency (3), (4) f lor 100 250 khz self-clocked mode frequency (4) f scm 0.5 15 mhz crystal startup time (5), (6) t cst ? 10 ms extal input high voltage crystal mode all other modes (1:1, bypass, external) v ihext v dd ? 1.0 2.0 v dd v dd v extal input low voltage crystal mode all other modes (1:1, bypass, external) v ilext v ss v ss 1.0 0.8 v xtal output high voltage i oh = 1.0 ma v ol v dd ? 1.0 ? v xtal output low voltage i ol = 1.0 ma v ol ? 0.5 v xtal load capacitance 5 30 pf pll lock time (4), (7) t lpll ? 200 s powerup to lock time (4), (5), (8) with crystal reference (includes p5 time) without crystal reference t lplk ? ? 11 200 ms s 1:1 clock skew (between clkout and extal) (9) t skew ? 22ns duty cycle of reference (4) t dc 40 60 % f sys frequency unlock range f ul ? 1.5 1.5 % f sys frequency lock range f lck ? 0.75 0.75 % f sys continued on next page f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . preliminary electrical specifications pll electrical specifications mmc2114 MMC2113 mmc2112 ? rev. 1.0 advance information motorola preliminary electrical specifications 619 pre limin ary clkout period jitter (4), (5), (7), (10) measured at f sys max peak-to-peak jitter (clock edge to clock edge) long term jitter (averaged over 2 ms interval) c jitter ? ? 5 0.01 % f sys 1. when the mfd in the pll is set to 000, the minimum crystal reference frequency is 3 mhz. 2. all internal registers retain data at 0 hz. 3. ? loss of reference frequency ? is the reference frequency detected internally, which transitions the pll into self-clocked mode. 4. self-clocked mode frequency is the frequency that the pll operates at when the reference frequency falls below f lor with default mfd/rfd settings. 5. this parameter is characterized before qualification rather than 100% tested. 6. proper pc board layout procedures must be followed to achieve specifications. 7. this specification applies to the period required for the pll to relock after changing the mfd frequency control bits in the synthesizer control register (syncr). 8. assuming a reference is available at powerup, lock time is measured from the time v dd and v dd are valid to rstout negating. if the crystal oscillator is being used as the reference for the pll, then the crystal start up time must be added to the pll lock time to determine the total start-up time. 9. pll is operating in 1:1 pll mode. 10. jitter is the average deviation from the programmed frequency measured over the specified interval at maximum f sys . measurements are made with the device powered by filtered supplies and clocked by a stable external clock signal. noise injected into the pll circuitry via v dd and v ss and variation in crystal oscillator frequency increase the c jitter percentage for a given interval. table 23-5. pll electrical specifications (continued) (v dd = 2.7 to 3.6 v, v ss = 0 v, t a = t l to t h ) characteristic symbol min max unit f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . advance information mmc2114 MMC2113 mmc2112 ? rev. 1.0 620 preliminary electrical specifications motorola preliminary electrical specifications pre limin ary 23.9 qadc electrical characteristics the qadc electrical characteristics are shown in table 23-6 , table 23-7 , and table 23-8 . table 23-6. qadc absolute maximum ratings parameter symbol min max unit analog supply, with reference to v ssa v dda ? 0.3 6.0 v internal digital supply (1) with reference to v ss v dd ? 0.3 4.0 v reference supply with reference to v rl v rh ? 0.3 6.0 v v ss differential voltage v ss ? v ssa ? 0.1 0.1 v v dd differential voltage (2) v dd ? v dda ? 6.0 4.0 v v ref differential voltage v rh ? v rl ? 0.3 6.0 v v rh to v dda differential voltage (2) v rh ? v dda ? 6.0 6.0 v v rl to v ssa differential voltage v rl ? v ssa ? 0.3 0.3 v v ddh to v dda differential voltage v ddh ? v dda ? 1.0 1.0 v maximum input current (3), (4), (5) i ma ? 25 25 ma 1. for internal digital supply of v dd = 3.3 v typical 2. refers to allowed random sequencing of power supplies 3. transitions within the limit do not affect device reliability or cause permanent damage. exceeding limit may cause permanent conversion error on stressed channels and on unstressed channels. 4. input must be current limited to the value specified. to determine the value of the required current-limiting resistor, calc ulate resistance values using v posclamp = v dda + 0.3 v and v negclamp = ? 0.3 v, then use the larger of the calculated values. 5. condition applies to one pin at a time. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . preliminary electrical specifications qadc electrical characteristics mmc2114 MMC2113 mmc2112 ? rev. 1.0 advance information motorola preliminary electrical specifications 621 pre limin ary table 23-7. qadc electrical specifications (operating) (v ddh and v dda = 5.0 vdc analog supply v dda 4.5 5.5 v v ss differential voltage v ss ? v ssa ? 100 100 mv reference voltage low (2) v rl v ssa v ssa + 0.1 v reference voltage high (2) v rh v dda ? 0.1 v dda v v ref differential voltage v rh ? v rl 4.5 5.5 v input voltage v indc v ssa ? 0.3 v dda +0.3 v input high voltage, pqa and pqb v ih 0.7 (v dda )v dda +0.3 v input low voltage, pqa and pqb v il v ssa ? 0.3 0.4 (v dda ) v input hysteresis, pqa and pqb (3) v hys 0.5 ? v output low voltage, pqa and pqb (4) i ol = 2.0 ma v ol ? 0.8 v output high voltage, pqa and pqb (3) i oh = ? 2.0 ma v oh v ddh ? 0.8 ? v reference supply current, dc i ref ? 250 a reference supply current, transient i ref ? 2ma load capacitance, pqa and pqb c l ? 50 pf input current, channel off (5) pqa pqb i off ? 200 ? 150 200 150 na total input capacitance (6) pqa not sampling pqb not sampling incremental capacitance added during sampling c in ? ? ? 15 10 5 pf 1. qadc converter specifications are only guaranteed for v ddh and v dda = 5.0 v 0.5 v. v ddh and v dda may be powered down to 2.7 v with only gpio functions supported. 2. to obtain full-scale, full-range results, v ssa <= v rl <= v indc <= v rh <= v dda 3. parameter applies to these pins: port a: pqa[7:0]/an[59:58]/etrig[2:1] port b: pqb[7:0]/an[3:0]/an[51:48]/an[z:w] 4. full driver (push-pull). 5. maximum leakage occurs at maximum operating temperature. current decreases by approximately one-half for each 8 c to 12 c, in the ambient temperature range of 50 c to 125 c. 6. this parameter is characterized before qualification rather than 100% tested. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . advance information mmc2114 MMC2113 mmc2112 ? rev. 1.0 622 preliminary electrical specifications motorola preliminary electrical specifications pre limin ary table 23-8. qadc conversion specifications (operating) (v ddh and v dda = 5.0 vdc , ? v rl = 5 vdc 0.5 v, t a within operating temperature range, f sys = 16 mhz) parameter symbol min max unit qadc clock (qclk) frequency (1) f qclk 0.5 2.1 mhz conversion cycles cc 14 28 qclk cycles conversion time f qclk = 2.0 mhz (1) min = ccw/ist =%00 max = ccw/ist =%11 t conv 7.0 14.0 s stop mode recovery time t sr ? 10 s resolution (2) ? 5 ? mv absolute (total unadjusted) error (3), (4), (5), (6) f qclk = 2.0 mhz (2) two clock input sample time ae ? 22counts disruptive input injection current (7), (8), (9) i inj (10) ? 11ma current coupling ratio (11) pqa pqb k ? ? 8x10 ? 5 8x10 ? 5 incremental error due to injection current (12) all channels have same 10 k < r s < 100k channel under test has r s = 10k, i inj = i injmax , i injmin e inj ? ? + 1.0 + 1.0 counts counts source impedance at input (13) r s ? 100 k ? incremental capacitance during sampling (14) c samp ? 5pf 1. conversion characteristics vary with f qclk rate. reduced conversion accuracy occurs at max f qclk rate. using the qadc pins as gpio functions during conversions may result in degraded results. 2. at v rh ? v rl = 5.12 v, one count = 5 mv 3. accuracy tested and guaranteed at v rh ? v rl = 5.0 v 0.5 v 4. this parameter is characterized before qualification rather than 100% tested. 5. absolute error includes 1/2 count (~2.5 mv) of inherent quantization error and circuit (differential, integral, and offset) error. specification assumes that adequate low-pass filtering is present on analog input pins ? capacitive filter with 0.01 f to 0.1 f capacitor between analog input and analog ground, typical source isolation impedance of 10 k ? . 6. input signals with large slew rates or high frequency noise components cannot be converted accurately. these signals may affect the conversion accuracy of other channels. notes continued on next page f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . preliminary electrical specifications qadc electrical characteristics mmc2114 MMC2113 mmc2112 ? rev. 1.0 advance information motorola preliminary electrical specifications 623 pre limin ary 7. below disruptive current conditions, the channel being stressed has conversion values of $3ff for analog inputs greater than v rh and $000 for values less than v rl . this assumes that v rh < v dda and v rl > v ssa due to the presence of the sample amplifier. other channels are not affected by non-disruptive conditions. 8. exceeding limit may cause conversion error on stressed channels and on unstressed channels. transitions within the limit do not affect device reliability or cause permanent damage. 9. input must be current limited to the value specified. to determine the value of the required current-limiting resister, calc ulate resistance values using v posclamp = v dda + 0.5v and v negclamp = ? 0.3 v, then use the larger of the calculated values. 10. condition applies to two adjacent pins. 11. current coupling ratio, k, is defined as the ratio of the output current, i out , measured on the pin under test to the injection current, i inj , when both adjacent pins are overstressed with the specified injection current. k = i out / i inj the input voltage error on the channel under test is calculated as v err = i inj * k * r s . 12. performance expected with production silicon. 13. maximum source impedance is application-dependent. error resulting from pin leakage depends on junction leakage into the pin and on leakage due to charge-sharing with internal capacitance. error from junction leakage is a function of external source impedance and input leakage current. in this expression, expected error in result value due to junction leakage is expressed in voltage (v errj ): v errj = r s * i off where i off is a function of operating temperature. charge-sharing leakage is a function of input source impedance, conversion rate, change in voltage between successive conversions, and the size of the filtering capacitor used. error levels are best determined empirically. in general, continuous conversion of the same channel may not be compatible with high source impedance. 14. for a maximum sampling error of the input voltage <= 1 lsb, then the external filter capacitor, c f >= 1024 * c samp . the value of c samp in the new design may be reduced. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . advance information mmc2114 MMC2113 mmc2112 ? rev. 1.0 624 preliminary electrical specifications motorola preliminary electrical specifications pre limin ary 23.10 flash memory characteristics the flash memory characteristics are shown in table 23-9 and table 23-10 . table 23-9. sgfm flash program and erase characteristics (v ddf = 2.7 to 3.6 v, t a = t l to t h ) (1) parameter symbol min typ max unit system clock (read only) f sys(r) 0 ? 33 mhz system clock (program/erase) f sys(p/e) 0.15 ? 33 mhz flash statemachine clock f clk 150 ? 200 khz 1. t l is defined to be ? 40 c and t h is defined to be 85 c table 23-10. sgfm flash module life characteristics (v ddf = 2.7 to 3.6 v, t a = t l to t h ) parameter symbol value unit maximum number of guaranteed program/erase cycles (1) before failure p/e 1,000 (2) cycles data retention at average operating temperature of 85 c retention 10 years 1. a program/erase cycle is defined as switching the bits from 1 0 1. 2. reprogramming of a flash array block prior to erase is not required. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . preliminary electrical specifications external interface timing characteristics mmc2114 MMC2113 mmc2112 ? rev. 1.0 advance information motorola preliminary electrical specifications 625 pre limin ary 23.11 external interface timing characteristics table 23-11. external interface timing characteristics (v dd = 2.7 v to 3.6 v, v ss = 0 v, t a = t l to t h ) no. characteristic (1), (2) symbol min max unit 1 clkout period t cyc 30 ? ns 2 clkout low pulse width t clw 0.5 t cyc ? 1 ? ns 3 clkout high pulse width t chw 0.5 t cyc ? 1 ? ns 4all rise times t cr ? 3ns 5 all fall times t cf ? 3ns 6 clkout high to a[22:0], tsiz[1:0] valid (3) t chav ? 7ns 7 clkout high to a[22:0], tsiz[1:0] invalid t chai 0 ? ns 8 clkout high to cs[3:0] asserted (3) t chca ? 7ns 9 clkout high to cs[3:0] negated t chcn 0 ? ns 10 clkout high to cse[1:0] valid t chcev ? 7ns 11 clkout high to cse[1:0] invalid t chcei 0 ? ns 12 clkout high to tc[2:0], pstat[3:0] valid t chtv ? 12 ns 13 clkout high to tc[2:0], pstat[3:0] invalid t chti 0 ? ns 14 clkout high to r/w high hold time t chrwh 010ns 15 clkout high to r/w valid write t chrwv 0.25 t cyc 0.25 t cyc + 6 ns 16 clkout high to oe , eb asserted (3), (4), (5) t choea 0.25 t cyc 0.25 t cyc + 8 ns 17 clkout high to oe , eb read negated t choen 06ns 17a clkout low to eb write negated (4) t clen 0.25 t cyc 0.25 t cyc + 6 ns 18 clkout low to shs low t clsl 07ns 19 clkout high to shs high (6) t chsh 07ns 20 clkout low to data-out low impedance write/show t chdod 0 ? ns 21 clkout high to data-out high impedance write/show (4), (6), (7) t chdoz 210ns 22 clkout low to data-out valid write t cldovw ? 8ns 22a clkout low to data-out valid show (8) t cldovs ? 15 ns continued on next page f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . advance information mmc2114 MMC2113 mmc2112 ? rev. 1.0 626 preliminary electrical specifications motorola preliminary electrical specifications pre limin ary figure 23-1. clkout timing 23 clkout high to data-out invalid write/show (6), (7) t chdoiw 2 ? ns 24 data-in valid to clkout high read t divch 17 ? ns 25 clkout high to data-in invalid read t chdii 0 ? ns 26 ta , tea asserted to clkout high t tach 0.25 t cyc + 9 ? ns 27 clkout high to ta , tea negated t chtn 0 ? ns 1. all ac timing is shown with respect to 50% v dd levels, unless otherwise noted. 2. timing is not guaranteed during the clock cycle of mode and/or setup changes (for example, changing pin function between gpio and primary function, changing gpio between input/output functions, changing control registers that affect pin functions). 3. a[22:0], tsiz[1:0], cs[3:0] valid to r/w (write), oe , eb asserted (minimum) spec is 0 ns. this parameter is characterized before qualification rather than 100% tested. 4. write/show data high-z to oe asserted (minimum) or from eb negated (write ? maximum) spec is 0 ns. this parameter is characterized before qualification rather than 100% tested. 5. to prevent an unintentional assertion glitch of the eb pins during a synchronous reset (and before the reset overrides configure the chip in a stable mode), leave the port output data register bits associated with the eb gpo default of 1 and do not pull the pins down with a current load. 6. shs high to show data or write data invalid (minimum) spec is 0 ns. this parameter is characterized before qualification rather than 100% tested. 7. write/show data high-z and write/show data invalid is 0 ns for synchronous reset conditions. 8. t cldovs value reflects maximum specification for any bus cycle. for non-flash read cycles, t cldovs is specified at 8 ns maximum. table 23-11. external interface timing characteristics (continued) (v dd = 2.7 v to 3.6 v, v ss = 0 v, t a = t l to t h ) no. characteristic (1), (2) symbol min max unit clkout 4 2 5 3 1 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . preliminary electrical specifications external interface timing characteristics mmc2114 MMC2113 mmc2112 ? rev. 1.0 advance information motorola preliminary electrical specifications 627 pre limin ary figure 23-2. clock read/write cycle timing clkout a[22:0] cse[1:0] 7 r/w (write) oe eb[3:0] (write) shs cs3 ? cs0 d[31:0] (read) ta /tea tc[2:0], 16 17 8 9 18 19 24 25 26 27 13 6 d[31:0] (write) 22 23 eb[3:0] (read) 17a r/w (read) 15 14 tsiz[1:0] 11 10 pstat[3:0] 20 21 12 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . advance information mmc2114 MMC2113 mmc2112 ? rev. 1.0 628 preliminary electrical specifications motorola preliminary electrical specifications pre limin ary figure 23-3. read/write cycle timing with wait states clkout a[22:0] cse[1:0] 7 r/w (write) oe eb[3:0] (write) shs cs3 ? cs0 d[31:0] (read) ta /tea tc[2:0], 16 17 8 9 18 19 24 25 26 27 13 6 d[31:0] (write) 22 23 eb[3:0] (read) 17a r/w (read) 15 14 tsiz[1:0] 11 10 pstat[3:0] 20 21 12 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . preliminary electrical specifications external interface timing characteristics mmc2114 MMC2113 mmc2112 ? rev. 1.0 advance information motorola preliminary electrical specifications 629 pre limin ary figure 23-4. show cycle timing clkout a[22:0] cse[1:0] 7 r/w (write) oe eb[3:0] shs cs3 ? cs0 ta /tea tc[2:0], 18 19 13 6 d[31:0] (write) 22a 23 r/w (read) 15 14 tsiz[1:0] 11 10 pstat[3:0] 20 21 12 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . advance information mmc2114 MMC2113 mmc2112 ? rev. 1.0 630 preliminary electrical specifications motorola preliminary electrical specifications pre limin ary 23.12 general purpose i/o timing figure 23-5. gpio timing table 23-12. gpio timing (1) (v dd = 2.7 to 3.6 v, v ss = 0 v, t a = t l to t h ) (2) no. characteristic symbol min max unit g1 clkout high to gpio output valid t chpov ? 20 ns g2 clkout high to gpio output invalid t chpoi 0 ? ns g3 gpio input valid to clkout high t pvch 10 ? ns g4 clkout high to gpio input invalid t chpi 2 ? ns ga1 clkout high to pqa output valid t chpaov ? 20 ns ga2 clkout high to pqa output invalid t chpaoi 0 ? ns ga3 pqa/pqb input valid to clkout low t pavch 10 ? ns ga3 clkout low to pqa/pqb input invalid t chpai 2 ? ns 1. gpio pins include: ports a ? i, edge port (including int functions), spi, sci1, and sci2 (including sci functions), and timer 1 and timer 2 (including timer functions). 2. all ac timing is shown with respect to 50% v dd levels unless otherwise noted. g1 clkout gpio outputs g2 pqa outputs ga2 ga3 ga4 pqa/pqb inputs g3 g4 gpio inputs ga1 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . preliminary electrical specifications reset and configuration override timing mmc2114 MMC2113 mmc2112 ? rev. 1.0 advance information motorola preliminary electrical specifications 631 pre limin ary 23.13 reset and configuration override timing figure 23-6. reset and configuration override timing table 23-13. reset and configuration override timing (v dd = 2.7 to 3.6 v, v ss = 0 v, t a = t l to t h ) no. parameter (1) symbol min max unit r1 reset input asserted to clkout high t rach 10 ? ns r2 clkout high to reset input negated t chrn 2 ? ns r3 reset input assertion time (2) t riat 5 ? t cyc r4 clkout high to rstout valid (3) t chrov ? 20 ns r5 rstout asserted to configuration overrides asserted t roaca 0 ? ns r6 configuration override setup time to rstout negated t cos 20 ? t cyc r7 configuration override hold time after rstout negated t coh 0 ? ns r8 rstout negated to configuration override high impedance t roncz ? 1 t cyc 1. all ac timing is shown with respect to 50% v dd levels, unless otherwise noted. 2. during low-power stop, the synchronizers for the reset input are bypassed and reset is asserted asynchronously to the system. thus, reset must be held a minimum of 100 ns. 3. this parameter also covers the timing of the show interrupt function. r1 r2 clkout reset rstout r3 r4 r8 r7 r6 r5 configuration overrides r4 (rcon , d[28, 26, 23:21, 19:16]) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . advance information mmc2114 MMC2113 mmc2112 ? rev. 1.0 632 preliminary electrical specifications motorola preliminary electrical specifications pre limin ary 23.14 spi timing characteristics table 23-14. spi timing characteristics (v dd = 2.7 to 3.6 v, v ss = 0 v, t a = t l to t h ) no. function (1) symbol min max unit ? operating frequency master slave f op dc dc 1 / 2 x f sys 1 / 2 x f sys system frequency 1 sck period master slave t sck 2 2 2048 ? t cyc t cyc 2 enable lead time master slave t lead 1 / 2 1 ? ? t sck t cyc 3 enable lag time master slave t lag 1 / 2 1 ? ? t sck t cyc 4 clock (sck) high or low time master slave t wsck t cyc ? 30 t cyc ? 30 1024 t cyc ? ns 5 data setup time, inputs master slave t su 25 25 ? ? ns 6 data hold time, inputs master slave t high 0 25 ? ? ns 7 slave access time t a ? 1 t cyc 8 slave miso disable time t dis ? 1 t cyc 9 data valid after sck edge master slave t v ? ? 25 25 ns 10 data hold time, outputs master slave t hold 0 0 ? ? ns 11 rise time input output t ri t ro ? ? t cyc ? 25 25 ns 12 fall time input output t fi t fo ? ? t cyc ? 25 25 ns 1. all ac timing is shown with respect to 50% v dd unless otherwise noted. timing is based on wired-or mode being off. with wired-or mode on, timing will depend on pullup value. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . preliminary electrical specifications spi timing characteristics mmc2114 MMC2113 mmc2112 ? rev. 1.0 advance information motorola preliminary electrical specifications 633 pre limin ary a) spi master timing (cpha = 0) b) spi master timing (cpha = 1) figure 23-7. spi timing diagram (sheet 1 of 2) sck output sck output miso input mosi output ss (1) output 1 9 5 6 msb in 2 bit 6 . . . 1 lsb in msb out 2 lsb out bit 6 . . . 1 10 4 4 2 9 cpol = 0 cpol = 1 3 11 12 1. ss output mode (dds7 = 1, ssoe = 1) 2. lsbf = 0. for lsbf = 1, bit order is lsb, bit 1, ..., bit 6, msb. notes: sck output sck output miso input mosi output 1 5 6 msb in 2 bit 6 . . . 1 lsb in master msb out 2 master lsb out bit 6 . . . 1 4 4 9 11 12 10 port data cpol = 0 cpol = 1 port data ss (1) output 2 12 11 3 1. ss output mode (dds7 = 1, ssoe = 1) 2. lsbf = 0. for lsbf = 1, bit order is lsb, bit 1, ..., bit 6, msb. notes: f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . advance information mmc2114 MMC2113 mmc2112 ? rev. 1.0 634 preliminary electrical specifications motorola preliminary electrical specifications pre limin ary a) spi slave timing (cpha = 0) b) spi slave timing (cpha = 1) figure 24-7. spi timing diagram (sheet 2 of 2) sck input sck input mosi input miso output ss input 1 9 5 6 msb in bit 6 . . . 1 lsb in msb out slave lsb out bit 6 . . . 1 10 4 4 2 7 cpol = 0 cpol = 1 3 12 note: not defined, but normally msb of character just received slave 12 11 10 see 11 note 8 sck input sck input mosi input miso output 1 5 6 msb in bit 6 . . . 1 lsb in msb out slave lsb out bit 6 . . . 1 4 4 9 11 12 10 see cpol = 0 cpol = 1 ss input 2 12 11 3 note: not defined, but normally lsb of character just received slave note 7 8 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . preliminary electrical specifications once, jtag, and boundary scan timing mmc2114 MMC2113 mmc2112 ? rev. 1.0 advance information motorola preliminary electrical specifications 635 pre limin ary 23.15 once, jtag, and boundary scan timing figure 23-8. test clock input timing table 23-15. once, jtag, and boundary scan timing (v dd = 2.7 to 3.6 v, v ss = 0 v, t a = t l to t h ) no. characteristics symbol min max unit 1 tclk frequency of operation f jcyc dc 1/2 x f sys mhz 2 tclk cycle period t jcyc 2 ? t cyc 3 tclk clock pulse width t jcw 25 ? ns 4 tclk rise and fall times t jcrf 03ns 5 boundary scan input data setup time to tclk rise t bsdst 5 ? ns 6 boundary scan input data hold time after tclk rise t bsdht 24 ? ns 7 tclk low-to-boundary scan output data valid t bsdv 040ns 8 tclk low-to-boundary scan output high z t bsdz 040ns 9 tms, tdi, and de input data setup time to tclk rise (1) t tapdst 7 ? ns 10 tms, tdi, and de input data hold time after tclk rise (1) t tapdht 15 ? ns 11 tclk low to tdo data valid t tdodv 025ns 12 tclk low to tdo high z t tdodz 09ns 13 trst assert time t trstat 100 ? ns 14 trst setup time (negation) to tclk high t trstst 10 ? ns 15 de input data setup time to clkout rise (1) t dedst 10 ? ns 16 de input data hold time after clkout rise (1) t dedht 2 ? ns 17 clkout high to de data valid t dedv 020ns 18 clkout high to de high z t dedz 010ns 1. parameters 9 and 10 apply to the de pin when used to enable once. parameters 15 and 16 apply to the de pin when used to request the processor to enter debug mode. tclk input v il v ih 44 2 3 3 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . advance information mmc2114 MMC2113 mmc2112 ? rev. 1.0 636 preliminary electrical specifications motorola preliminary electrical specifications pre limin ary figure 23-9. boundary scan (jtag) timing figure 23-10. test access port timing figure 23-11. trst timing input data valid output data valid output data valid tclk data inputs data outputs data outputs data outputs v il v ih 7 8 7 56 input data valid output data valid output data valid tclk tdi tdo tdo tdo tms v il v ih de 11 12 11 910 tclk trst 14 13 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . preliminary electrical specifications once, jtag, and boundary scan timing mmc2114 MMC2113 mmc2112 ? rev. 1.0 advance information motorola preliminary electrical specifications 637 pre limin ary figure 23-12. debug event pin timing input data valid output data valid output data valid v il v ih clkout de de de de input 17 18 17 15 16 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . advance information mmc2114 MMC2113 mmc2112 ? rev. 1.0 638 preliminary electrical specifications motorola preliminary electrical specifications pre limin ary f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . mmc2114 MMC2113 mmc2112 ? rev. 1.0 advance information motorola mechanical specifications 639 advance information ? mmc2114, MMC2113, and mmc2112 section 24. mechanical specifications 24.1 contents 24.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .639 24.3 bond pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .640 24.4 package information for the 144-pin lqfp . . . . . . . . . . . . . .641 24.5 package information for the 100-pin lqfp . . . . . . . . . . . . . .641 24.6 package information for the 196-ball mapbga . . . . . . . . . . .642 24.7 144-pin lqfp mechanical drawing . . . . . . . . . . . . . . . . . . . .643 24.8 100-pin lqfp mechanical drawing . . . . . . . . . . . . . . . . . . . .644 24.9 196-ball mapbga mechanical drawing. . . . . . . . . . . . . . . . .645 24.2 introduction the mmc2114, MMC2113, and mmc2112 are available in three types of packages: 1. 100-pin low-profile quad flat pack (lqfp) version supporting single-chip mode of operation 2. 144-pin lqfp version supporting: ? single-chip operation with extra general-purpose input/output ? expanded master mode for interfacing to external memories ? emulation mode for development and debug 3. 196-ball mold array process ball grid array (mapbga) version supporting: ? single-chip operation with extra general-purpose input/output ? expanded master mode for interfacing to external memories ? emulation mode for development and debug f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . advance information mmc2114 MMC2113 mmc2112 ? rev. 1.0 640 mechanical specifications motorola mechanical specifications this section shows the latest package specifications available at the time of this publication. to make sure that you have the latest information, contact one of the following: local motorola sales office world wide web at http://www.motorola.com/semiconductors/ follow the world wide web on-line instructions to retrieve the current mechanical specifications. 24.3 bond pins the die has a total of 144 bond pads. of these, the pads that are not bonded out in the 100-pin package are distributed around the circumference of the die. this optional group of pins includes: a[22:0] r/w eb[3:0] cse[1:0] tc[2:0] oe cs[3:0] 3 x v dd 3 x v ss for more detailed information, see section 3. signal description . f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . mechanical specifications package information for the 144-pin lqfp mmc2114 MMC2113 mmc2112 ? rev. 1.0 advance information motorola mechanical specifications 641 24.4 package information for the 144-pin lqfp the production 144-pin package characteristics are: joint-electron device engineering council (jedec) standard low-profile quad flat pack (lqfp) dimension: 20 x 20 mm lead pitch: 0.5 mm thin: 1.4 mm case number: 918-03 clam shell socket: yamaichi part #ic51-1444-1354 open face socket: yamaichi part #ic201-1444-034 24.5 package information for the 100-pin lqfp the production 100-pin package characteristics are: jedec standard low-profile quad flat pack (lqfp) dimension: 14 x 14 mm lead pitch: 0.5 mm thin: 1.4 mm case number: 983-02 clam shell socket: yamaichi part #ic51-1004-809 open face socket: yamaichi part #ic201-1004-008 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . advance information mmc2114 MMC2113 mmc2112 ? rev. 1.0 642 mechanical specifications motorola mechanical specifications 24.6 package information for the 196-ball mapbga the production 196-pin package characteristics are: jedec standard 196-ball plastic mold array process ball grid array (mapbga) dimension: 15 x 15 ball pitch: 1 mm thickness: 1.6 mm case number: 1128c-02 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . mechanical specifications 144-pin lqfp mechanical drawing mmc2114 MMC2113 mmc2112 ? rev. 1.0 advance information motorola mechanical specifications 643 24.7 144-pin lqfp mechanical drawing n 0.20 t l-m 144 gage plane 73 109 37 seating 108 1 36 72 plane 4x 4x 36 tips pin 1 ident view y b b1 v1 a1 s1 v p g a s 0.1 c 2 q view ab j1 j1 140x 4x view y plating f aa j d base metal section j1-j1 (rotated 90 ) 144 pl n 0.08 m tl-m q dim a min max 20.00 bsc millimeters a1 10.00 bsc b 20.00 bsc b1 10.00 bsc c 1.40 1.60 c1 0.05 0.15 c2 1.35 1.45 d 0.17 0.27 e 0.45 0.75 f 0.17 0.23 g 0.50 bsc j 0.09 0.20 k 0.50 ref p 0.25 bsc r1 0.13 0.20 r2 0.13 0.20 s 22.00 bsc s1 11.00 bsc v 22.00 bsc v1 11.00 bsc y 0.25 ref z 1.00 ref aa 0.09 0.16 q0 q 0 7 q 11 13 1 2 notes: 1. dimensions and tolerancing per asme y14.5m, 1994. 2. dimensions in millimeters. 3. datums l, m, n to be determined at the seating plane, datum t. 4. dimensions s and v to be determined at seating plane, datum t. 5. dimensions a and b do not include mold protrusion. allowable protrusion is 0.25 per side. dimensions a and b do include mold mismatch and are determined at datum plane h. 6. dimension d does not include dambar protrusion. allowable dambar protrusion shall not cause the d dimension to exceed 0.35. 0.05 c l (z) r2 e c2 (y) r1 (k) c1 1 q 0.25 view ab n 0.20 t l-m m l n 2 q t t 144x x x=l, m or n f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . advance information mmc2114 MMC2113 mmc2112 ? rev. 1.0 644 mechanical specifications motorola mechanical specifications 24.8 100-pin lqfp mechanical drawing dim a min max 14.00 bsc millimeters a1 7.00 bsc b 14.00 bsc b1 7.00 bsc c 1.70 c1 0.05 0.20 c2 1.30 1.50 d 0.10 0.30 e 0.45 0.75 f 0.15 0.23 g 0.50 bsc j 0.07 0.20 k 0.50 ref r1 0.08 0.20 s 16.00 bsc s1 8.00 bsc u 0.09 0.16 v 16.00 bsc v1 8.00 bsc w 0.20 ref z 1.00 ref q0 7 q 0 q 12 ref q notes: 1. dimensions and tolerances per asme y14.5m, 1994. 2. dimensions in millimeters. 3. datums l, m and n to be determined at the seating plane, datum t. 4. dimensions s and v to be determined at seating plane, datum t. 5. dimensions a and b do not include mold protrusion. allowable protrusion is 0.25 per side. dimensions a and b include mold mismatch. 6. dimension d does not include dambar protrusion. dambar protrusion shall not cause the lead width to exceed 0.35. minimum space between protrusion and adjacent lead or protrusion 0.07. 1 2 3 n 0.2 t l-m 0.08 t c2 c1 (k) (z) (w) gage plane view aa view y ab plating u j d f rotated 90 clockwise base metal section ab-ab 0.05 e 0.25 c l l-m m 0.08 n t 3x 3 q 4x 1 q 2x r r1 q x = l, m or n g a s a1 s1 b1 v1 b v --- --- n 0.2 t l-m m n t seating 2 q 4x 100x plane x ab l 12 ref f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . mechanical specifications 196-ball mapbga mechanical drawing mmc2114 MMC2113 mmc2112 ? rev. 1.0 advance information motorola mechanical specifications 645 24.9 196-ball mapbga mechanical drawing notes: 1. dimensions are in millimeters. 2. interpret dimensions innd tolerances per asme y14.5m, 1994. 3. dimension b is measured at the maximum solder ball diameter, parallel to datum plane z. 4. datum z (seating plane) is defined by the spherical crowns of the solder balls. 5. parallelism measurement shall exclude any effect of mark on top surface of package. dim min max millimeters a 1.25 1.60 a1 0.27 0.47 a2 1.16 ref b 0.45 0.55 d 15.00 bsc e 15.00 bsc e 1.00 bsc s 0.50 bsc 3 x m 0.15 y z m 0.08 z z 13x e a1 a2 196x s 13x e s 196x b laser mark for metalized mark for pin a1 pin a1 identification in this area identification in thisarea k view m-m 1413121110 9 a b 654321 c d e f g h j k l m n p e d y x 0.15 z 0.20 m m z 0.10 5 4 a detail k rotated 90 clockwise f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . advance information mmc2114 MMC2113 mmc2112 ? rev. 1.0 646 mechanical specifications motorola mechanical specifications f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . mmc2114 MMC2113 mmc2112 ? rev. 1.0 advance information motorola ordering information 647 advance information ? mmc2114, MMC2113, and mmc2112 section 25. ordering information 25.1 contents 25.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .647 25.3 mc order numbers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .647 25.2 introduction this section contains instructions for ordering the mmc2114, MMC2113, and mmc2112. 25.3 mc order numbers table 25-1. mc order numbers mc order number (1) 1. pu = 100-pin 14 x 14 mm low-profile quad flat pack (lqfp) pv = 144-pin 20 x 20 mm lqfp vf = 196-pin plastic molded array process ball grid array (mapbga) operating temperature range mmc2114cfcpu33 MMC2113cfcpu33 ? 40 c to +85 c mmc2114cfcpv33 MMC2113cfcpv33 mmc2112ccpv33 ? 40 c to +85 c mmc2114cfcvf33 MMC2113cfcvf33 mmc2112ccvf33 ? 40 c to +85 c f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . advance information mmc2114 MMC2113 mmc2112 ? rev. 1.0 648 ordering information motorola ordering information f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . mmc2114 MMC2113 mmc2112 ? rev. 1.0 advance information motorola security 649 advance information ? mmc2114, MMC2113, and mmc2112 appendix a. security a.1 contents a.2 security philosophy/strategy . . . . . . . . . . . . . . . . . . . . . . . . .649 a.3 mcu operation with security enabled . . . . . . . . . . . . . . . . . .650 a.4 flash access blocking mechanisms . . . . . . . . . . . . . . . . . .650 a.4.1 forced operating mode selection . . . . . . . . . . . . . . . . . . .650 a.4.2 disabled once access . . . . . . . . . . . . . . . . . . . . . . . . . . . 651 a.2 security philosophy/strategy members of the m core microcontroller family with the sgfm (second generation flash for m core) module incorporate features that prevent unauthorized users from reading the contents of the sgfm array. the security mechanism comprises several hardware interlocks that block the means by which an unauthorized user could gain access to the flash array. apart from dedicated non-volatile memory bits in the sgfm array that engage security, the interlocking mechanism consists exclusively of digital logic constructs that require no special processing. thorough mcu security must incorporate both hardware and software considerations. while the MMC2113 and mmc2114 provide the necessary hardware interlocks, it is incumbent upon the user to write software that minimizes the potential for unauthorized code and data access. in particular, if firmware-based debug, diagnostic, or update interfaces are needed, they should be protected with passwords that are not easily compromised. even brute force hacking attempts can be foiled by incorporating exponential time delays after failed password entries. when used together, the flash back door security key and an appropriately defined software construct can provide both password protection and product identification or serialization features. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . advance information mmc2114 ? MMC2113 mmc2112 ? rev. 1.0 650 security motorola security a.3 mcu operation with security enabled once the flash has been programmed with application code, the mcu can be secured by programming the security bytes located in the sgfm configuration field. these non-volatile bytes will keep the mcu secure through reset and power down. only two bytes within this field are used to enable or disable security. refer to the section 10. second generation flash for m?core (sgfm) for the state of the security bytes and the resulting state of security. when flash security is enabled, the mcu will boot only in single-chip mode and will fetch its reset vector from address 0x0000_0000 of the on-chip flash. the m core cpu will fetch and execute opcodes from the on-chip flash or on-chip sram if user code is copied there. normal program execution is not affected by enabling flash security. a.4 flash access blocking mechanisms m core microcontrollers have several operating functional and test modes. effective flash security must address operating mode selection and anticipate modes in which the on-chip flash can be compromised and read without explicit user permission. blocking the two currently identified means for doing this are outlined in the subsections that follow. a.4.1 forced operating mode selection the chip configuration module (ccm) determines, at boot time, in which of the four functional modes the mcu will operate. these modes are: master mode single-chip mode emulation mode factory access slave test (fast) mode f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . security mmc2114 MMC2113 mmc2112 ? rev. 1.0 advance information motorola security 651 when flash security is enabled, the mcu will boot only in single-chip mode and will fetch its reset vector from address 0x0000_0000 of the on-chip flash. this security affords protection only to applications in which the mcu operates in single-chip mode. operating in any other mode would make the external bus interface (ebi) available and would be inherently insecure. when security is enabled, any attempt to override the default single-chip operating mode by asserting the reset configuration (rcon ) pin in conjunction with mode select inputs d26, d17, and d16 will be ignored. when security is enabled, override will be allowed only for the rpllsel, rpllref, and rload bits in the rcon register. these bits are overridden by asserting rcon in conjunction with appropriate logic levels applied to the d[23:22] pins (rpllsel and rpllref) and the d21 pin (rload). the override inputs for all other rcon bits will be ignored. a.4.2 disabled once access on-chip flash can be read by issuing commands across the once port which is the debug interface for the m core cpu. the trst , tclk, tms, tdo, and tdi pins comprise a jtag (joint test action group) interface onto which the once port functionality is mapped. when the mcu boots, the top level jtag tap (test access port) is active and provides the chip ? s boundary scan capability and access to its id register. once port features are enabled by: asserting the debug enable (de ) input for two tclk periods when trst is negated shifting the enable_mcu_once command into the tap controller ? s instruction register (ir), entering the update_ir state and returning to the run_test/idle state. proper implementation of flash security requires that no access to the once port is provided when security is enabled. once port access is f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . advance information mmc2114 MMC2113 mmc2112 ? rev. 1.0 652 security motorola security blocked in such a way that the jtag boundary scan feature is still usable when security is enabled. please refer to section 22. jtag test access port and once for further information on boundary scan operation. if security is inadvertently enabled on the mcu, a lockout recovery mechanism allows the on-chip flash to be completely erased (including the configuration field), thus disabling security. this does not compromise security as all flash physical blocks are erased before security is disabled during the next reset or power-up sequence. to activate lockout recovery, the jtag public instruction lockout_recovery must first be shifted into the top level tap controller ? s instruction register. the lockout_recovery instruction has an associated 7-bit data register that is used to control the clock divider circuit within the sgfm module. this divider controls the frequency of the sgfm state machine clock and must be set with an appropriate value before the lockout recovery sequence can begin. refer to section 10. second generation flash for m core (sgfm) for more details on setting this register value. once the lockout_recovery instruction has been shifted into the instruction register, the clock divider value must be shifted into the corresponding 7-bit data register. after the data register has been updated, the user must transition the tap controller into the run-test/idle state for the lockout recovery sequence to commence. the controller must remain in the run-test/idle state until the erase sequence is complete. see section 22. jtag test access port and once for further details on controlling transitions of the tap controller. it is important to note that the lockout_recovery instruction is only effective on a secured mcu. using this instruction on an unsecured device has no effect. note: once the lockout recovery sequence is complete, both the jtag tap controller (by asserting trst ) and the mcu (by asserting reset ) must be reset to resume normal unsecured operation. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . how to reach us: usa/europe/locations not listed: motorola literature distribution; p.o. box 5405, denver, colorado 80217 1-303-675-2140 or 1-800-441-2447 japan: motorola japan ltd.; sps, technical information center, 3-20-1, minami-azabu minato-ku, tokyo 106-8573 japan 81-3-3440-3569 asia/pacific: motorola semiconductors h.k. ltd.; silicon harbour centre, 2 dai king street, tai po industrial estate, tai po, n.t., hong kong 852-26668334 technical information center: 1-800-521-6274 home page: http://www.motorola.com/semiconductors information in this document is provided solely to enable system and software implementers to use motorola products. there are no express or implied copyright licenses granted hereunder to design or fabricate any integrated circuits or integrated circuits based on the information in this document. motorola reserves the right to make changes without further notice to any products herein. motorola makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does motorola assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. ? typical ? parameters which may be provided in motorola data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. all operating parameters, including ? typicals ? must be validated for each customer application by customer ? s technical experts. motorola does not convey any license under its patent rights nor the rights of others. motorola products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the motorola product could create a situation where personal injury or death may occur. should buyer purchase or use motorola products for any such unintended or unauthorized application, buyer shall indemnify and hold motorola and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that motorola was negligent regarding the design or manufacture of the part. motorola and the stylized m logo are registered in the u.s. patent and trademark office. digital dna is a trademark of motorola, inc. all other product or service names are the property of their respective owners. motorola, inc. is an equal opportunity/affirmative action employer. ? motorola, inc. 2002 mmc2114/d f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . |
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